void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
-/*************/
-/* Utilities */
-/*************/
-
-#undef adf_os_cpu_to_le16
-
-static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
-{
- return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
-}
-
/*
* Extend a 32 bit TSF to 64 bit, taking wrapping into account.
*/
static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
{
+ struct ath_hal *ah = sc->sc_ah;
u_int64_t tsf;
u_int32_t tsf_low;
u_int64_t tsf64;
- tsf = ath_hal_gettsf64(sc->sc_ah);
+ tsf = ah->ah_getTsf64(ah);
tsf_low = tsf & 0xffffffff;
tsf64 = (tsf & ~0xffffffffULL) | rstamp;
ds->ds_link = 0;
adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
- ath_hal_setuprxdesc(ah, ds,
- adf_nbuf_tailroom(ds->ds_nbuf),
- 0);
+ ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
if (sc->sc_rxlink == NULL) {
- ath_hal_putrxbuf(ah, ds->ds_daddr);
+ ah->ah_setRxDP(ah, ds->ds_daddr);
}
else {
*sc->sc_rxlink = ds->ds_daddr;
}
sc->sc_rxlink = &ds->ds_link;
- ath_hal_rxena(ah);
+ ah->ah_enableReceive(ah);
return 0;
}
((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
- tsf = ath_hal_gettsf64(ah);
+ tsf = ah->ah_getTsf64(ah);
bf = asf_tailq_first(&sc->sc_rxbuf);
ds = asf_tailq_first(&sc->sc_rxdesc);
continue;
}
- retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr,
+ retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
if (HAL_EINPROGRESS == retval) {
break;
}
ds = asf_tailq_first(&sc->sc_rxdesc);
- ath_hal_putrxbuf(ah, ds->ds_daddr);
+ ah->ah_setRxDP(ah, ds->ds_daddr);
return 0;
}
} while(1);
sc->sc_imask |= HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
}
/*******************/
rt = sc->sc_currates;
rate = rt->info[rix].rateCode;
- ath_hal_setuptxdesc(ah, ds
+ ah->ah_setupTxDesc(ds
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, sizeof(struct ieee80211_frame)
, HAL_PKT_TYPE_BEACON
, MAX_RATE_POWER
, rate, 1
, HAL_TXKEYIX_INVALID
- , 0
, flags
, 0
- , 0
- , 0
- , 0
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , 0);
- ath_hal_filltxdesc(ah, ds
+ ah->ah_fillTxDesc(ds
, asf_roundup(adf_nbuf_len(skb), 4)
, AH_TRUE
, AH_TRUE
series[0].Rate = rate;
series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
series[0].RateFlags = 0;
- ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0);
+ ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
}
static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
- ath_hal_stoptxdma(ah, sc->sc_bhalq);
- ath_hal_puttxbuf(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
- ath_hal_txstart(ah, sc->sc_bhalq);
+ ah->ah_stopTxDma(ah, sc->sc_bhalq);
+ ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
+ ah->ah_startTxDma(ah, sc->sc_bhalq);
}
/******/
{
struct ath_hal *ah = sc->sc_ah;
- (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
+ ah->ah_stopTxDma(ah, txq->axq_qnum);
}
static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
ath_tx_status_clear(sc);
sc->sc_tx_draining = 1;
- (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
+ ah->ah_stopTxDma(ah, sc->sc_bhalq);
for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
if (ATH_TXQ_SETUP(sc, i))
a_uint32_t tmp;
#ifdef ATH_ENABLE_CABQ
- tsf = ath_hal_gettsf64(ah);
+ tsf = ah->ah_getTsf64(ah);
tmp = tsf - sc->sc_swba_tsf;
if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
if (sc->sc_invalid)
return ADF_OS_IRQ_NONE;
- if (!ath_hal_intrpend(ah))
+ if (!ah->ah_isInterruptPending(ah))
return ADF_OS_IRQ_NONE;
- ath_hal_getisr(ah, &status);
+ ah->ah_getPendingInterrupts(ah, &status);
status &= sc->sc_imask;
if (status & HAL_INT_FATAL) {
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
} else {
if (status & HAL_INT_SWBA) {
WMI_SWBA_EVENT swbaEvt;
struct ath_txq *txq = ATH_TXQ(sc, 8);
- swbaEvt.tsf = ath_hal_gettsf64(ah);
- swbaEvt.beaconPendingCount = ath_hal_numtxpending(ah, sc->sc_bhalq);
- sc->sc_swba_tsf = ath_hal_gettsf64(ah);
+ swbaEvt.tsf = ah->ah_getTsf64(ah);
+ swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
+ sc->sc_swba_tsf = ah->ah_getTsf64(ah);
wmi_event(sc->tgt_wmi_handle,
WMI_SWBA_EVENTID,
ath_uapsd_processtriggers(sc);
sc->sc_imask &= ~HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
}
if (status & HAL_INT_TXURN) {
sc->sc_int_stats.ast_txurn++;
- ath_hal_updatetxtriglevel(ah, AH_TRUE);
+ ah->ah_updateTxTrigLevel(ah, AH_TRUE);
}
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
sc->sc_imask |= HAL_INT_BMISS;
}
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
sc->sc_imask |= HAL_INT_GTT;
- if (ath_hal_htsupported(ah))
+ if (ath_hal_getcapability(ah, HAL_CAP_HT))
sc->sc_imask |= HAL_INT_CST;
adf_os_setup_intr(sc->sc_dev, ath_intr);
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
t = (struct registerWrite *)(data+i);
if( t->reg > 0xffff ) {
- a_uint32_t *pReg = (a_uint32_t *)t->reg;
-
- *pReg = t->val;
-
+ HAL_WORD_REG_WRITE(t->reg, t->val);
#if defined(PROJECT_K2)
if( t->reg == 0x50040 ) {
static uint8_t flg=0;
#if defined(PROJECT_K2)
if( t->reg == 0x7014 ) {
static uint8_t resetPLL = 0;
- a_uint32_t *pReg;
if( resetPLL == 0 ) {
- t->reg = 0x50044;
- pReg = (a_uint32_t *)t->reg;
- *pReg = 0;
+ /* here we write to core register */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ /* and here to mac register */
ath_hal_reg_write_target(ah, 0x786c,
ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
ath_hal_reg_write_target(ah, 0x786c,
ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
- *pReg = 0x20;
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
resetPLL = 1;
}
- t->reg = 0x7014;
}
#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
if( t->reg == 0x7014 ){
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
{
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
+ struct ath_hal *ah = sc->sc_ah;
- ath_hal_aborttxdma(sc->sc_ah);
+ ah->ah_abortTxDma(sc->sc_ah);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
q = *(a_uint32_t *)data;
q = adf_os_ntohl(q);
- ath_hal_stoptxdma(ah, q);
+ ah->ah_stopTxDma(ah, q);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- ath_hal_stoppcurecv(ah);
- ath_hal_setrxfilter(ah, 0);
- ath_hal_stopdmarecv(ah);
+ ah->ah_stopPcuReceive(ah);
+ ah->ah_setRxFilter(ah, 0);
+ ah->ah_stopDmaReceive(ah);
sc->sc_rxlink = NULL;
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
struct ath_hal *ah = sc->sc_ah;
ath_desc_free(sc);
- ath_hal_detach(ah);
+ ah->ah_detach(ah);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
adf_os_mem_free(sc);
}
ath_tgt_txq_setup(sc);
sc->sc_imask =0;
- ath_hal_intrset(ah,0);
+ ah->ah_setInterrupts(ah, 0);
return 0;
bad:
bad2:
ath_desc_free(sc);
if (ah)
- ath_hal_detach(ah);
+ ah->ah_detach(ah);
}
static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
projects / open-ath9k-htc-firmware.git / blobdiff