remove ath_hal_reg_read_target and OS_REG_READ

[open-ath9k-htc-firmware.git] / target_firmware / wlan / if_ath.c

diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c
index 3cc61f7f29f094db4f2fa358e7668a0de3ba70ab..6a887126e446bdb8c9367671d50ade70105395f8 100755 (executable)
--- a/target_firmware/wlan/if_ath.c
+++ b/target_firmware/wlan/if_ath.c
@@ -1384,17 +1384,17 @@ static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
 {
        if ((addr & 0xffffe000) == 0x2000) {
                /* SEEPROM registers */
-               ath_hal_reg_read_target(ah, addr);
+               ioread32_mac(addr);
                if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
                        adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
 
-               return (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
+               return ioread32_mac(0x407c) & 0x0000ffff;
        } else if (addr > 0xffff)
                /* SoC registers */
                return HAL_WORD_REG_READ(addr);
        else
                /* MAC registers */
-               return ath_hal_reg_read_target(ah, addr);
+               return ioread32_mac(addr);
 }
 
 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
@@ -1427,17 +1427,17 @@ static void ath_pll_reset_ones(struct ath_hal *ah)
                HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
                /* and here to mac register */
                ath_hal_reg_write_target(ah, 0x786c,
-                        ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
+                        ioread32_mac(0x786c) | 0x6000000);
                ath_hal_reg_write_target(ah, 0x786c,
-                        ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
+                        ioread32_mac(0x786c) & (~0x6000000));
 
                HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
 
 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
                ath_hal_reg_write_target(ah, 0x7890,
-                        ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
+                        ioread32_mac(0x7890) | 0x1800000);
                ath_hal_reg_write_target(ah, 0x7890,
-                        ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
+                        ioread32_mac(0x7890) & (~0x1800000));
 #endif
                reset_pll = 1;
        }