HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
{
- a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+ a_uint32_t host_isr =
+ ioread32_mac(AR_INTR_ASYNC_CAUSE);
/*
* Some platforms trigger our ISR before applying power to
* the card, so make sure.
HAL_BOOL fatal_int = AH_FALSE;
a_uint32_t sync_cause;
- if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
- if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
+ if (ioread32_mac(AR_INTR_ASYNC_CAUSE)
+ & AR_INTR_MAC_IRQ) {
+ if ((ioread32_mac(AR_RTC_STATUS)
+ & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
*masked = 0;
return AH_FALSE;
}
return AH_FALSE;
}
#endif
- isr = OS_REG_READ(ah, AR_ISR_RAC);
+ isr = ioread32_mac(AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = 0;
return AH_FALSE;
if (isr & AR_ISR_BCNMISC) {
a_uint32_t s2_s;
- s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
+ s2_s = ioread32_mac(AR_ISR_S2_S);
if (s2_s & AR_ISR_S2_GTT) {
*masked |= HAL_INT_GTT;
a_uint32_t s0_s, s1_s;
*masked |= HAL_INT_TX;
- s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
- s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
+ s0_s = ioread32_mac(AR_ISR_S0_S);
+ s1_s = ioread32_mac(AR_ISR_S1_S);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
}
#ifndef AR9100
- sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+ sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE);
fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
- (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
- AH_TRUE : AH_FALSE;
+ (sync_cause & (AR_INTR_SYNC_HOST1_FATAL
+ | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE;
if (AH_TRUE == fatal_int) {
- OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
- (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
+ iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause);
+ (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR);
}
#endif
return AH_TRUE;
a_uint32_t mask;
if (omask & HAL_INT_GLOBAL) {
- OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
- (void) OS_REG_READ(ah, AR_IER);
+ iowrite32_mac(AR_IER, AR_IER_DISABLE);
+ (void) ioread32_mac(AR_IER);
}
mask = ints & HAL_INT_COMMON;
mask |= AR_IMR_BCNMISC;
}
- OS_REG_WRITE(ah, AR_IMR, mask);
- (void) OS_REG_READ(ah, AR_IMR);
+ iowrite32_mac(AR_IMR, mask);
+ (void) ioread32_mac(AR_IMR);
ahp->ah_maskReg = ints;
/* Re-enable interrupts if they were enabled before. */
if (ints & HAL_INT_GLOBAL) {
- OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+ iowrite32_mac(AR_IER, AR_IER_ENABLE);
/* See explanation above... */
- (void) OS_REG_READ(ah, AR_IER);
+ (void) ioread32_mac(AR_IER);
}
- OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
- OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
- OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
+ iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
+ iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+ iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
return omask;
}
{
u_int64_t tsf;
- tsf = OS_REG_READ(ah, AR_TSF_U32);
- tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
+ tsf = ioread32_mac(AR_TSF_U32);
+ tsf = (tsf << 32) | ioread32_mac(AR_TSF_L32);
return tsf;
}
/******/
void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
{
- OS_REG_WRITE(ah, AR_RXDP, rxdp);
- HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
+ iowrite32_mac(AR_RXDP, rxdp);
+ HALASSERT(ioread32_mac(AR_RXDP) == rxdp);
}
HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
{
- OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
+ iowrite32_mac(AR_CR, AR_CR_RXD); /* Set receive disable bit */
if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
return AH_FALSE;
} else {
{
a_uint32_t phybits;
- OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
+ iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
phybits = 0;
if (bits & HAL_RX_FILTER_PHYRADAR)
phybits |= AR_PHY_ERR_RADAR;
if (bits & HAL_RX_FILTER_PHYERR)
phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
- OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
+ iowrite32_mac(AR_PHY_ERR, phybits);
if (phybits) {
- OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
+ iowrite32_mac(AR_RXCFG,
+ ioread32_mac(AR_RXCFG)
+ | AR_RXCFG_ZLFDMA);
} else {
- OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
+ iowrite32_mac(AR_RXCFG,
+ ioread32_mac(AR_RXCFG)
+ & ~AR_RXCFG_ZLFDMA);
}
}
void ar5416EnableReceive(struct ath_hal *ah)
{
- OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
+ iowrite32_mac(AR_CR, AR_CR_RXE);
}
void ar5416StopPcuReceive(struct ath_hal *ah)
* once and picked it up again...make sure the hw has moved on.
*/
if ((ands->ds_rxstatus8 & AR_RxDone) == 0
- && OS_REG_READ(ah, AR_RXDP) == pa)
+ && ioread32_mac(AR_RXDP) == pa)
return HAL_EINPROGRESS;
/*
*/
omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
- txcfg = OS_REG_READ(ah, AR_TXCFG);
+ txcfg = ioread32_mac(AR_TXCFG);
curLevel = MS(txcfg, AR_FTRIG);
newLevel = curLevel;
} else if (curLevel > MIN_TX_FIFO_THRESHOLD)
newLevel--;
if (newLevel != curLevel)
- OS_REG_WRITE(ah, AR_TXCFG,
- (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
+ iowrite32_mac(AR_TXCFG,
+ (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
/* re-enable chip interrupts */
ar5416SetInterrupts(ah, omask);
* Make sure that TXE is deasserted before setting the TXDP. If TXE
* is still asserted, setting TXDP will have no effect.
*/
- HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
+ HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0);
- OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
+ iowrite32_mac(AR_QTXDP(q), txdp);
return AH_TRUE;
}
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
/* Check to be sure we're not enabling a q that has its TXD bit set. */
- HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
+ HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0);
- OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
+ iowrite32_mac(AR_Q_TXE, 1 << q);
return AH_TRUE;
}
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
- npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
+ npend = ioread32_mac(AR_QSTS(q))
+ & AR_Q_STS_PEND_FR_CNT;
if (npend == 0) {
/*
* Pending frame count (PFC) can momentarily go to zero
* while TXE remains asserted. In other words a PFC of
* zero is not sufficient to say that the queue has stopped.
*/
- if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
+ if (ioread32_mac(AR_Q_TXE) & (1 << q))
npend = 1;
}
#ifdef DEBUG
if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
- if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
+ if (ioread32_mac(AR_Q_RDYTIMESHDN)
+ & (1 << q)) {
isrPrintf("RTSD on CAB queue\n");
/* Clear the ReadyTime shutdown status bits */
- OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
+ iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q);
}
}
#endif
/*
* set txd on all queues
*/
- OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
+ iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M);
/*
* set tx abort bits
/*
* clear txd
*/
- OS_REG_WRITE(ah, AR_Q_TXD, 0);
+ iowrite32_mac(AR_Q_TXD, 0);
return AH_TRUE;
}
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
- OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
+ iowrite32_mac(AR_Q_TXD, 1 << q);
for (i = 1000; i != 0; i--) {
if (ar5416NumTxPending(ah, q) == 0)
break;
OS_DELAY(100); /* XXX get actual value */
}
- OS_REG_WRITE(ah, AR_Q_TXD, 0);
+ iowrite32_mac(AR_Q_TXD, 0);
return (i != 0);
}
ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
}
-void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds,
a_uint32_t burstDuration)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
}
-void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
+void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds,
a_uint32_t vmf)
{
struct ar5416_desc *ads = AR5416DESC(ds);
projects / open-ath9k-htc-firmware.git / blobdiff