HAL_CAP_VEOL = 0,
HAL_CAP_BSSIDMASK = 1,
HAL_CAP_TSF_ADJUST = 2,
- HAL_CAP_RX_STBC = 3,
- HAL_CAP_TX_STBC = 4,
HAL_CAP_HT = 5,
HAL_CAP_RTS_AGGR_LIMIT = 6,
} HAL_CAPABILITY_TYPE;
-typedef enum {
- HAL_M_STA = 1,
- HAL_M_IBSS = 0,
- HAL_M_HOSTAP = 6,
- HAL_M_MONITOR = 8,
-} HAL_OPMODE;
-
typedef enum {
HAL_TX_QUEUE_INACTIVE = 0,
HAL_TX_QUEUE_DATA = 1,
struct ath_tx_desc *ds, a_uint32_t aggrLen,
a_uint32_t numDelims);
void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *ah,
- struct ath_desc *ds, a_uint32_t numDelims);
+ struct ath_tx_desc *ds, a_uint32_t numDelims);
void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *ah,
- struct ath_desc *ds);
+ struct ath_tx_desc *ds);
void __ahdecl(*ah_clr11nAggr)(struct ath_hal *ah,
struct ath_tx_desc *ds);
void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *ah,