add new ZM_SOC_USB_DMA_RESET_OFFSET register

[open-ath9k-htc-firmware.git] / target_firmware / magpie_fw_dev / target / init / init.c

diff --git a/target_firmware/magpie_fw_dev/target/init/init.c b/target_firmware/magpie_fw_dev/target/init/init.c
index b6e6a4456c8b860dee9575e945f74938f34994a8..8fc464006ba7805f7d49a6b594650083c7442df1 100755 (executable)
--- a/target_firmware/magpie_fw_dev/target/init/init.c
+++ b/target_firmware/magpie_fw_dev/target/init/init.c
@@ -35,10 +35,10 @@
 #if defined(_RAM_)
 
 #include "athos_api.h"
-    
+#include "usb_defs.h"
+
 #if defined(PROJECT_MAGPIE)
 #include "regdump.h"
-#include "usb_defs.h"
 extern  uint32_t *init_htc_handle;
 uint8_t htc_complete_setup = 0;
 void reset_EP4_FIFO(void);
@@ -145,12 +145,12 @@ void exception_reset(struct register_dump_s *dump)
        HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR,
                           (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1));
 
-       HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0);
+       USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, 0x0);
        HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|BIT4);
        A_DELAY_USECS(5);
        HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)&~BIT4);
        A_DELAY_USECS(5);
-       HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1);
+       USB_WORD_REG_WRITE(ZM_SOC_USB_DMA_RESET_OFFSET, BIT0);
 
        // set clock to bypass mode - 40Mhz from XTAL
        HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4));