carl9170: fix total error filter bit handling

[carl9170fw.git] / include / shared / wlan.h

diff --git a/include/shared/wlan.h b/include/shared/wlan.h
index 35e2e4f884850bfce009a3252e82b455f8f34946..24d63b583b6b08459d657055d70836c621106177 100644 (file)
--- a/include/shared/wlan.h
+++ b/include/shared/wlan.h
@@ -1,7 +1,7 @@
 /*
- * Atheros AR9170 driver
+ * Shared Atheros AR9170 Header
  *
- * Hardware-specific definitions
+ * RX/TX meta descriptor format
  *
  * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
  * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
@@ -56,7 +56,8 @@
 
 #define        AR9170_RX_ENC_SOFTWARE                  0x8
 
-#define        AR9170_RX_STATUS_MODULATION_MASK        0x03
+#define        AR9170_RX_STATUS_MODULATION             0x03
+#define        AR9170_RX_STATUS_MODULATION_S           0
 #define        AR9170_RX_STATUS_MODULATION_CCK         0x00
 #define        AR9170_RX_STATUS_MODULATION_OFDM        0x01
 #define        AR9170_RX_STATUS_MODULATION_HT          0x02
@@ -66,12 +67,16 @@
 #define        AR9170_RX_STATUS_SHORT_PREAMBLE         0x08
 #define        AR9170_RX_STATUS_GREENFIELD             0x08
 
-#define        AR9170_RX_STATUS_MPDU_MASK              0x30
+#define        AR9170_RX_STATUS_MPDU                   0x30
+#define        AR9170_RX_STATUS_MPDU_S                 4
 #define        AR9170_RX_STATUS_MPDU_SINGLE            0x00
 #define        AR9170_RX_STATUS_MPDU_FIRST             0x20
 #define        AR9170_RX_STATUS_MPDU_MIDDLE            0x30
 #define        AR9170_RX_STATUS_MPDU_LAST              0x10
 
+#define        AR9170_RX_STATUS_CONT_AGGR              0x40
+#define        AR9170_RX_STATUS_TOTAL_ERROR            0x80
+
 #define        AR9170_RX_ERROR_RXTO                    0x01
 #define        AR9170_RX_ERROR_OVERRUN                 0x02
 #define        AR9170_RX_ERROR_DECRYPT                 0x04
@@ -79,12 +84,11 @@
 #define        AR9170_RX_ERROR_WRONG_RA                0x10
 #define        AR9170_RX_ERROR_PLCP                    0x20
 #define        AR9170_RX_ERROR_MMIC                    0x40
-#define        AR9170_RX_ERROR_FATAL                   0x80
 
 /* these are either-or */
 #define        AR9170_TX_MAC_PROT_RTS                  0x0001
 #define        AR9170_TX_MAC_PROT_CTS                  0x0002
-#define        AR9170_TX_MAC_PROT_MASK                 0x0003
+#define        AR9170_TX_MAC_PROT                      0x0003
 
 #define        AR9170_TX_MAC_NO_ACK                    0x0004
 /* if unset, MAC will only do SIFS space before frame */
@@ -229,6 +233,13 @@ struct ar9170_tx_hw_phy_control {
        } __packed;
 } __packed;
 
+struct ar9170_tx_rate_info {
+       u8 tries:3;
+       u8 erp_prot:2;
+       u8 ampdu:1;
+       u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */
+} __packed;
+
 struct carl9170_tx_superdesc {
        __le16 len;
        u8 rix;
@@ -239,12 +250,13 @@ struct carl9170_tx_superdesc {
        u8 ampdu_commit_density:1;
        u8 ampdu_commit_factor:1;
        u8 ampdu_unused_bit:1;
-       u8 queue:3;
+       u8 queue:2;
+       u8 reserved:1;
        u8 vif_id:3;
        u8 fill_in_tsf:1;
        u8 cab:1;
        u8 padding2;
-       u8 tries[CARL9170_TX_MAX_RATES];
+       struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES];
        struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES];
 } __packed;
 
@@ -285,13 +297,20 @@ struct _ar9170_tx_hwdesc {
 #define        CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR           0x40
 #define        CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S         6
 
-#define CARL9170_TX_SUPER_MISC_QUEUE                   0x7
+#define CARL9170_TX_SUPER_MISC_QUEUE                   0x3
 #define CARL9170_TX_SUPER_MISC_QUEUE_S                 0
 #define        CARL9170_TX_SUPER_MISC_VIF_ID                   0x38
 #define        CARL9170_TX_SUPER_MISC_VIF_ID_S                 3
 #define        CARL9170_TX_SUPER_MISC_FILL_IN_TSF              0x40
 #define        CARL9170_TX_SUPER_MISC_CAB                      0x80
 
+#define CARL9170_TX_SUPER_RI_TRIES                     0x7
+#define CARL9170_TX_SUPER_RI_TRIES_S                   0
+#define CARL9170_TX_SUPER_RI_ERP_PROT                  0x18
+#define CARL9170_TX_SUPER_RI_ERP_PROT_S                        3
+#define CARL9170_TX_SUPER_RI_AMPDU                     0x20
+#define CARL9170_TX_SUPER_RI_AMPDU_S                   5
+
 struct _carl9170_tx_superdesc {
        __le16 len;
        u8 rix;
@@ -300,7 +319,7 @@ struct _carl9170_tx_superdesc {
        u8 ampdu_settings;
        u8 misc;
        u8 padding;
-       u8 tries[CARL9170_TX_MAX_RATES];
+       u8 ri[CARL9170_TX_MAX_RATES];
        __le32 rr[CARL9170_TX_MAX_RETRY_RATES];
 } __packed;
 
@@ -312,13 +331,15 @@ struct _carl9170_tx_superframe {
 
 #define        CARL9170_TX_SUPERDESC_LEN               24
 #define        AR9170_TX_HWDESC_LEN                    8
-#define        AR9170_TX_SUPERFRAME_LEN                (CARL9170_TX_HWDESC_LEN + \
-                                                AR9170_TX_SUPERDESC_LEN)
+#define        CARL9170_TX_SUPERFRAME_LEN              (CARL9170_TX_SUPERDESC_LEN + \
+                                                AR9170_TX_HWDESC_LEN)
 
 struct ar9170_rx_head {
        u8 plcp[12];
 } __packed;
 
+#define        AR9170_RX_HEAD_LEN                      12
+
 struct ar9170_rx_phystatus {
        union {
                struct {
@@ -333,12 +354,16 @@ struct ar9170_rx_phystatus {
        u8 phy_err;
 } __packed;
 
+#define        AR9170_RX_PHYSTATUS_LEN                 20
+
 struct ar9170_rx_macstatus {
        u8 SAidx, DAidx;
        u8 error;
        u8 status;
 } __packed;
 
+#define        AR9170_RX_MACSTATUS_LEN                 4
+
 struct ar9170_rx_frame_single {
        struct ar9170_rx_head phy_head;
        struct ieee80211_hdr i3e;
@@ -386,8 +411,6 @@ enum ar9170_txq {
        AR9170_TXQ_BK,
 
        __AR9170_NUM_TXQ,
-
-       AR9170_TXQ_MGMT = 4,
 };
 
 static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 };