carl9170 firmware: shared register file update

[carl9170fw.git] / include / shared / hw.h

diff --git a/include/shared/hw.h b/include/shared/hw.h
index bde4244011aff2021c6c2e8d5532cd953d52ce06..6961d14fd8b1ece71d2beaafeddb8273c40697dc 100644 (file)
--- a/include/shared/hw.h
+++ b/include/shared/hw.h
@@ -174,6 +174,7 @@
 #define                AR9170_MAC_SNIFFER_ENABLE_PROMISC       BIT(0)
 #define                AR9170_MAC_SNIFFER_DEFAULTS             0x02000000
 #define        AR9170_MAC_REG_ENCRYPTION               (AR9170_MAC_REG_BASE + 0x678)
+#define                AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE  BIT(2)
 #define                AR9170_MAC_ENCRYPTION_RX_SOFTWARE       BIT(3)
 #define                AR9170_MAC_ENCRYPTION_DEFAULTS          0x70
 
@@ -222,6 +223,12 @@
 #define AR9170_MAC_REG_TX_BLOCKACKS            (AR9170_MAC_REG_BASE + 0x6c0)
 #define AR9170_MAC_REG_NAV_COUNT               (AR9170_MAC_REG_BASE + 0x6c4)
 #define AR9170_MAC_REG_BACKOFF_STATUS          (AR9170_MAC_REG_BASE + 0x6c8)
+#define                AR9170_MAC_BACKOFF_CCA                  BIT(24)
+#define                AR9170_MAC_BACKOFF_TX_PEX               BIT(25)
+#define                AR9170_MAC_BACKOFF_RX_PE                BIT(26)
+#define                AR9170_MAC_BACKOFF_MD_READY             BIT(27)
+#define                AR9170_MAC_BACKOFF_TX_PE                BIT(28)
+
 #define        AR9170_MAC_REG_TX_RETRY                 (AR9170_MAC_REG_BASE + 0x6cc)
 
 #define AR9170_MAC_REG_TX_COMPLETE             (AR9170_MAC_REG_BASE + 0x6d4)
@@ -357,7 +364,18 @@
 
 #define AR9170_MAC_REG_DMA_WLAN_STATUS         (AR9170_MAC_REG_BASE + 0xd38)
 #define        AR9170_MAC_REG_DMA_STATUS               (AR9170_MAC_REG_BASE + 0xd3c)
-
+#define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR       (AR9170_MAC_REG_BASE + 0xd40)
+#define        AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR       (AR9170_MAC_REG_BASE + 0xd40)
+#define        AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR       (AR9170_MAC_REG_BASE + 0xd44)
+#define        AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR       (AR9170_MAC_REG_BASE + 0xd48)
+#define        AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR       (AR9170_MAC_REG_BASE + 0xd4c)
+#define        AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR       (AR9170_MAC_REG_BASE + 0xd50)
+#define        AR9170_MAC_REG_DMA_TXQ0Q1_LEN           (AR9170_MAC_REG_BASE + 0xd54)
+#define        AR9170_MAC_REG_DMA_TXQ2Q3_LEN           (AR9170_MAC_REG_BASE + 0xd58)
+#define        AR9170_MAC_REG_DMA_TXQ4_LEN             (AR9170_MAC_REG_BASE + 0xd5c)
+
+#define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR      (AR9170_MAC_REG_BASE + 0xd74)
+#define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR      (AR9170_MAC_REG_BASE + 0xd78)
 #define        AR9170_MAC_REG_TXRX_MPI                 (AR9170_MAC_REG_BASE + 0xd7c)
 #define                AR9170_MAC_TXRX_MPI_TX_MPI_MASK         0x0000000f
 #define                AR9170_MAC_TXRX_MPI_TX_TO_MASK          0x0000fff0