carl9170 firmware: revamp reset code

[carl9170fw.git] / include / shared / hw.h

diff --git a/include/shared/hw.h b/include/shared/hw.h
index 33e856bbb5eb9db26459c8b96c8470015b857542..30b19a7ef312968fb95525dbd0938113d9a55b3a 100644 (file)
--- a/include/shared/hw.h
+++ b/include/shared/hw.h
@@ -445,10 +445,17 @@
 
 #define AR9170_PWR_REG_POWER_STATE             (AR9170_PWR_REG_BASE + 0x000)
 
-#define        AR9170_PWR_REG_ADDA_BB                  (AR9170_PWR_REG_BASE + 0x004)
-#define                AR9170_PWR_ADDA_BB_USB_FIFO_RESET       0x00000005
-#define                AR9170_PWR_ADDA_BB_COLD_RESET           0x00000800
-#define                AR9170_PWR_ADDA_BB_WARM_RESET           0x00000400
+#define        AR9170_PWR_REG_RESET                    (AR9170_PWR_REG_BASE + 0x004)
+#define                AR9170_PWR_RESET_COMMIT_RESET_MASK      BIT(0)
+#define                AR9170_PWR_RESET_WLAN_MASK              BIT(1)
+#define                AR9170_PWR_RESET_DMA_MASK               BIT(2)
+#define                AR9170_PWR_RESET_BRIDGE_MASK            BIT(3)
+#define                AR9170_PWR_RESET_AHB_MASK               BIT(9)
+#define                AR9170_PWR_RESET_BB_WARM_RESET          BIT(10)
+#define                AR9170_PWR_RESET_BB_COLD_RESET          BIT(11)
+#define                AR9170_PWR_RESET_ADDA_CLK_COLD_RESET    BIT(12)
+#define                AR9170_PWR_RESET_PLL                    BIT(13)
+#define                AR9170_PWR_RESET_USB_PLL                BIT(14)
 
 #define        AR9170_PWR_REG_CLOCK_SEL                (AR9170_PWR_REG_BASE + 0x008)
 #define                AR9170_PWR_CLK_AHB_40MHZ                0