carl9170 firmware: merge CARL9170FW_PSM with the standard RF code

[carl9170fw.git] / carlfw / src / rf.c

diff --git a/carlfw/src/rf.c b/carlfw/src/rf.c
index be705a7934b49c75f345e8bb41762ac4ba67982a..10220481d3e8514e04c1ab1010dd73a81ae87538 100644 (file)
--- a/carlfw/src/rf.c
+++ b/carlfw/src/rf.c
@@ -6,7 +6,7 @@
  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
  * Copyright (c) 2007-2009 Atheros Communications, Inc.
  * Copyright   2009    Johannes Berg <johannes@sipsolutions.net>
- * Copyright 2009, 2010 Christian Lamparter <chunkeey@googlemail.com>
+ * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -136,7 +136,7 @@ static uint32_t AGC_calibration(uint32_t loop)
        uint32_t wrdata;
        uint32_t ret;
 
-#define AGC_CAL_NF     (AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF);
+#define AGC_CAL_NF     (AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF)
 
        wrdata = get_async(AR9170_PHY_REG_AGC_CONTROL) | AGC_CAL_NF;
        set(AR9170_PHY_REG_AGC_CONTROL, wrdata);
@@ -144,14 +144,10 @@ static uint32_t AGC_calibration(uint32_t loop)
        ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
 
        /* sitesurvey : 100 ms / current connected 200 ms */
-       while (loop && ret != 0x0) {
-               ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
-
-               if (ret == 0)
-                       break;
-
+       while ((ret != 0) && loop--) {
                udelay(100);
-               loop--;
+
+               ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
        }
 
        /* return the AGC/Noise calibration state to the driver */
@@ -185,10 +181,6 @@ static uint32_t rf_init(const uint32_t delta_slope_coeff_exp,
                set(AR9170_PHY_REG_ANALOG_SWAP, AR9170_PHY_ANALOG_SWAP_AB |
                                                AR9170_PHY_ANALOG_SWAP_ALT_CHAIN);
 
-               /* configure mask */
-               set(AR9170_PHY_REG_RX_CHAINMASK, 0x5);  /* chain 0 + chain 2 */
-               set(AR9170_PHY_REG_CAL_CHAINMASK, 0x5); /* chain 0 + chain 2 */
-
                /* Activate BB */
                set(AR9170_PHY_REG_ACTIVE, AR9170_PHY_ACTIVE_EN);
                delay(10);
@@ -208,9 +200,9 @@ void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
        fw.phy.frequency = cmd->rf_init.freq;
 
        if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
-               clock_set(true, AHB_80_88MHZ);
+               clock_set(AHB_80_88MHZ, true);
        else
-               clock_set(true, AHB_40_44MHZ);
+               clock_set(AHB_40_44MHZ, true);
 
        ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
                      le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),
@@ -221,18 +213,8 @@ void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
 
        resp->hdr.len = sizeof(struct carl9170_rf_init_result);
        resp->rf_init_res.ret = cpu_to_le32(ret);
-
-       resp->rf_init_res.regs[0] = get(AR9170_PHY_REG_CCA);
-       resp->rf_init_res.regs[3] = get(AR9170_PHY_REG_EXT_CCA);
-
-       resp->rf_init_res.regs[1] = get(AR9170_PHY_REG_CH1_CCA);
-       resp->rf_init_res.regs[4] = get(AR9170_PHY_REG_CH1_EXT_CCA);
-
-       resp->rf_init_res.regs[2] = get(AR9170_PHY_REG_CH2_CCA);
-       resp->rf_init_res.regs[5] = get(AR9170_PHY_REG_CH2_EXT_CCA);
 }
 
-#ifdef CONFIG_CARL9170FW_PSM
 void rf_psm(void)
 {
        u32 bank3;
@@ -292,6 +274,5 @@ void rf_psm(void)
 
        set(0x1c58f0, bank3);
 }
-#endif /* CONFIG_CARL9170FW_PSM */
 
 #endif /* CONFIG_CARL9170FW_RADIO_FUNCTIONS */