unbreak allmodconfig KCONFIG_ALLCONFIG=...

[carl9170fw.git] / carlfw / include / timer.h

diff --git a/carlfw/include/timer.h b/carlfw/include/timer.h
index bf2f310ba07f4cf08c64b4083bf40fd8bc996d4f..43d6f2ece5afbf8a79360caf28a9fd9a42c63ca6 100644 (file)
--- a/carlfw/include/timer.h
+++ b/carlfw/include/timer.h
@@ -6,7 +6,7 @@
  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
  * Copyright (c) 2007-2009 Atheros Communications, Inc.
  * Copyright   2009    Johannes Berg <johannes@sipsolutions.net>
- * Copyright 2009, 2010 Christian Lamparter <chunkeey@googlemail.com>
+ * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,8 +19,7 @@
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; If not, see <http://www.gnu.org/licenses/>.
  */
 
 #ifndef __CARL9170FW_TIMER_H
@@ -35,53 +34,57 @@ enum cpu_clock_t {
        AHB_80_88MHZ    = 3
 };
 
-#define AR9170_TICKS_PER_MICROSECOND   80
-
 static inline __inline uint32_t get_clock_counter(void)
 {
        return (get(AR9170_TIMER_REG_CLOCK_HIGH) << 16) | get(AR9170_TIMER_REG_CLOCK_LOW);
 }
 
-static inline __inline bool is_after_msecs(uint32_t t0, uint32_t msecs)
+/*
+ * works only up to 97 secs [44 MHz] or 107 secs for 40 MHz
+ * Also, the delay wait will be affected by 2.4GHz<->5GHz
+ * band changes.
+ */
+static inline __inline bool is_after_msecs(const uint32_t t0, const uint32_t msecs)
 {
-       return (get_clock_counter() - t0) / (AR9170_TICKS_PER_MICROSECOND * 1000) > msecs;
+       return ((get_clock_counter() - t0) / 1000) > (msecs * fw.ticks_per_usec);
 }
 
-static inline __inline void delay(uint32_t msec)
+/*
+ * Note: Be careful with [u]delay. They won't service the
+ * hardware watchdog timer. It might trigger if you
+ * wait long enough. Also they don't terminate if sec is
+ * above 97 sec [44MHz] or more than 107 sec [40MHz].
+ */
+static inline __inline void delay(const uint32_t msec)
 {
-       uint32_t t1, t2, dt;
+       uint32_t t1, t2, dt, wt;
+
+       wt = msec * fw.ticks_per_usec;
 
        t1 = get_clock_counter();
        while (1) {
                t2 = get_clock_counter();
-               dt = (t2 - t1) / AR9170_TICKS_PER_MICROSECOND / 1000;
-               if (dt >= msec)
+               dt = (t2 - t1) / 1000;
+               if (dt >= wt)
                        break;
        }
 }
 
-static inline __inline void udelay(uint32_t usec)
+static inline __inline void udelay(const uint32_t usec)
 {
        uint32_t t1, t2, dt;
 
        t1 = get_clock_counter();
        while (1) {
                t2 = get_clock_counter();
-               dt = (t2 - t1) / AR9170_TICKS_PER_MICROSECOND;
-               if (dt >= usec)
+               dt = (t2 - t1);
+               if (dt >= (usec * fw.ticks_per_usec))
                        break;
        }
 }
 
-static inline void clock_set(const bool on, const enum cpu_clock_t _clock)
-{
-       /*
-        * Word of Warning!
-        * This setting does more than just mess with the CPU Clock.
-        * So watch out, if you need _stable_ timer interrupts.
-        */
-
-       set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | _clock));
-}
+void clock_set(enum cpu_clock_t _clock, bool on);
+void handle_timer(void);
+void timer_init(const unsigned int timer, const unsigned int interval);
 
 #endif /* __CARL9170FW_TIMER_H */