carl9170: add register definitions for EEPROM and SPI controller

Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>

diff --git a/include/shared/hw.h b/include/shared/hw.h
index 139ded8dc6a402d1efe179cb40108452d9ecd22b..08e0ae9c5836dc38d7d4f2d9f5abe71d8af86a66 100644 (file)
--- a/include/shared/hw.h
+++ b/include/shared/hw.h
@@ -453,9 +453,74 @@
 #define        AR9170_MC_REG_BASE                      0x1d1000
 
 #define        AR9170_MC_REG_FLASH_WAIT_STATE          (AR9170_MC_REG_BASE + 0x000)
-#define        AR9170_MC_REG_SEEPROM_WP0               (AR9170_MC_REG_BASE + 0x400)
-#define        AR9170_MC_REG_SEEPROM_WP1               (AR9170_MC_REG_BASE + 0x404)
-#define        AR9170_MC_REG_SEEPROM_WP2               (AR9170_MC_REG_BASE + 0x408)
+
+#define AR9170_SPI_REG_BASE                    (AR9170_MC_REG_BASE + 0x200)
+#define AR9170_SPI_REG_CONTROL0                        (AR9170_SPI_REG_BASE + 0x000)
+#define                AR9170_SPI_CONTROL0_BUSY                BIT(0)
+#define                AR9170_SPI_CONTROL0_CMD_GO              BIT(1)
+#define                AR9170_SPI_CONTROL0_PAGE_WR             BIT(2)
+#define                AR9170_SPI_CONTROL0_SEQ_RD              BIT(3)
+#define                AR9170_SPI_CONTROL0_CMD_ABORT           BIT(4)
+#define                AR9170_SPI_CONTROL0_CMD_LEN_S           8
+#define                AR9170_SPI_CONTROL0_CMD_LEN             0x00000f00
+#define                AR9170_SPI_CONTROL0_RD_LEN_S            12
+#define                AR9170_SPI_CONTROL0_RD_LEN              0x00007000
+
+#define        AR9170_SPI_REG_CONTROL1                 (AR9170_SPI_REG_BASE + 0x004)
+#define                AR9170_SPI_CONTROL1_SCK_RATE            BIT(0)
+#define                AR9170_SPI_CONTROL1_DRIVE_SDO           BIT(1)
+#define                AR9170_SPI_CONTROL1_MODE_SEL_S          2
+#define                AR9170_SPI_CONTROL1_MODE_SEL            0x000000c0
+#define                AR9170_SPI_CONTROL1_WRITE_PROTECT       BIT(4)
+
+#define AR9170_SPI_REG_COMMAND_PORT0           (AR9170_SPI_REG_BASE + 0x008)
+#define                AR9170_SPI_COMMAND_PORT0_CMD0_S         0
+#define                AR9170_SPI_COMMAND_PORT0_CMD0           0x000000ff
+#define                AR9170_SPI_COMMAND_PORT0_CMD1_S         8
+#define                AR9170_SPI_COMMAND_PORT0_CMD1           0x0000ff00
+#define                AR9170_SPI_COMMAND_PORT0_CMD2_S         16
+#define                AR9170_SPI_COMMAND_PORT0_CMD2           0x00ff0000
+#define                AR9170_SPI_COMMAND_PORT0_CMD3_S         24
+#define                AR9170_SPI_COMMAND_PORT0_CMD3           0xff000000
+
+#define AR9170_SPI_REG_COMMAND_PORT1           (AR9170_SPI_REG_BASE + 0x00C)
+#define                AR9170_SPI_COMMAND_PORT1_CMD4_S         0
+#define                AR9170_SPI_COMMAND_PORT1_CMD4           0x000000ff
+#define                AR9170_SPI_COMMAND_PORT1_CMD5_S         8
+#define                AR9170_SPI_COMMAND_PORT1_CMD5           0x0000ff00
+#define                AR9170_SPI_COMMAND_PORT1_CMD6_S         16
+#define                AR9170_SPI_COMMAND_PORT1_CMD6           0x00ff0000
+#define                AR9170_SPI_COMMAND_PORT1_CMD7_S         24
+#define                AR9170_SPI_COMMAND_PORT1_CMD7           0xff000000
+
+#define AR9170_SPI_REG_DATA_PORT               (AR9170_SPI_REG_BASE + 0x010)
+#define AR9170_SPI_REG_PAGE_WRITE_LEN          (AR9170_SPI_REG_BASE + 0x014)
+
+#define AR9170_EEPROM_REG_BASE                 (AR9170_MC_REG_BASE + 0x400)
+#define        AR9170_EEPROM_REG_WP_MAGIC1             (AR9170_EEPROM_REG_BASE + 0x000)
+#define                AR9170_EEPROM_WP_MAGIC1                 0x12345678
+
+#define        AR9170_EEPROM_REG_WP_MAGIC2             (AR9170_EEPROM_REG_BASE + 0x004)
+#define                AR9170_EEPROM_WP_MAGIC2                 0x55aa00ff
+
+#define        AR9170_EEPROM_REG_WP_MAGIC3             (AR9170_EEPROM_REG_BASE + 0x008)
+#define                AR9170_EEPROM_WP_MAGIC3                 0x13579ace
+
+#define        AR9170_EEPROM_REG_CLOCK_DIV             (AR9170_EEPROM_REG_BASE + 0x00C)
+#define                AR9170_EEPROM_CLOCK_DIV_FAC_S           0
+#define                AR9170_EEPROM_CLOCK_DIV_FAC             0x000001ff
+#define                AR9170_EEPROM_CLOCK_DIV_FAC_39KHZ       0xff
+#define                AR9170_EEPROM_CLOCK_DIV_FAC_78KHZ       0x7f
+#define                AR9170_EEPROM_CLOCK_DIV_FAC_312KHZ      0x1f
+#define                AR9170_EEPROM_CLOCK_DIV_FAC_10MHZ       0x0
+#define        AR9170_EEPROM_CLOCK_DIV_SOFT_RST                BIT(9)
+
+#define AR9170_EEPROM_REG_MODE                 (AR9170_EEPROM_REG_BASE + 0x010)
+#define        AR9170_EEPROM_MODE_EEPROM_SIZE_16K_PLUS         BIT(31)
+
+#define AR9170_EEPROM_REG_WRITE_PROTECT                (AR9170_EEPROM_REG_BASE + 0x014)
+#define                AR9170_EEPROM_WRITE_PROTECT_WP_STATUS   BIT(0)
+#define                AR9170_EEPROM_WRITE_PROTECT_WP_SET      BIT(8)
 
 /* Interrupt Controller */
 #define        AR9170_MAX_INT_SRC                      9