and convert dos to unix files. no other changes made here.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
// #############################################################################
/**
- *
+ *
* @brief allocate a new nbuf,
- *
+ *
* @param hdl (adf_net handle)
* @param size (size of the new buf)
* @param reserve (amount of space to reserve in the head)
- *
+ *
* @return newly allocated nbuf
*/
-__adf_nbuf_t
-__adf_nbuf_alloc(adf_os_size_t size, a_uint32_t reserve,
+__adf_nbuf_t
+__adf_nbuf_alloc(adf_os_size_t size, a_uint32_t reserve,
a_uint32_t align)
{
VBUF *buf = NULL;
VDESC *desc;
-
+
buf = VBUF_alloc_vbuf();
if ( buf != NULL ) {
desc = VDESC_alloc_vdesc();
desc->next_desc = NULL;
desc->data_offset = reserve;
desc->data_size = 0;
- desc->control = 0;
-
+ desc->control = 0;
+
buf->desc_list = desc;
- buf->buf_length = 0;
+ buf->buf_length = 0;
}
-
+
return buf;
-}
-
+}
+
/**
* @brief Free the nbuf
* function to be called in
* @param hdl
* @param adf_nbuf
- *
+ *
*/
void __adf_nbuf_free(__adf_nbuf_t buf)
{
/**
* @brief reallocate the head space, call it only after the you
* have called headroom
- *
+ *
* @param adf_nbuf
- * @param headroom
- *
+ * @param headroom
+ *
* @return new nbuf
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_realloc_headroom(__adf_nbuf_t buf, a_uint32_t headroom)
{
adf_os_assert(0);
/**
* @brief expand the tailroom, mostly by adding the new tail
* buffer, also take care of the priv
- *
+ *
* @param buf
* @param tailroom
- *
+ *
* @return struct mbuf * (buffer with the new tailroom)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, a_uint32_t tailroom)
{
adf_os_assert(0);
/**
* @brief expand the headroom or tailroom or both
- *
+ *
* @param buf
* @param headroom ( 0 if no headroom expansion req)
* @param tailroom ( 0 if no tailroom expansion req)
- *
+ *
* @return struct mbuf* (NULL if something goofed up)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_expand(__adf_nbuf_t buf, a_uint32_t headroom, a_uint32_t tailroom)
{
adf_os_assert(0);
/**
* @brief put data in the head
- *
+ *
* @param buf
* @param len (how much data to put)
- *
+ *
* @return new data pointer ,NULL if the len is more than the
* space available in the head frag.
*/
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t len)
{
- a_uint8_t *ptr = NULL;
+ a_uint8_t *ptr = NULL;
VDESC *desc = buf->desc_list;
-
+
desc->data_offset -= len;
desc->data_size += len;
buf->buf_length += len;
}
/**
- *
+ *
* @brief add data in the end of tail
- *
+ *
* @param buf
* @param len (how much data to put)
- *
+ *
* @return previous tail (data+len),NULL if the len is more than
* space available
*/
{
a_uint8_t *tail = NULL;
VDESC *last_desc = __adf_nbuf_last(buf);
-
+
tail = last_desc->buf_addr + last_desc->data_offset + last_desc->data_size;
last_desc->data_size += len;
buf->buf_length += len;
-
+
return tail;
}
/**
* @brief strip data from head
- *
+ *
* @param adf_nbuf
* @param len (how much data to rip)
- *
+ *
* @return new data pointer
*/
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t len)
{
a_uint8_t *ptr = NULL;
VDESC *desc = buf->desc_list;
-
+
desc->data_offset += len;
desc->data_size -= len;
buf->buf_length -= len;
ptr = desc->buf_addr + desc->data_offset;
-
+
return ptr;
}
/**
* @brief strip data from tail, priv safe
- *
+ *
* @param buf
* @param len (how much to strip down)
- *
+ *
*/
-void
+void
__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t len)
{
VDESC *last_desc = __adf_nbuf_last(buf);
-
+
adf_os_assert(buf != NULL);
last_desc->data_size -= len;
buf->buf_length -= len;
-
+
//adf_os_assert(0); //0820
}
/**
* @brief Copy assumes that we create a writeable copy of the
* nbuf which is equivalent in FreeBSD as duping the
* mbuf.
- *
+ *
* @param src
- *
+ *
* @return struct mbuf * (newly allocated buffer)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_copy(__adf_nbuf_t src)
{
- __adf_nbuf_t buf = NULL;
+ __adf_nbuf_t buf = NULL;
adf_os_assert(src != NULL);
-
+
return buf;
}
/**
* @brief make the writable copy of the nbuf
- *
+ *
* @param adf_nbuf
- *
+ *
* @return new nbuf
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_unshare(__adf_nbuf_t src)
{
__adf_nbuf_t buf = NULL;
/**
* @brief return the frag data & len, where frag no. is
* specified by the index
- *
+ *
* @param[in] buf
* @param[out] sg (scatter/gather list of all the frags)
- *
+ *
*/
-void
+void
__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg)
{
VDESC *desc = buf->desc_list;
int count = 0;
-
+
while( desc != NULL ) {
sg->sg_segs[count].vaddr = desc->buf_addr + desc->data_offset;
sg->sg_segs[count].len = desc->data_size;
-
- count++;
+
+ count++;
desc = desc->next_desc;
}
-
+
sg->nsegs = count;
}
/**
* @brief retrieve the priv space pointer from nbuf
- *
+ *
* @param buf (nbuf to attach the priv space)
- *
+ *
* @return uint8_t* ( pointer to the data )
*/
a_uint8_t *
}
/**
- *
+ *
* @brief append the nbuf to the queue
- *
+ *
* @param adf_qhead
* @param adf_nbuf
- *
+ *
*/
-void
-__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead,
+void
+__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead,
__adf_nbuf_t buf)
{
qhead->qlen++;
/**
* @brief dequeue an nbuf
- *
+ *
* @param adf_qhead
- *
+ *
* @return the nbuf
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead)
{
__adf_nbuf_t b0 = NULL;
} else {
qhead->head = qhead->head->next_buf;
}
-
+
b0->next_buf = NULL;
}
return b0;
/**
* @brief creates a streaming mapping (takes a pre allocated
* global tag for 4K mbuf sizes)
- *
+ *
* @param hdl
* @param max_sz
* @param dmap
- *
+ *
* @return a_status_t
*/
-a_status_t
+a_status_t
__adf_nbuf_dmamap_create(__adf_os_device_t osdev, __adf_os_dma_map_t *dmap)
{
a_status_t retval = A_STATUS_OK;
-
+
(*dmap) = A_ALLOCRAM(sizeof(struct __adf_dma_map));
if(*dmap == NULL)
return A_STATUS_ENOMEM;
-
+
(*dmap)->buf = NULL;
return retval;
}
-a_status_t
-__adf_nbuf_map(__adf_os_device_t osdev, __adf_os_dma_map_t bmap,
+a_status_t
+__adf_nbuf_map(__adf_os_device_t osdev, __adf_os_dma_map_t bmap,
__adf_nbuf_t buf, adf_os_dma_dir_t dir)
-{
+{
bmap->buf = buf;
-
+
return A_STATUS_OK;
}
-void
-__adf_nbuf_unmap(__adf_os_device_t osdev, __adf_os_dma_map_t bmap,
+void
+__adf_nbuf_unmap(__adf_os_device_t osdev, __adf_os_dma_map_t bmap,
adf_os_dma_dir_t dir)
{
bmap->buf = NULL;
-
+
return;
}
void
-__adf_nbuf_dmamap_destroy(__adf_os_device_t osdev,
+__adf_nbuf_dmamap_destroy(__adf_os_device_t osdev,
__adf_os_dma_map_t dmap)
{
//dmap->buf = NULL;
-
+
// Should not be called in FW!
//return A_STATUS_OK;
}
/**
- * @brief return the dma map info
- *
+ * @brief return the dma map info
+ *
* @param[in] bmap
* @param[out] sg (map_info ptr)
*/
-void
+void
__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg)
{
VDESC *desc = bmap->buf->desc_list;
int count = 0;
-
+
while( desc != NULL ) {
sg->dma_segs[count].paddr = (adf_os_dma_addr_t)(desc->buf_addr + desc->data_offset);
sg->dma_segs[count].len = desc->data_size;
-
- count++;
+
+ count++;
desc = desc->next_desc;
}
-
- sg->nsegs = count;
+
+ sg->nsegs = count;
}
/**
/**
* @brief sets the cksum type & value for nbuf
* XXX: not fully implemented
- *
+ *
* @param buf
* @param cksum
*/
-void
+void
__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum)
{
}
-a_status_t
-__adf_nbuf_get_vlan_info(adf_net_handle_t hdl, __adf_nbuf_t buf,
+a_status_t
+__adf_nbuf_get_vlan_info(adf_net_handle_t hdl, __adf_nbuf_t buf,
adf_net_vlanhdr_t *vlan)
{
return A_STATUS_OK;
}
if (cnt != len) {
- //adf_os_print("cnt: %x, len: %x, __adf_nbuf_queue_len: %x\n", cnt, len,
+ //adf_os_print("cnt: %x, len: %x, __adf_nbuf_queue_len: %x\n", cnt, len,
// __adf_nbuf_queue_len(qhead));
adf_os_assert(0);
}
buf->desc_list = NULL;
buf->buf_length = 0;
VBUF_free_vbuf(buf);
-
+
}
/**
* @brief return the last mbuf
- *
+ *
* @param m0
- *
+ *
* @return struct mbuf*
*/
-VDESC *
+VDESC *
__adf_nbuf_last(VBUF *buf)
{
VDESC *desc = buf->desc_list;
-
+
//for(; desc->next_desc != NULL; desc = desc->next_desc)
// ;
while(desc->next_desc != NULL)
{
desc = desc->next_desc;
}
-
+
return desc;
}
/**
* @brief num bytes in the head
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes available
*/
a_uint32_t
/**
* @brief num of bytes available in the tail excluding the priv
* portion
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes
*/
-a_uint32_t
+a_uint32_t
__adf_nbuf_tailroom(__adf_nbuf_t buf)
{
VDESC *last_desc = __adf_nbuf_last(buf);
-
+
return last_desc->buf_size - last_desc->data_offset - last_desc->data_size;
}
/**
* @brief get the entire packet length
- *
+ *
* @param adf_nbuf
- *
+ *
* @return total length of packet (sum of all frag lengths)
- */
+ */
a_uint32_t
__adf_nbuf_len(__adf_nbuf_t buf)
{
- return buf->buf_length;
+ return buf->buf_length;
}
/**
* @brief Clone the nbuf (will not create writeable copies)
- *
+ *
* @param adf_nbuf
- *
+ *
* @return Read-only copy of the nbuf (including clusters)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_clone(__adf_nbuf_t src)
{
__adf_nbuf_t buf = NULL;
-
+
return buf;
}
/*
* @brief check if the mbuf is cloned or not
- *
+ *
* @param buf
- *
+ *
* @return a_bool_t
*/
a_bool_t
* @brief This will return the header's addr & m_len
*/
void
-__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
+__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
a_uint32_t *len)
{
VDESC *desc = buf->desc_list;
-
+
*addr = desc->buf_addr + desc->data_offset;
- *len = desc->data_size;
+ *len = desc->data_size;
}
/**
* @brief init the queue
* @param qhead
*/
-void
+void
__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead)
{
qhead->qlen = 0;
/**
* @brief return the length of queue
* @param adf_qhead
- *
+ *
* @return length
- *
+ *
*/
-a_uint32_t
+a_uint32_t
__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead)
{
return qhead->qlen;
/**
* @brief returns the first guy in the Q
* @param qhead
- *
+ *
* @return (NULL if the Q is empty)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead)
{
return qhead->head;
}
/**
* @brief return the next packet from packet chain
- *
+ *
* @param buf (packet)
- *
+ *
* @return (NULL if no packets are there)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_queue_next(__adf_nbuf_t buf)
{
return buf->next_buf;
}
/**
* @brief check if the queue is empty or not
- *
+ *
* @param qhead
- *
+ *
* @return a_bool_t
*/
-a_bool_t
+a_bool_t
__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead)
{
return ((qhead->qlen == 0));
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * FreeBSD specific prototypes
+ * FreeBSD specific prototypes
*/
#ifndef _ADF_NBUF_PVT_H
#define _ADF_NBUF_PVT_H
//#include <adf_nbuf_api.h>
#define __ADF_NBUF_NULL NULL
-#define __ADF_NBUF_CTX_BUF
+#define __ADF_NBUF_CTX_BUF
typedef VBUF * __adf_nbuf_t;
*/
typedef struct __adf_nbuf_qhead {
VBUF *head;
- VBUF *tail;
+ VBUF *tail;
a_uint32_t qlen;
}__adf_nbuf_qhead_t;
typedef __adf_nbuf_qhead_t __adf_nbuf_queue_t;
-__adf_nbuf_t
-__adf_nbuf_alloc(adf_os_size_t size,
- a_uint32_t reserve, a_uint32_t align);
+__adf_nbuf_t
+__adf_nbuf_alloc(adf_os_size_t size,
+ a_uint32_t reserve, a_uint32_t align);
-void
+void
__adf_nbuf_free(__adf_nbuf_t buf);
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t size);
-
-a_uint8_t *
+
+a_uint8_t *
__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t size);
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t size);
-void
+void
__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t size);
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_realloc_headroom(__adf_nbuf_t buf,
- a_uint32_t headroom);
-
-__adf_nbuf_t
-__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf,
+ a_uint32_t headroom);
+
+__adf_nbuf_t
+__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf,
a_uint32_t tailroom);
-
-__adf_nbuf_t
+
+__adf_nbuf_t
__adf_nbuf_expand(__adf_nbuf_t buf,
a_uint32_t headroom, a_uint32_t tailroom);
-
-__adf_nbuf_t
+
+__adf_nbuf_t
__adf_nbuf_copy(__adf_nbuf_t src);
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_unshare(__adf_nbuf_t src);
-void
+void
__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg);
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_get_priv(__adf_nbuf_t buf);
-void
-__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead,
+void
+__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead,
__adf_nbuf_t buf);
-
-__adf_nbuf_t
+
+__adf_nbuf_t
__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead);
-a_uint32_t
-__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf,
- a_uint8_t **hdr_off,
+a_uint32_t
+__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf,
+ a_uint8_t **hdr_off,
a_uint8_t **where);
-
-void
+
+void
__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum);
-void
+void
__adf_nbuf_get_tso_info(__adf_nbuf_t buf, adf_nbuf_tso_t *tso);
-a_status_t
-__adf_nbuf_get_vlan_info(adf_net_handle_t hdl,
- __adf_nbuf_t buf,
- adf_net_vlanhdr_t *vlan);
-
-void
+a_status_t
+__adf_nbuf_get_vlan_info(adf_net_handle_t hdl,
+ __adf_nbuf_t buf,
+ adf_net_vlanhdr_t *vlan);
+
+void
__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg);
/**
* @brief return the last mbuf
- *
+ *
* @param m0
- *
+ *
* @return struct mbuf*
*/
-VDESC *
+VDESC *
__adf_nbuf_last(VBUF *buf);
/**
* @brief num bytes in the head
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes available
*/
a_uint32_t
/**
* @brief num of bytes available in the tail excluding the priv
* portion
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes
*/
-a_uint32_t
+a_uint32_t
__adf_nbuf_tailroom(__adf_nbuf_t buf);
/**
* @brief get the entire packet length
- *
+ *
* @param adf_nbuf
- *
+ *
* @return total length of packet (sum of all frag lengths)
- */
+ */
a_uint32_t
__adf_nbuf_len(__adf_nbuf_t buf);
/**
* @brief Clone the nbuf (will not create writeable copies)
- *
+ *
* @param adf_nbuf
- *
+ *
* @return Read-only copy of the nbuf (including clusters)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_clone(__adf_nbuf_t src);
void
/*
* @brief check if the mbuf is cloned or not
- *
+ *
* @param buf
- *
+ *
* @return a_bool_t
*/
a_bool_t
* @brief This will return the header's addr & m_len
*/
void
-__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
+__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
a_uint32_t *len);
/**
* @brief init the queue
* @param qhead
*/
-void
+void
__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead);
/**
* @brief return the length of queue
* @param adf_qhead
- *
+ *
* @return length
- *
+ *
*/
-a_uint32_t
+a_uint32_t
__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead);
/**
* @brief returns the first guy in the Q
* @param qhead
- *
+ *
* @return (NULL if the Q is empty)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead);
/**
* @brief return the next packet from packet chain
- *
+ *
* @param buf (packet)
- *
+ *
* @return (NULL if no packets are there)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_queue_next(__adf_nbuf_t buf);
/**
* @brief check if the queue is empty or not
- *
+ *
* @param qhead
- *
+ *
* @return a_bool_t
*/
-a_bool_t
+a_bool_t
__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead);
__adf_nbuf_t
void
__adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_queue_t *qhead);
-a_status_t __adf_nbuf_dmamap_create(__adf_os_device_t osdev,
+a_status_t __adf_nbuf_dmamap_create(__adf_os_device_t osdev,
__adf_os_dma_map_t *dmap);
-void __adf_nbuf_dmamap_destroy(__adf_os_device_t osdev,
+void __adf_nbuf_dmamap_destroy(__adf_os_device_t osdev,
__adf_os_dma_map_t dmap);
a_status_t __adf_nbuf_map(__adf_os_device_t osdev, __adf_os_dma_map_t dmap,
/**
* @brief register the driver into the shim
* @param[in] drv
- *
+ *
* @return a_status_t
*/
a_status_t
__adf_net_register_drv(adf_drv_info_t *drv)
{
- wlan_pci_register_drv(drv);
+ wlan_pci_register_drv(drv);
return A_STATUS_OK;
}
#define __ADF_PCI_BAR0 0x10
-a_status_t
+a_status_t
__adf_net_register_drv(adf_drv_info_t *drv);
void
static inline void
__adf_net_start_queue(adf_net_handle_t hdl)
-{
+{
}
return NULL;
}
-static inline adf_net_handle_t __adf_net_vdev_create(adf_net_handle_t dev_hdl,
- adf_drv_handle_t hdl, adf_vdev_sw_t *op,
+static inline adf_net_handle_t __adf_net_vdev_create(adf_net_handle_t dev_hdl,
+ adf_drv_handle_t hdl, adf_vdev_sw_t *op,
adf_net_dev_info_t *info)
{
return NULL;
__adf_net_hdl_to_os(adf_net_handle_t hdl)
{
return NULL;
-}
+}
#endif
/**
* @brief This initiallizes the varriable to zero
- *
+ *
* @param __adf_os_atomic_t (int pointer)
- *
+ *
*/
static inline void
__adf_os_atomic_init(__adf_os_atomic_t *v)
__adf_os_atomic_write(__adf_os_atomic_t *v,a_uint32_t p)
{
atomic_store_rel_int(v,(int)p);
-}
+}
*/
#endif
*/
#include "adf_os_defer_pvt.h"
-void
+void
__adf_os_defer_func(void *arg, int pending)
{
__adf_os_defer_ctx_t *ctx = (__adf_os_defer_ctx_t *)arg;
/**
* @brief initiallize the defer function (work or bh)
- *
+ *
* @param defer
* @param func
* @param arg
*/
static inline void __adf_os_init_defer(__adf_os_defer_t *defer,
- adf_os_defer_fn_t func,
+ adf_os_defer_fn_t func,
void *arg)
{
defer->ctx.caller_fn = func;
//__adf_os_init_defer(bh, func, arg);
A_TASKLET_INIT_TASK(func, arg, bh);
}
-static inline void __adf_os_sched_work(adf_os_handle_t hdl,
+static inline void __adf_os_sched_work(adf_os_handle_t hdl,
__adf_os_work_t * work)
{
//taskqueue_enqueue(taskqueue_thread, &work->tsk);
}
-static inline void __adf_os_disable_work(adf_os_handle_t hdl,
+static inline void __adf_os_disable_work(adf_os_handle_t hdl,
__adf_os_work_t * work)
{
//taskqueue_drain(taskqueue_thread, &work->tsk);
}
-static inline void __adf_os_sched_bh(adf_os_handle_t hdl,
+static inline void __adf_os_sched_bh(adf_os_handle_t hdl,
__adf_os_bh_t * bh)
{
A_TASKLET_SCHEDULE(bh);
}
-static inline void __adf_os_disable_bh(adf_os_handle_t hdl,
+static inline void __adf_os_disable_bh(adf_os_handle_t hdl,
__adf_os_bh_t * bh)
{
A_TASKLET_DISABLE(bh);
}
-#endif
+#endif
adf_os_assert(nseg == 1);
((bus_dma_segment_t *)arg)[0].ds_addr = dseg[0].ds_addr;
- ((bus_dma_segment_t *)arg)[0].ds_len = dseg[0].ds_len;
+ ((bus_dma_segment_t *)arg)[0].ds_len = dseg[0].ds_len;
}
#endif
* @brief Allocates a DMA region, uses the tag elem to store the
* tag value which constant for all the mappings done
* through this API.
- *
+ *
* @param osdev
* @param size
* @param coherent
* @param dmap
- *
+ *
* @return void* (Virtual address)
*/
inline void*
-__adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size,
+__adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size,
a_bool_t coherent, __adf_os_dma_map_t *dmap)
-{
+{
(*dmap) = A_ALLOCRAM(sizeof(struct __adf_dma_map));
-
+
if((*dmap) == NULL){
goto fail_malloc;
}
-
+
(*dmap)->ds_addr = A_ALLOCRAM(size);
(*dmap)->ds_len = size;
-
+
return (*dmap)->ds_addr;
-
-fail_malloc:
- return NULL;
+
+fail_malloc:
+ return NULL;
}
#include <adf_os_util.h>
inline void*
-__adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size,
+__adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size,
a_bool_t coherent, __adf_os_dma_map_t *dmap);
-/*
- * Free a previously mapped DMA buffer
+/*
+ * Free a previously mapped DMA buffer
* Direction doesnt matter, since this API is called at closing time.
*/
static inline void
__adf_os_dmamem_free(adf_os_device_t osdev, __adf_os_size_t size, a_bool_t coherent,
void *vaddr, __adf_os_dma_map_t dmap)
-{
+{
}
//#define __adf_os_dmamem_map2addr(_dmap) ((_dmap)->seg[0].ds_addr)
#define __adf_os_dmamem_map2addr(_dmap) ((adf_os_dma_addr_t)(_dmap)->ds_addr)
-static inline void
+static inline void
__adf_os_dmamem_cache_sync(__adf_os_device_t osdev, __adf_os_dma_map_t dmap, adf_os_cache_sync_t sync)
{
#define __adf_os_htons(x) x
#define __adf_os_htonl(x) x
-#define __adf_os_cpu_to_le16(x) __bswap16(x)
+#define __adf_os_cpu_to_le16(x) __bswap16(x)
#endif
* @brief setup the Interrupt handler for the driver
* @param[in] dev
* @param[in] sc
- *
+ *
* @return int
*/
__adf_os_setup_intr(__adf_os_device_t osdev, adf_os_drv_intr fn)
{
g_wlan_intr = fn;
-
- return 0;
+
+ return 0;
}
/**
void
__adf_os_free_intr(__adf_os_device_t osdev)
{
- g_wlan_intr = NULL;
+ g_wlan_intr = NULL;
}
static inline void __adf_os_init_mutex(__adf_os_mutex_t *mtx)
{
-
+
}
static inline int __adf_os_mutex_acquire(__adf_os_mutex_t *mtx)
{
//mtx_unlock_spin(lock);
}
-static inline a_bool_t __adf_os_spinlock_irq_exec(adf_os_handle_t hdl, __adf_os_spinlock_t *lock,
+static inline a_bool_t __adf_os_spinlock_irq_exec(adf_os_handle_t hdl, __adf_os_spinlock_t *lock,
adf_os_irqlocked_func_t func, void *arg)
{
return 0;
/* move a memory buffer */
static inline void __adf_os_mem_copy(void *dst, const void *src, adf_os_size_t size)
{
- A_MEMCPY(dst,src,size);
+ A_MEMCPY(dst,src,size);
}
/* set a memory buffer */
/**
* @brief generic driver /module init function
- *
+ *
* @param mod (module data)
* @param event (LOAD or UNLOAD)
* @param arg (any extra argument needed if
- *
+ *
* @return int
*/
/**
* exit module macro
*/
-#define __adf_os_virt_module_exit(_fn)
+#define __adf_os_virt_module_exit(_fn)
-#define __adf_os_module_dep(_name, _dep)
+#define __adf_os_module_dep(_name, _dep)
#endif
/**
* exit module macro
*/
-#define __adf_os_pci_module_exit(_fn)
+#define __adf_os_pci_module_exit(_fn)
/**
* initiallize the PCI driver structure
* @param osdev
* @param offset
* @param val
- *
+ *
* @return int
*/
-static inline int
+static inline int
__adf_os_pci_config_read8(adf_os_device_t osdev, int offset, a_uint8_t *val)
{
(*val) = wlan_pci_config_read(offset, 1);
*/
}
-static inline int
+static inline int
__adf_os_pci_config_write8(adf_os_device_t osdev, int offset, a_uint8_t val)
{
wlan_pci_config_write(offset, val, 1);
- return 0;
+ return 0;
}
-static inline int
+static inline int
__adf_os_pci_config_read16(adf_os_device_t osdev, int offset, a_uint16_t *val)
{
(*val) = wlan_pci_config_read(offset, 2);
return 0;
}
-static inline int
+static inline int
__adf_os_pci_config_write16(adf_os_device_t osdev, int offset, a_uint16_t val)
{
wlan_pci_config_write(offset, val, 2);
- return 0;
+ return 0;
}
-static inline int
+static inline int
__adf_os_pci_config_read32(adf_os_device_t osdev, int offset, a_uint32_t *val)
{
(*val) = wlan_pci_config_read(offset, 4);
return 0;
}
-static inline int
+static inline int
__adf_os_pci_config_write32(adf_os_device_t osdev, int offset, a_uint32_t val)
{
wlan_pci_config_write(offset, val, 4);
- return 0;
+ return 0;
}
#endif
* @brief this code is modified version of tvtohz(9) which
* returns signed int which we don't require, hence we
* got rid of the type casting thing
- *
+ *
* @return unsigned long
*/
static inline unsigned long
static inline unsigned long
__adf_os_getuptime(void)
{
- return MSEC_TO_TICK(A_MILLISECONDS());;
+ return MSEC_TO_TICK(A_MILLISECONDS());;
}
static inline void
#include "Magpie_api.h"
-typedef struct
+typedef struct
{
A_timer_t *magpie_timer;
adf_os_timer_func_t timer_func;
void
__adf_os_timer_func(A_HANDLE timer_handle, void *arg);
-/*
+/*
* Initialize a timer
*/
static inline void
A_INIT_TIMER(timer->magpie_timer, __adf_os_timer_func, arg);
}
-/*
- * start a timer
+/*
+ * start a timer
*/
static inline void
__adf_os_timer_start(__adf_os_timer_t *timer, int msec)
/**
* CACHE-SYNC (DMA)
*/
-#define __ADF_SYNC_PREREAD 0
+#define __ADF_SYNC_PREREAD 0
#define __ADF_SYNC_POSTREAD 1
#define __ADF_SYNC_PREWRITE 2
#define __ADF_SYNC_POSTWRITE 3
#define __ADF_OS_DMA_TO_DEVICE 0
-#define __ADF_OS_DMA_FROM_DEVICE 1
-
+#define __ADF_OS_DMA_FROM_DEVICE 1
+
struct __adf_softc;
__ADF_IEEE80211_SCAN = 105,
__ADF_IEEE80211_REPLAY = 106,
__ADF_IEEE80211_MICHAEL = 107,
- __ADF_IEEE80211_REJOIN = 108,
+ __ADF_IEEE80211_REJOIN = 108,
__ADF_CUSTOM_PUSH_BUTTON = 109,
};
/* generic data types */
struct __adf_device {
-int dummy;
-};
+int dummy;
+};
typedef struct __adf_device *__adf_os_device_t;
struct __adf_dma_map {
VBUF *buf;
-
+
A_UINT32 *ds_addr;
A_UINT16 ds_len;
-};
+};
typedef struct __adf_dma_map *__adf_os_dma_map_t;
#define __adf_os_iomem_t
#if 0
-typedef int __a_uint8_t;
-typedef int __a_int8_t;
-typedef int __a_uint16_t;
-typedef int __a_int16_t;
-typedef int __a_uint32_t;
-typedef int __a_int32_t;
-typedef int __a_uint64_t;
-typedef int __a_int64_t;
+typedef int __a_uint8_t;
+typedef int __a_int8_t;
+typedef int __a_uint16_t;
+typedef int __a_int16_t;
+typedef int __a_uint32_t;
+typedef int __a_int32_t;
+typedef int __a_uint64_t;
+typedef int __a_int64_t;
#else
typedef A_UINT8 __a_uint8_t;
-typedef A_INT8 __a_int8_t;
-typedef A_UINT16 __a_uint16_t;
-typedef A_INT16 __a_int16_t;
-typedef A_UINT32 __a_uint32_t;
-typedef A_INT32 __a_int32_t;
-typedef A_UINT64 __a_uint64_t;
-typedef A_INT64 __a_int64_t;
+typedef A_INT8 __a_int8_t;
+typedef A_UINT16 __a_uint16_t;
+typedef A_INT16 __a_int16_t;
+typedef A_UINT32 __a_uint32_t;
+typedef A_INT32 __a_int32_t;
+typedef A_UINT64 __a_uint64_t;
+typedef A_INT64 __a_int64_t;
typedef A_UINT32 u_int32_t;
typedef A_UINT16 u_int16_t;
//#define __adf_os_print my_printf
#define __adf_os_print A_PRINTF
-#if 1
+#if 1
#if defined(__XCC__)
#include "stdarg.h"
#define __va_list __gnuc_va_list
#include <adf_os_types.h>
-#define __adf_os_unlikely(_expr)
-#define __adf_os_likely(_expr)
+#define __adf_os_unlikely(_expr)
+#define __adf_os_likely(_expr)
/**
- * @brief memory barriers.
+ * @brief memory barriers.
*/
#define __adf_os_wmb() oops no implementation...
#define __adf_os_rmb() oops no implementation...
#define __adf_os_mb() oops no implementation...
-#define __adf_os_min(_a, _b) ((_a < _b) ? _a : _b)
-#define __adf_os_max(_a, _b) ((_a > _b) ? _a : _b)
+#define __adf_os_min(_a, _b) ((_a < _b) ? _a : _b)
+#define __adf_os_max(_a, _b) ((_a > _b) ? _a : _b)
#ifdef _DEBUG_BUILD_
#define __adf_os_assert(expr) do {\
#define inline
#endif
-static void inline
+static void inline
__adf_os_get_rand(adf_os_handle_t hdl,__a_uint8_t *ptr, __a_uint32_t len)
{
-#if 0
+#if 0
u_int8_t *dp = ptr;
u_int32_t v;
size_t nb;
dp += sizeof(u_int32_t);
len -= nb;
}
-#endif
+#endif
}
*/
/*
* @File: buf_pool_api.h
- *
+ *
* @Abstract: BUF Pool api
- *
+ *
* @Notes:
*/
/* endpoint defines */
typedef enum
{
- POOL_ID_HTC_CONTROL = 0,
- POOL_ID_WMI_SVC_CMD_REPLY = 1,
+ POOL_ID_HTC_CONTROL = 0,
+ POOL_ID_WMI_SVC_CMD_REPLY = 1,
POOL_ID_WMI_SVC_EVENT = 2,
POOL_ID_WLAN_RX_BUF = 3,
- POOL_ID_MAX = 10
+ POOL_ID_MAX = 10
} BUF_POOL_ID;
typedef void* pool_handle_t;
/* hardware API table structure (API descriptions below) */
struct buf_pool_api {
pool_handle_t (*_init)(adf_os_handle_t handle);
-
+
void (*_shutdown)(pool_handle_t handle);
-
+
void (*_create_pool)(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize);
-
+
adf_nbuf_t (*_alloc_buf)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve);
-
+
adf_nbuf_t (*_alloc_buf_align)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align);
-
+
void (*_free_buf)(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf);
-
+
/* room to expand this table by another table */
- void *pReserved;
+ void *pReserved;
};
extern void buf_pool_module_install(struct buf_pool_api *apis);
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * @File:
- *
+ * @File:
+ *
* @Abstract: Buf pool implementation: Dynamic version
- *
- * @Notes:
+ *
+ * @Notes:
*/
#include <adf_os_mem.h>
#include <adf_os_module.h>
#include <osapi.h>
-#include <Magpie_api.h>
+#include <Magpie_api.h>
//#include <os/cmnos_api.h>
#include <buf_pool_api.h>
-
+
LOCAL htc_handle_t _buf_pool_dynamic_init(adf_os_handle_t handle);
LOCAL void _buf_pool_dynamic_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize);
LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve);
LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align);
LOCAL void _buf_pool_dynamic_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf);
LOCAL void _buf_pool_dynamic_shutdown(pool_handle_t handle);
-
+
typedef struct _POOL_CONFIG {
int nSize;
} POOL_CONFIG;
-
+
typedef struct _BUF_POOL_DYNAMIC_CONTEXT {
adf_os_handle_t OSHandle;
- POOL_CONFIG poolConf[POOL_ID_MAX];
+ POOL_CONFIG poolConf[POOL_ID_MAX];
} BUF_POOL_DYNAMIC_CONTEXT;
void buf_pool_module_install(struct buf_pool_api *pAPIs)
-{
+{
pAPIs->_init = _buf_pool_dynamic_init;
pAPIs->_create_pool = _buf_pool_dynamic_create_pool;
pAPIs->_alloc_buf = _buf_pool_dynamic_alloc_buf;
pAPIs->_free_buf = _buf_pool_dynamic_free_buf;
pAPIs->_shutdown = _buf_pool_dynamic_shutdown;
}
-
+
LOCAL pool_handle_t _buf_pool_dynamic_init(adf_os_handle_t handle)
{
BUF_POOL_DYNAMIC_CONTEXT *ctx;
-
+
ctx = (BUF_POOL_DYNAMIC_CONTEXT *)adf_os_mem_alloc(sizeof(BUF_POOL_DYNAMIC_CONTEXT));
ctx->OSHandle = handle;
-
- return ctx;
-}
-
-LOCAL void _buf_pool_dynamic_shutdown(pool_handle_t handle)
+
+ return ctx;
+}
+
+LOCAL void _buf_pool_dynamic_shutdown(pool_handle_t handle)
{
BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle;
-
+
adf_os_mem_free(ctx);
}
LOCAL void _buf_pool_dynamic_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize)
{
BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle;
-
+
ctx->poolConf[poolId].nSize = nSize;
}
-
+
LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve)
{
BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle;
POOL_CONFIG *poolConf = &ctx->poolConf[poolId];
-
- return adf_nbuf_alloc(poolConf->nSize,
+
+ return adf_nbuf_alloc(poolConf->nSize,
reserve, 0);
}
-
+
LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align)
{
BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle;
POOL_CONFIG *poolConf = &ctx->poolConf[poolId];
- return adf_nbuf_alloc(poolConf->nSize,
+ return adf_nbuf_alloc(poolConf->nSize,
reserve, align);
}
LOCAL void _buf_pool_dynamic_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf)
{
//BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle;
-
+
adf_nbuf_free(buf);
}
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * @File:
- *
+ * @File:
+ *
* @Abstract: Buf pool implementation: static version
- *
- * @Notes:
+ *
+ * @Notes:
*/
#include <osapi.h>
-#include <Magpie_api.h>
+#include <Magpie_api.h>
#include <cmnos_api.h>
#include <buf_pool_api.h>
#include <vbuf_api.h>
#include <vdesc_api.h>
-#include <adf_os_mem.h>
+#include <adf_os_mem.h>
#include "buf_pool_static.h"
LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve);
LOCAL adf_nbuf_t _buf_pool_static_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align);
LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf);
-LOCAL void _buf_pool_static_shutdown(pool_handle_t handle);
+LOCAL void _buf_pool_static_shutdown(pool_handle_t handle);
BUF_POOL_STATIC_CONTEXT g_poolCtx;
void buf_pool_module_install(struct buf_pool_api *pAPIs)
-{
+{
pAPIs->_init = _buf_pool_static_init;
pAPIs->_create_pool = _buf_pool_static_create_pool;
pAPIs->_alloc_buf = _buf_pool_static_alloc_buf;
pAPIs->_free_buf = _buf_pool_static_free_buf;
pAPIs->_shutdown = _buf_pool_static_shutdown;
}
-
+
LOCAL pool_handle_t _buf_pool_static_init(adf_os_handle_t handle)
{
#if 1
int i;
-
+
for(i=0; i < POOL_ID_MAX; i++) {
g_poolCtx.bufQ[i] = NULL;
}
-
+
return &g_poolCtx;
-#else
+#else
BUF_POOL_STATIC_CONTEXT *ctx;
-
+
//ctx = (BUF_POOL_static_CONTEXT *)A_ALLOCRAM(sizeof(BUF_POOL_static_CONTEXT));
ctx = (BUF_POOL_STATIC_CONTEXT *)adf_os_mem_alloc(sizeof(BUF_POOL_STATIC_CONTEXT));
ctx->NetHandle = handle;
-
- return ctx;
-#endif
-}
-
-LOCAL void _buf_pool_static_shutdown(pool_handle_t handle)
+
+ return ctx;
+#endif
+}
+
+LOCAL void _buf_pool_static_shutdown(pool_handle_t handle)
{
// SHALL NOT BE USED in FW
}
int i;
VBUF *buf;
VDESC *desc;
-
+
//BUF_POOL_STATIC_CONTEXT *ctx = (BUF_POOL_STATIC_CONTEXT *)handle;
-
+
for ( i = 0; i < nItems; i++) {
buf = VBUF_alloc_vbuf();
desc = VDESC_alloc_vdesc();
desc->buf_size = nSize;
desc->data_offset = 0;
desc->data_size = 0;
-
- buf->buf_length = 0;
+
+ buf->buf_length = 0;
buf->desc_list = desc;
-
+
if ( g_poolCtx.bufQ[poolId] == NULL ) {
g_poolCtx.bufQ[poolId] = buf;
} else {
}
}
}
-
+
LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve)
{
VBUF *buf;
-
+
buf = g_poolCtx.bufQ[poolId];
if ( buf != NULL ) {
g_poolCtx.bufQ[poolId] = buf->next_buf;
-
+
buf->next_buf = NULL;
buf->desc_list->data_offset = reserve;
buf->desc_list->data_size = 0;
buf->buf_length = 0;
}
-
+
return buf;
}
{
return _buf_pool_static_alloc_buf(handle, poolId, reserve);
}
-
+
LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf)
{
if ( g_poolCtx.bufQ[poolId] == NULL ) {
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * @File:
- *
- * @Abstract:
- *
- * @Notes:
+ * @File:
+ *
+ * @Abstract:
+ *
+ * @Notes:
*/
#ifndef BUF_POOL_STATIC_H_
typedef struct _BUF_POOL_STATIC_CONTEXT {
VBUF *bufQ[POOL_ID_MAX];
-
+
// Left a door for extension the structure
void *pReserved;
} BUF_POOL_STATIC_CONTEXT;
A_UINT32 (* _refclk_speed_get)(void);
A_UINT32 (* _milliseconds)(void);
void (* _sysclk_change)(void);
-
+
void (* _clock_tick)(void);
};
#define A_MEMMOVE(dst, src, size)
#define A_MEMCMP(p1, p2, nbytes)
-#endif
+#endif
#if 1
#define A_UART_HWINIT(freq, baud)
-#define A_UART_ENABLED()
+#define A_UART_ENABLED()
-#define A_PUTS(str)
+#define A_PUTS(str)
#define A_PUTC(ch)
#define A_GETC(pCh)
#define A_IS_HOST_PRESENT()
#define A_KBHIT(delay)
#define A_GET_ROM_VER()
-#endif
+#endif
//#if SYSTEM_MODULE_DBG
/* debug Support */
#define A_USB_EP0_SETUP() A_CMN(usb._usb_ep0_setup())
#define A_USB_EP0_TX_DATA() A_CMN(usb._usb_ep0_tx_data())
#define A_USB_EP0_RX_DATA() A_CMN(usb._usb_ep0_rx_data())
-
+
#define A_USB_GET_CONFIG() A_CMN(usb._usb_get_configuration())
#define A_USB_SET_CONFIG() A_CMN(usb._usb_set_configuration())
-
+
#define A_USB_GET_INTERFACE() A_CMN(usb._usb_get_interface())
#define A_USB_SET_INTERFACE() A_CMN(usb._usb_set_interface())
-
+
#define A_USB_STANDARD_CMD() A_CMN(usb._usb_standard_cmd())
#define A_USB_VENDOR_CMD() A_CMN(usb._usb_vendor_cmd())
-
+
#define A_USB_POWER_OFF() A_CMN(usb._usb_power_off())
#define A_USB_RESET_FIFO() A_CMN(usb._usb_reset_fifo())
#define A_USB_GEN_WDT() A_CMN(usb._usb_gen_wdt())
#else
#define A_USB_INIT()
-#define A_USB_TASK()
+#define A_USB_TASK()
#define A_USB_INIT_PHY()
-#define A_USB_EP0_SETUP()
-#define A_USB_EP0_TX()
-#define A_USB_EP0_RX()
-
-#define A_USB_GET_CONFIG()
-#define A_USB_SET_CONFIG()
-
-#define A_USB_GET_INTERFACE()
-#define A_USB_SET_INTERFACE()
-
-#define A_USB_STANDARD_CMD()
-#define A_USB_VENDOR_CMD()
-
+#define A_USB_EP0_SETUP()
+#define A_USB_EP0_TX()
+#define A_USB_EP0_RX()
+
+#define A_USB_GET_CONFIG()
+#define A_USB_SET_CONFIG()
+
+#define A_USB_GET_INTERFACE()
+#define A_USB_SET_INTERFACE()
+
+#define A_USB_STANDARD_CMD()
+#define A_USB_VENDOR_CMD()
+
#define A_USB_POWER_OFF()
#define A_USB_RESET_FIFO()
#define A_USB_GEN_WDT()
#define A_USB_JUMP_BOOT()
#define A_USB_GET_DESCRIPTOR()
-#define A_USB_SET_ADDRESS()
-#define A_USB_SET_FEATURE()
-#define A_USB_CLEAR_FEATURE()
+#define A_USB_SET_ADDRESS()
+#define A_USB_SET_FEATURE()
+#define A_USB_CLEAR_FEATURE()
#define A_USB_GET_STATUS()
#define A_USB_SETUP_DESC()
A_CMN(timer._timer_run())
#define A_PCI_BOOT_INIT() \
- A_CMN(pci.pci_boot_init())
+ A_CMN(pci.pci_boot_init())
#define A_GMAC_BOOT_INIT() \
- A_CMN(gmac.gmac_boot_init())
+ A_CMN(gmac.gmac_boot_init())
#if SYSTEM_MODULE_ALLOCRAM
/* Default size of ALLOCRAM area */
int (* hal_linkage_check)(int sz, struct _A_os_linkage_check *);
unsigned int *start_bss;
void (* app_start)(void);
-
+
#if SYSTEM_MODULE_MEM
struct mem_api mem;
#endif
A_UINT32 pll_settling_time; /* 50us */
} cmnos_clocking_table[] = {
{A_REFCLK_10_MHZ,
- //10485760,
+ //10485760,
10000000,
- 0x0,
+ 0x0,
0x0,
0x0},
- {A_REFCLK_20_MHZ,
- //20971520,
+ {A_REFCLK_20_MHZ,
+ //20971520,
20000000,
- 0x0,
+ 0x0,
0x0,
0x0},
{A_REFCLK_40_MHZ,
- //41943040,
- 40000000,
+ //41943040,
+ 40000000,
0x0,
0x0,
0x0},
- {A_REFCLK_UNKNOWN,
- 0,
- 0x0,
+ {A_REFCLK_UNKNOWN,
+ 0,
+ 0x0,
0x0,
0x0},
};
A_UINT32 ref_clk = (clock_info->ticks_per_sec) >> 20;
A_UINT32 start_time = NOW();
unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us
-
+
while ( (NOW() - start_time) < num_ticks) {
/* busy spin */;
}
clock_info = (struct cmnos_clock_s *)&cmnos_clocking_table[i];
// HOST_INTEREST->hi_clock_info = (A_UINT32)clock_info;
-
+
#endif
}
cmnos_tick(void)
{
#if 0
-
+
set_ccompare0(xthal_get_ccompare(XTENSA_TIMER_0)+ONE_MSEC);
cticks++;
/* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail :
* The designers reached an conclusion that the spi master (the apb_spi interface control) will be
- * modified as ¡§presuming the attached flash model to be 24-bit addressing¡¨, i.e., no more
+ * modified as presuming the attached flash model to be 24-bit addressing, i.e., no more
* auto-size detection!
* Hence you are free to force the 24-bit addressing in the *.c test code.
*/
pending_intrs = A_INTR_GET_INTRENABLE()&(~CMNOS_IMASK_XTTIMER);
A_INTR_SET_INTRENABLE(pending_intrs);
A_PRINTF("- intr [0x%08x]\n\r", pending_intrs);
-
+
}
else if( db_ascii_to_hex(param2, &data)==0 )
{
delay = data;
else
delay = 3;
-
+
A_PRINTF("==>set cb to %d seconds \n\r", delay);
}
clk_sel = 4;
break;
case 40:
- clk_sel = 6;
+ clk_sel = 6;
break;
default:
clk_sel = 6;
uint32_t ratio = 1;
uint32_t baud = 19200;
uint32_t clk = 0;
-
+
if( db_ascii_to_int(param1, &clk) != -1 )
{
A_PRINTF("changing clock to %d\n", clk);
return 1;
#else
-
+
{
uint32_t ccount1;
uint32_t ccount2;
a_uint32_t ref_clk = 0;
extern a_uint32_t cticks;
-// clock change
+// clock change
//
void cmnos_clock_init_patch(a_uint32_t refclk)
{
}
// retrieve current clock setting
-//
+//
a_uint32_t cmnos_refclk_speed_get_patch(void)
{
return ref_clk;
{
a_uint32_t start_time = NOW();
unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us
-
+
while ( (NOW() - start_time) < num_ticks) {
/* busy spin */
;
}
// get current sysmem up time in milliseconds based
-//
+//
a_uint32_t cmnos_milliseconds_patch(void)
{
cmnos_tick_patch();
-
+
return (cticks);
}
#include <hif_api.h>
#include <Magpie_api.h>
#include <vdesc_api.h>
-#include <adf_os_mem.h>
+#include <adf_os_mem.h>
#include <adf_os_io.h>
#include <rom.h>
#include "hif_usb.h"
/*
- * -- support more than 64 bytes command on ep4 --
+ * -- support more than 64 bytes command on ep4 --
*/
int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe)
{
case HIF_USB_PIPE_INTERRUPT:
case HIF_USB_PIPE_COMMAND:
return 512;
-
+
default:
return 1600;
}
default_data[6] = 0x1aaabe40;
default_data[7] = 0xbe105554;
default_data[8] = 0x00043007;
-
+
for(i=0; i<9; i++)
{
A_DELAY_USECS(10);
-
+
iowrite32(0x10ff4040, default_data[i]);
}
A_DELAY_USECS(10);
* -- turn_off_phy --
*
* . write shift register to both pcie ep and rc
- * .
+ * .
*/
static void turn_off_phy()
for(i=0; i<9; i++)
{
- // check for the done bit to be set
+ // check for the done bit to be set
while (1)
{
if (ioread32(0x40028) & BIT31)
break;
}
-
+
A_DELAY_USECS(1);
-
+
iowrite32(0x40024, default_data[i]);
}
iowrite32(0x40028, BIT0);
static void turn_off_phy_rc()
{
-
+
volatile uint32_t default_data[9];
uint32_t i=0;
-
+
A_PRINTF("turn_off_phy_rc\n");
-
+
default_data[0] = 0x9248fd00;
default_data[1] = 0x24924924;
default_data[2] = 0xa8000019;
default_data[6] = 0x1aaabe40;
default_data[7] = 0xbe105554;
default_data[8] = 0x00043007;
-
+
for(i=0; i<9; i++)
{
- // check for the done bit to be set
-
+ // check for the done bit to be set
+
while (1)
{
if (ioread32(0x40028) & BIT31)
* -- patch zfTurnOffPower --
*
* . set suspend counter to non-zero value
- * .
+ * .
*/
void zfTurnOffPower_patch(void)
{
//32clk wait for External ETH PLL stable
A_DELAY_USECS(100);
-
+
iowrite32(0x52000, 0x70303); /* read back 0x703f7 */
iowrite32(0x52008, 0x0e91c); /* read back 0x1e948 */
-
+
io32_set(MAGPIE_REG_SUSPEND_ENABLE_ADDR, BIT0);
- // wake up, and turn on cpu, eth, pcie and usb pll
+ // wake up, and turn on cpu, eth, pcie and usb pll
_fw_power_on();
// restore gpio and other settings
_fw_restore_dma_fifo();
A_PRINTF("0x4048 0x%x ......\n", ioread32(0x10ff4048));
A_PRINTF("0x404C 0x%x ......\n", ioread32(0x10ff404C));
A_PRINTF("0x4088 0x%x ......\n", ioread32(0x10ff4088));
-
+
// turn off merlin
turn_off_merlin();
// pcie ep
io32_clr(0x40040, BIT0 | BIT1);
A_PRINTF("turn_off_magpie_ep_end ......\n");
- // pcie rc
+ // pcie rc
A_PRINTF("turn_off_magpie_rc_start ......\n");
A_DELAY_USECS(measure_time);
io32_clr(0x40040, BIT0);
A_PRINTF("0x4001C %p ......\n", ioread32(0x4001c));
A_PRINTF("0x40040 %p ......\n", ioread32(0x40040));
-
+
/* turn off pcie_pll - power down (bit16) */
A_PRINTF(" before pwd PCIE PLL CFG:0x5601C: 0x%08x\n",
ioread32(0x5601C));
* 2. turn off CPU PLL
* 3. turn off ETH PLL
* 4. disable ETH PLL bypass and update
- * 4.1 set suspend timeout
+ * 4.1 set suspend timeout
* 5. set SUSPEND_ENABLE
*/
}
static void _fw_power_on()
-{
+{
/*
* 1. turn on CPU PLL
* 2. disable CPU bypass
* 3. turn on ETH PLL
* 4. disable ETH PLL bypass and update
* 5. turn on pcie pll
- */
+ */
io32_clr(MAGPIE_REG_ETH_PLL_ADDR, BIT16);
static void _fw_restore_dma_fifo(void)
{
io32_clr(0x5601C, BIT18);
-
+
/* reset pcie_rc shift */
io32_clr(0x50010, BIT10 | BIT8 | BIT7);
A_DELAY_USECS(1);
}
/*
- * support more than 64 bytes command on ep4
+ * support more than 64 bytes command on ep4
*/
void usb_reg_out_patch(void)
{
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * @File:
- *
+ * @File:
+ *
* @Abstract: host target communications
- *
- * @Notes:
+ *
+ * @Notes:
*/
#include <osapi.h>
-#include <Magpie_api.h>
+#include <Magpie_api.h>
#include <htc.h>
#include <htc_api.h>
#include <hif_api.h>
-#include <adf_os_mem.h>
-#include <adf_os_io.h>
+#include <adf_os_mem.h>
+#include <adf_os_io.h>
-#include "htc_internal.h"
+#include "htc_internal.h"
#define A_UNCACHED_ADDR(addr) addr
void _HTC_ResumeRecv(HTC_ENDPOINT_ID EndpointID);
LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg);
LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg);
-LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId);
+LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId);
LOCAL void _HTC_Shutdown(htc_handle_t htcHandle);
-/* macro to check if the service wants to prevent credit dribbling by using
+/* macro to check if the service wants to prevent credit dribbling by using
a dynamic threshold */
#define CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint) \
if ((pEndpoint)->ConnectionFlags & HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE) { \
AdjustCreditThreshold((pEndpoint)); \
- }
+ }
LOCAL void HTC_AssembleBuffers(HTC_CONTEXT *pHTC, int Count, int Size)
{
- BUF_Pool_create_pool(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, Count, Size);
+ BUF_Pool_create_pool(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, Count, Size);
}
LOCAL htc_handle_t _HTC_Init(HTC_SETUP_COMPLETE_CB SetupComplete,
HTC_CONFIG *pConfig)
{
HIF_CALLBACK hifCBConfig;
- HTC_CONTEXT *pHTC;
-
+ HTC_CONTEXT *pHTC;
+
pHTC = (HTC_CONTEXT *)adf_os_mem_alloc(sizeof(HTC_CONTEXT));
-
+
adf_os_mem_zero(pHTC, sizeof(HTC_CONTEXT));
pHTC->OSHandle = pConfig->OSHandle;
pHTC->PoolHandle = pConfig->PoolHandle;
pHTC->hifHandle = pConfig->HIFHandle;
-
+
hifCBConfig.send_buf_done = A_INDIR(htc._HTC_SendDoneHandler);
hifCBConfig.recv_buf = A_INDIR(htc._HTC_MsgRecvHandler);
hifCBConfig.context = pHTC;
-
+
/* initialize hardware layer */
HIF_register_callback(pConfig->HIFHandle, &hifCBConfig);
-
+
/* see if the host wants us to override the number of ctrl buffers */
pHTC->NumBuffersForCreditRpts = 0;
-
+
if (0 == pHTC->NumBuffersForCreditRpts) {
/* nothing to override, simply set default */
- pHTC->NumBuffersForCreditRpts = HTC_DEFAULT_NUM_CTRL_BUFFERS;
- }
-
+ pHTC->NumBuffersForCreditRpts = HTC_DEFAULT_NUM_CTRL_BUFFERS;
+ }
+
pHTC->MaxEpPendingCreditRpts = 0;
-
+
if (0 == pHTC->MaxEpPendingCreditRpts) {
- pHTC->MaxEpPendingCreditRpts = HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS;
+ pHTC->MaxEpPendingCreditRpts = HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS;
}
/* calculate the total allocation size based on the number of credit report buffers */
pHTC->CtrlBufferAllocSize = MIN_CREDIT_BUFFER_ALLOC_SIZE * pHTC->NumBuffersForCreditRpts;
/* we need at least enough buffer space for 1 ctrl message */
pHTC->CtrlBufferAllocSize = A_MAX(pHTC->CtrlBufferAllocSize,MAX_HTC_SETUP_MSG_SIZE);
-
+
/* save the size of each buffer/credit we will receive */
pHTC->RecvBufferSize = pConfig->CreditSize; //RecvBufferSize;
pHTC->TotalCredits = pConfig->CreditNumber;
pHTC->TotalCreditsAssigned = 0;
-
+
/* setup the pseudo service that handles HTC control messages */
pHTC->HTCControlService.ProcessRecvMsg = A_INDIR(htc._HTC_ControlSvcProcessMsg);
pHTC->HTCControlService.ProcessSendBufferComplete = A_INDIR(htc._HTC_ControlSvcProcessSendComplete);
pHTC->HTCControlService.TrailerSpcCheckLimit = HTC_CTRL_BUFFER_CHECK_SIZE;
pHTC->HTCControlService.MaxSvcMsgSize = MAX_HTC_SETUP_MSG_SIZE;
pHTC->HTCControlService.ServiceCtx = pHTC;
-
+
/* automatically register this pseudo service to endpoint 1 */
pHTC->Endpoints[ENDPOINT0].pService = &pHTC->HTCControlService;
- HIF_get_default_pipe(pHTC->hifHandle, &pHTC->Endpoints[ENDPOINT0].UpLinkPipeID,
+ HIF_get_default_pipe(pHTC->hifHandle, &pHTC->Endpoints[ENDPOINT0].UpLinkPipeID,
&pHTC->Endpoints[ENDPOINT0].DownLinkPipeID);
-
+
/* Initialize control pipe so we could receive the HTC control packets */
// @TODO: msg size!
- HIF_config_pipe(pHTC->hifHandle, pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, 1);
-
+ HIF_config_pipe(pHTC->hifHandle, pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, 1);
+
/* set the first free endpoint */
pHTC->CurrentEpIndex = ENDPOINT1;
pHTC->SetupCompleteCb = SetupComplete;
-
+
/* setup buffers for just the setup phase, we only need 1 buffer to handle
* setup */
HTC_AssembleBuffers(pHTC, 4, MAX_HTC_SETUP_MSG_SIZE);
-
+
/* start hardware layer so that we can queue buffers */
HIF_start(pHTC->hifHandle);
-
+
return pHTC;
}
LOCAL void _HTC_Shutdown(htc_handle_t htcHandle)
{
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
-
+
adf_os_mem_free(pHTC);
}
LOCAL void _HTC_RegisterService(htc_handle_t htcHandle, HTC_SERVICE *pService)
{
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
-
+
/* add it to the list */
pService->pNext = pHTC->pServiceList;
pHTC->pServiceList = pService;
HTC_READY_MSG *pReady;
a_uint8_t *addr;
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
-
+
pBuffer = HTCAllocMsgBuffer(pHTC);
-
+
/* an optimization... the header length is chosen to
* be aligned on a 16 bit bounday, the fields in the message are designed to
* be aligned */
- addr = adf_nbuf_put_tail(pBuffer, sizeof(HTC_READY_MSG));
- pReady = (HTC_READY_MSG *)addr;
- A_MEMZERO(pReady,sizeof(HTC_READY_MSG));
+ addr = adf_nbuf_put_tail(pBuffer, sizeof(HTC_READY_MSG));
+ pReady = (HTC_READY_MSG *)addr;
+ A_MEMZERO(pReady,sizeof(HTC_READY_MSG));
pReady->MessageID = adf_os_htons(HTC_MSG_READY_ID);
pReady->CreditSize = adf_os_htons((A_UINT16)pHTC->RecvBufferSize);
pReady->CreditCount = adf_os_htons((A_UINT16)pHTC->TotalCredits);
pReady->MaxEndpoints = ENDPOINT_MAX;
-
+
/* send out the message */
HTC_SendMsg(pHTC, ENDPOINT0, pBuffer);
/* now we need to wait for service connection requests */
LOCAL void ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID,
adf_nbuf_t pBuffers, A_BOOL sendCreditFlag)
-{
+{
int nbufs = 1;
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
-
+
/* supply some head-room again */
adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH);
-
+
/* enqueue all buffers to the single mailbox */
- HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers);
-
- if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) {
+ HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers);
+
+ if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) {
A_UINT32 epCreditMask = (1 << EndpointID);
/* we are running normally */
/* update pending credit counts with the number of buffers that were added */
pHTC->Endpoints[EndpointID].CreditsToReturn += (A_INT16)nbufs;
- pHTC->Endpoints[EndpointID].CreditsConsumed -= (A_INT16)nbufs;
+ pHTC->Endpoints[EndpointID].CreditsConsumed -= (A_INT16)nbufs;
/* update bit map that this endpoint has non-zero credits */
- pHTC->EpCreditPendingMap |= epCreditMask;
+ pHTC->EpCreditPendingMap |= epCreditMask;
if (sendCreditFlag) {
HTCCheckAndSendCreditReport(pHTC, epCreditMask,&pHTC->Endpoints[EndpointID],EndpointID);
} else {
/* we have not started yet so all return operations are simply adding buffers
- * to the interface at startup, so we can keep track of how many total
+ * to the interface at startup, so we can keep track of how many total
* credits we get */
/* update global count that will be returned to the host */
pHTC->TotalCredits += nbufs;
- }
+ }
}
LOCAL void _HTC_ReturnBuffersList(htc_handle_t htcHandle,
{
ReturnBuffers(htcHandle, EndpointID, pBuffers, TRUE);
}
-
+
LOCAL void _HTC_SendMsg(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID,
adf_nbuf_t pBuffers)
{
HTC_FRAME_HDR *pHTCHdr;
int totsz;
- HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
+ HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
HTC_BUF_CONTEXT *ctx;
-
+
ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers);
-
+
/* init total size (this does not include the space we will put in for the HTC header) */
totsz = adf_nbuf_len(pBuffers);
-
+
/* the first buffer stores the header */
/* back up buffer by a header size when we pass it down, by agreed upon convention the caller
- * points the buffer to it's payload and leaves head room for the HTC header
+ * points the buffer to it's payload and leaves head room for the HTC header
* Note: in HTCSendDoneHandler(), we undo this so that the caller get's it's buffer
- * back untainted */
+ * back untainted */
pHTCHdr = (HTC_FRAME_HDR *)adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH);
-
+
/* flag that this is the header buffer that was modified */
- ctx->htc_flags |= HTC_FLAGS_BUF_HDR;
+ ctx->htc_flags |= HTC_FLAGS_BUF_HDR;
/* mark where this buffer came from */
- ctx->end_point = EndpointID;
+ ctx->end_point = EndpointID;
/* the header start is ALWAYS aligned since we DMA it directly */
/* set some fields, the rest of them will be filled below when we check for
* trailer space */
pHTCHdr->Flags = 0;
- pHTCHdr->EndpointID = EndpointID;
-
+ pHTCHdr->EndpointID = EndpointID;
+
/* check opportunistically if we can return any reports via a trailer */
do {
int room,i,totalReportBytes;
HTC_RECORD_HDR *pRecHdr;
int pipeMaxLen;
A_UINT32 roomForPipeMaxLen;
-
+
/* figure out how much room the last buffer can spare */
pipeMaxLen = HIF_get_max_msg_len(pHTC->hifHandle,
pHTC->Endpoints[EndpointID].DownLinkPipeID);
if ( roomForPipeMaxLen < 0 ) {
roomForPipeMaxLen = 0;
}
-
+
room = adf_os_min( adf_nbuf_tailroom(pBuffers), roomForPipeMaxLen);
if (room < (int)(sizeof(HTC_CREDIT_REPORT) + sizeof(HTC_RECORD_HDR))) {
/* no room for any reports */
- break;
- }
+ break;
+ }
/* note, a record header only has 8 bit fields, so this is safe.
- * we need an uncached pointer here too */
+ * we need an uncached pointer here too */
totalReportBytes = 0;
-
- /* get a copy */
- creditsPendingMap = pHTC->EpCreditPendingMap;
-
+
+ /* get a copy */
+ creditsPendingMap = pHTC->EpCreditPendingMap;
+
/* test pending map to see if we can send a report , if any
- * credits are available, we might as well send them on the
+ * credits are available, we might as well send them on the
* unused space in the buffer */
- if (creditsPendingMap) {
-
+ if (creditsPendingMap) {
+
pRecHdr = (HTC_RECORD_HDR *)adf_nbuf_put_tail(pBuffers,
sizeof(HTC_RECORD_HDR));
-
+
/* set the ID, the length will be updated with the number of credit reports we
* can fit (see below) */
pRecHdr->RecordID = HTC_RECORD_CREDITS;
pRecHdr->Length = 0;
- /* the credit report follows the record header */
+ /* the credit report follows the record header */
totalReportBytes += sizeof(HTC_RECORD_HDR);
room -= sizeof(HTC_RECORD_HDR);
-
+
/* walkthrough pending credits map and build the records */
- for (i = 0;
- (creditsPendingMap != 0) && (room >= (int)sizeof(HTC_CREDIT_REPORT));
- i++) {
+ for (i = 0;
+ (creditsPendingMap != 0) && (room >= (int)sizeof(HTC_CREDIT_REPORT));
+ i++) {
compareMask = (1 << i);
if (compareMask & creditsPendingMap) {
-
+
pCreditRpt = (HTC_CREDIT_REPORT *)adf_nbuf_put_tail(pBuffers,
sizeof(HTC_CREDIT_REPORT));
-
+
/* clear pending mask, we are going to return all these credits */
creditsPendingMap &= ~(compareMask);
/* add this record */
pCreditRpt->EndpointID = i;
pCreditRpt->Credits = (A_UINT8)pHTC->Endpoints[i].CreditsToReturn;
/* remove pending credits, we always send deltas */
- pHTC->Endpoints[i].CreditsToReturn = 0;
+ pHTC->Endpoints[i].CreditsToReturn = 0;
/* adjust new threshold for this endpoint if needed */
CHECK_AND_ADJUST_CREDIT_THRESHOLD(&pHTC->Endpoints[i]);
/* update this record length */
}
}
}
-
- /* update new pending credits map */
+
+ /* update new pending credits map */
pHTC->EpCreditPendingMap = creditsPendingMap;
}
-
+
if (totalReportBytes <= 0) {
break;
}
-
+
/* must fit into a byte, this should never actually happen since
- * the maximum possible number of endpoints is 32.
+ * the maximum possible number of endpoints is 32.
* The trailer can have at most 1 credit record with up to 32 reports in the record.
* The trailer can have at most 1 lookahead record with only 1 lookahead report in the record.
*/
-
- /* set header option bytes */
+
+ /* set header option bytes */
pHTCHdr->ControlBytes[0] = totalReportBytes;
/* HTC frame contains a trailer */
pHTCHdr->Flags |= HTC_FLAGS_RECV_TRAILER;
/* increment total size by the reports we added */
totsz += totalReportBytes;
- /* adjust the last buffer we used for adding on the trailer */
+ /* adjust the last buffer we used for adding on the trailer */
} while (FALSE);
-
+
if (totsz == 0) {
}
-
+
/* set length for message (this includes any reports that were added above) */
- pHTCHdr->PayloadLen = adf_os_htons(totsz);
- HIF_send_buffer(pHTC->hifHandle, pHTC->Endpoints[EndpointID].DownLinkPipeID, pBuffers);
+ pHTCHdr->PayloadLen = adf_os_htons(totsz);
+ HIF_send_buffer(pHTC->hifHandle, pHTC->Endpoints[EndpointID].DownLinkPipeID, pBuffers);
}
void _HTC_PauseRecv(HTC_ENDPOINT_ID EndpointID)
int _HTC_GetReservedHeadroom(htc_handle_t htcHandle)
{
- HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
-
+ HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle;
+
return HTC_HDR_LENGTH + HIF_get_reserved_headroom(pHTC->hifHandle);
}
void htc_module_install(struct htc_apis *pAPIs)
-{
+{
pAPIs->_HTC_Init = _HTC_Init;
pAPIs->_HTC_ReturnBuffers = _HTC_ReturnBuffers;
pAPIs->_HTC_ReturnBuffersList = _HTC_ReturnBuffersList;
pAPIs->_HTC_Ready = _HTC_Ready;
pAPIs->_HTC_RegisterService = _HTC_RegisterService;
- pAPIs->_HTC_SendMsg = _HTC_SendMsg;
+ pAPIs->_HTC_SendMsg = _HTC_SendMsg;
pAPIs->_HTC_Shutdown = _HTC_Shutdown;
pAPIs->_HTC_GetReservedHeadroom = _HTC_GetReservedHeadroom;
pAPIs->_HTC_MsgRecvHandler = HTCMsgRecvHandler;
}
/* free message to the free list */
-LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t buf)
+LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t buf)
{
- BUF_Pool_free_buf(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, buf);
+ BUF_Pool_free_buf(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, buf);
}
/* HTC control message allocator (also used for empty frames to send trailer options) */
{
return BUF_Pool_alloc_buf(pHTC->PoolHandle,
POOL_ID_HTC_CONTROL,
- HTC_GetReservedHeadroom(pHTC));
+ HTC_GetReservedHeadroom(pHTC));
}
LOCAL void HTCCheckAndSendCreditReport(HTC_CONTEXT *pHTC, A_UINT32 EpMask,
HTC_ENDPOINT *pEndpoint, HTC_ENDPOINT_ID Eid)
{
adf_nbuf_t pCredBuffer;
- HTC_BUF_CONTEXT *ctx;
-
+ HTC_BUF_CONTEXT *ctx;
+
do {
/* check if host needs credits */
if (!(pHTC->EpHostNeedsCreditMap & EpMask)) {
/* host does not need any credits for this set */
- break;
+ break;
}
/* check if any are pending */
if (!(pHTC->EpCreditPendingMap & EpMask)) {
/* nothing to send up */
- break;
- }
+ break;
+ }
/* was an endpoint specified? */
if (pEndpoint != NULL) {
/* see if a threshold is in effect for this endpoint */
break;
}
}
-
+
if (pEndpoint->PendingCreditReports >= pHTC->MaxEpPendingCreditRpts) {
/* this endpoint already has some reports outstanding */
/* flag that as soon as a buffer is reaped, we issue a credit update to
* pick up this credit that is being held up because the endpoint has already
- * exceeded the max outstanding credit report limit */
+ * exceeded the max outstanding credit report limit */
pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON;
- break;
- }
+ break;
+ }
}
-
+
/* if we get here we have some credits to send up */
-
+
/* allocate a message buffer for the trailer */
pCredBuffer = HTCAllocMsgBuffer(pHTC);
if (NULL == pCredBuffer) {
* have to wait until we get our endpoint 0 messages back.. */
/* mark that we need to send an update as soon as we can get a buffer back */
pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON;
- break;
+ break;
}
-
+
ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pCredBuffer);
if (pEndpoint != NULL) {
/* keep track of pending reports */
- pEndpoint->PendingCreditReports++;
+ pEndpoint->PendingCreditReports++;
/* save the endpoint in order to decrement the count when the send completes */
ctx->htc_flags = Eid | HTC_FLAGS_CREDIT_RPT;
- }
-
+ }
+
/* this is an empty message, the HTC_SendMsg will tack on a trailer in the remaining
* space, NOTE: no need to flush the cache, the header and trailers are assembled
* using uncached addresses */
- HTC_SendMsg(pHTC, ENDPOINT0, pCredBuffer);
-
- } while (FALSE);
+ HTC_SendMsg(pHTC, ENDPOINT0, pCredBuffer);
+
+ } while (FALSE);
}
-
+
/* called in response to the arrival of a service connection message */
LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg)
{
HTC_CONNECT_SERVICE_RESPONSE_MSG *pRspMsg;
int metaDataOutLen = 0;
A_UINT16 serviceId = adf_os_ntohs(pMsg->ServiceID);
-
+
pBuffer = HTCAllocMsgBuffer(pHTC);
/* note : this will be aligned */
pRspMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)
adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG));
-
+
A_MEMZERO(pRspMsg,sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG));
pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONNECT_SERVICE_RESPONSE_ID);
/* reflect the service ID for this connect attempt */
pRspMsg->ServiceID = adf_os_htons(serviceId);
while (pService) {
-
+
if (pHTC->CurrentEpIndex >= ENDPOINT_MAX) {
/* no more endpoints */
connectStatus = HTC_SERVICE_NO_RESOURCES;
- break;
+ break;
}
if (serviceId == pService->ServiceID) {
- /* we found a match */
- A_UINT8 *pMetaDataIN = NULL;
+ /* we found a match */
+ A_UINT8 *pMetaDataIN = NULL;
A_UINT8 *pMetaDataOut;
-
+
/* outgoing meta data resides in the space after the response message */
pMetaDataOut = ((A_UINT8 *)pRspMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG);
-
+
if (pMsg->ServiceMetaLength != 0) {
/* the meta data follows the connect service message */
pMetaDataIN = ((A_UINT8 *)pMsg) + sizeof(HTC_CONNECT_SERVICE_MSG);
pMsg->ServiceMetaLength,
pMetaDataOut,
&metaDataOutLen);
-
+
/* check if the service accepted this connection request */
if (HTC_SERVICE_SUCCESS == connectStatus) {
/* set the length of the response meta data going back to the host */
pHTC->Endpoints[pHTC->CurrentEpIndex].pService = pService;
/* set connection flags */
pHTC->Endpoints[pHTC->CurrentEpIndex].ConnectionFlags = pMsg->ConnectionFlags;
-
+
pHTC->Endpoints[pHTC->CurrentEpIndex].DownLinkPipeID = pMsg->DownLinkPipeID;
pHTC->Endpoints[pHTC->CurrentEpIndex].UpLinkPipeID = pMsg->UpLinkPipeID;
-
+
/* mark that we are now connected */
pService->ServiceFlags |= HTC_SERVICE_FLAGS_CONNECTED;
/* bump up our index, this EP is now in use */
- pHTC->CurrentEpIndex++;
+ pHTC->CurrentEpIndex++;
}
break;
- }
-
- pService = pService->pNext;
+ }
+
+ pService = pService->pNext;
}
-
- pRspMsg->Status = connectStatus;
-
+
+ pRspMsg->Status = connectStatus;
+
/* send out the response message */
- HTC_SendMsg(pHTC, ENDPOINT0, pBuffer);
+ HTC_SendMsg(pHTC, ENDPOINT0, pBuffer);
}
LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg)
{
adf_nbuf_t pBuffer;
HTC_CONFIG_PIPE_RESPONSE_MSG *pRspMsg;
-
+
pBuffer = HTCAllocMsgBuffer(pHTC);
-
+
/* note : this will be aligned */
pRspMsg = (HTC_CONFIG_PIPE_RESPONSE_MSG *)
- adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG));
-
+ adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG));
+
A_MEMZERO(pRspMsg,sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG));
-
+
pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONFIG_PIPE_RESPONSE_ID);
/* reflect the service ID for this connect attempt */
pRspMsg->PipeID = pMsg->PipeID;
if ( HIF_is_pipe_supported(pHTC->hifHandle, pMsg->PipeID) ) {
- pRspMsg->Status = 0;
+ pRspMsg->Status = 0;
} else {
- pRspMsg->Status = 1;
+ pRspMsg->Status = 1;
goto config_done;
}
pRspMsg->Status = 2;
goto config_done;
}
-
+
HIF_config_pipe(pHTC->hifHandle, pMsg->PipeID, pMsg->CreditCount);
-
-config_done:
+
+config_done:
/* send out the response message */
- HTC_SendMsg(pHTC, ENDPOINT0, pBuffer);
+ HTC_SendMsg(pHTC, ENDPOINT0, pBuffer);
}
/* process an incomming control message from the host */
LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf,
adf_nbuf_t pBuffers, void *arg)
-{
+{
A_BOOL setupComplete = FALSE;
a_uint8_t *anbdata;
a_uint32_t anblen;
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg;
HTC_UNKNOWN_MSG *pMsg;
-
+
adf_os_assert(hdr_buf == ADF_NBUF_NULL);
/* we assume buffers are aligned such that we can access the message
* parameters directly*/
adf_nbuf_peek_header(pBuffers, &anbdata, &anblen);
pMsg = (HTC_UNKNOWN_MSG *)anbdata;
-
+
/* we cannot handle fragmented messages across buffers */
-
- switch ( adf_os_ntohs(pMsg->MessageID) ) {
+
+ switch ( adf_os_ntohs(pMsg->MessageID) ) {
case HTC_MSG_CONNECT_SERVICE_ID:
- HTCProcessConnectMsg(pHTC, (HTC_CONNECT_SERVICE_MSG *)pMsg);
+ HTCProcessConnectMsg(pHTC, (HTC_CONNECT_SERVICE_MSG *)pMsg);
break;
case HTC_MSG_CONFIG_PIPE_ID:
- HTCProcessConfigPipeMsg(pHTC, (HTC_CONFIG_PIPE_MSG *)pMsg);
- break;
+ HTCProcessConfigPipeMsg(pHTC, (HTC_CONFIG_PIPE_MSG *)pMsg);
+ break;
case HTC_MSG_SETUP_COMPLETE_ID:
/* the host has indicated that it has completed all
setup tasks and we can now let the services take over to
run the rest of the application */
- setupComplete = TRUE;
+ setupComplete = TRUE;
/* can't get this more than once */
break;
default:
;
- }
-
+ }
+
if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) {
/* recycle buffer only if we are fully running */
HTC_ReturnBuffers(pHTC, ENDPOINT0,pBuffers);
} else {
/* supply some head-room again */
adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH);
-
+
/* otherwise return the packet back to mbox */
- HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers);
+ HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers);
}
- if (setupComplete) {
+ if (setupComplete) {
/* mark that setup has completed */
- pHTC->StateFlags |= HTC_STATE_SETUP_COMPLETE;
+ pHTC->StateFlags |= HTC_STATE_SETUP_COMPLETE;
if (pHTC->SetupCompleteCb != NULL) {
pHTC->SetupCompleteCb();
}
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg;
HTC_BUF_CONTEXT *ctx;
HTC_ENDPOINT_ID creditRptEndpoint;
-
- ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers);
-
+
+ ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers);
+
/* put them back into the pool */
- if ( ctx->htc_flags & HTC_FLAGS_CREDIT_RPT ) {
- /* extract the endpoint number that requested this credit report */
- creditRptEndpoint = ctx->htc_flags & HTC_FLAGS_CRPT_EP_MASK;
- pHTC->Endpoints[creditRptEndpoint].PendingCreditReports--;
+ if ( ctx->htc_flags & HTC_FLAGS_CREDIT_RPT ) {
+ /* extract the endpoint number that requested this credit report */
+ creditRptEndpoint = ctx->htc_flags & HTC_FLAGS_CRPT_EP_MASK;
+ pHTC->Endpoints[creditRptEndpoint].PendingCreditReports--;
}
-
+
HTCFreeMsgBuffer(pHTC, pBuffers);
-
+
if (pHTC->StateFlags & HTC_SEND_CREDIT_UPDATE_SOON) {
/* this flag is set when the host could not send a credit report
* because we ran out of HTC control buffers */
pHTC->StateFlags &= ~HTC_SEND_CREDIT_UPDATE_SOON;
/* send out a report if anything is pending */
HTCCheckAndSendCreditReport(pHTC, HTC_ANY_ENDPOINT_MASK,NULL,ENDPOINT_MAX);
- }
+ }
}
LOCAL void HTCSendDoneHandler(adf_nbuf_t buf, void *context)
A_UINT8 current_eid;
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context;
HTC_BUF_CONTEXT *ctx;
-
+
ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(buf);
current_eid = ctx->end_point;
-
+
/* Walk through the buffers and fixup the ones we used for HTC headers.
* The buffer list may contain more than one string of HTC buffers comprising of an
- * HTC message so we need to check every buffer */
+ * HTC message so we need to check every buffer */
adf_nbuf_pull_head(buf, HTC_HDR_LENGTH);
-
+
pHTC->Endpoints[current_eid].pService->
- ProcessSendBufferComplete(current_eid,
- buf,
+ ProcessSendBufferComplete(current_eid,
+ buf,
pHTC->Endpoints[current_eid].pService->ServiceCtx);
}
A_INT16 creditsOutstanding = pEndpoint->CreditsToReturn + pEndpoint->CreditsConsumed;
/* set the new threshold based on the number of credits that have been consumed
* and which have not been returned by the app.
- * Note: it is okay for this threshold to be zero which indicates no threshold
- * is in use */
+ * Note: it is okay for this threshold to be zero which indicates no threshold
+ * is in use */
switch (pEndpoint->ConnectionFlags & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK) {
case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH :
creditsOutstanding >>= 2;
- break;
+ break;
case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF :
creditsOutstanding >>= 1;
break;
- case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS :
- creditsOutstanding = (creditsOutstanding * 3) >> 2;
+ case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS :
+ creditsOutstanding = (creditsOutstanding * 3) >> 2;
break;
- /* default case is unity */
+ /* default case is unity */
}
-
+
pEndpoint->CreditReturnThreshhold = creditsOutstanding;
-
+
}
LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId)
{
}
-
+
/* callback from the mailbox hardware layer when a full message arrives */
LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context)
{
A_UINT16 totsz;
HTC_ENDPOINT *pEndpoint;
A_UINT32 eidMask;
- int eid;
+ int eid;
a_uint8_t *anbdata;
a_uint32_t anblen;
HTC_FRAME_HDR *pHTCHdr;
HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context;
adf_nbuf_t tmp_nbuf;
-
+
if (hdr_buf == ADF_NBUF_NULL) {
/* HTC hdr is not in the hdr_buf */
tmp_nbuf = buffer;
else {
tmp_nbuf = hdr_buf;
}
-
- adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen);
- pHTCHdr = (HTC_FRAME_HDR *)anbdata;
-
- totsz = adf_os_ntohs(pHTCHdr->PayloadLen);
-
- eid = pHTCHdr->EndpointID;
-
+
+ adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen);
+ pHTCHdr = (HTC_FRAME_HDR *)anbdata;
+
+ totsz = adf_os_ntohs(pHTCHdr->PayloadLen);
+
+ eid = pHTCHdr->EndpointID;
+
pEndpoint = &pHTC->Endpoints[eid];
eidMask = 1 << eid;
if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) {
/* after setup we keep track of credit consumption to allow us to
- * adjust thresholds to reduce credit dribbling */
+ * adjust thresholds to reduce credit dribbling */
pEndpoint->CreditsConsumed ++;
}
* when we receive a frame with the NEED_CREDIT_UPDATE flag set .
* if the host received credits through an opportunistic path, then it can
* issue a another frame with this bit cleared, this signals the target to clear
- * the "host-needs-credit" state */
+ * the "host-needs-credit" state */
if (pHTCHdr->Flags & HTC_FLAGS_NEED_CREDIT_UPDATE) {
/* the host is running low (or is out) of credits on this
* endpoint, update mask */
- pHTC->EpHostNeedsCreditMap |= eidMask;
+ pHTC->EpHostNeedsCreditMap |= eidMask;
/* check and set new threshold since host has reached a low credit situation */
- CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint);
+ CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint);
} else {
/* clear the flag */
- pHTC->EpHostNeedsCreditMap &= ~(eidMask);
- pEndpoint->CreditReturnThreshhold = 0;
+ pHTC->EpHostNeedsCreditMap &= ~(eidMask);
+ pEndpoint->CreditReturnThreshhold = 0;
}
- /* Adjust the first buffer to point to the start of the actual
+ /* Adjust the first buffer to point to the start of the actual
payload, the first buffer contains the header */
adf_nbuf_pull_head(tmp_nbuf, HTC_HDR_LENGTH);
-
+
/* NOTE : This callback could re-queue the recv buffers within this calling context.
* The callback could also send a response message within the context of this callback
* as the result of parsing this message. In either case, if there are
- * pending credits and the host needs them, a credit report will be sent either through
+ * pending credits and the host needs them, a credit report will be sent either through
* the response message trailer or a NULL message through HTC_ReturnBuffers().
- */
-
+ */
+
pEndpoint->pService->ProcessRecvMsg(eid, hdr_buf, buffer, pEndpoint->pService->ServiceCtx);
- /* Calls to HTC_ReturnBuffers drives the endpoint credit reporting state machine.
- * We do not want to delay credits for too long in the event that the application is
+ /* Calls to HTC_ReturnBuffers drives the endpoint credit reporting state machine.
+ * We do not want to delay credits for too long in the event that the application is
* holding onto buffers for excessive periods of time. This gives us "some" better
* opportunities to send up credits. */
- HTCCheckAndSendCreditReport(pHTC, eidMask, pEndpoint, eid);
+ HTCCheckAndSendCreditReport(pHTC, eidMask, pEndpoint, eid);
}
*/
/*
* @File: htc_api.h
- *
+ *
* @Abstract: host-target communications API
- *
- * @Notes:
+ *
+ * @Notes:
*/
#ifndef __HTC_API_H__
typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx);
typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx);
-
+
/* HTC service structure :
* the caller is required to allocate storage for the service structure and register the
* structure using HTC_RegisterService() The service must set the following fields:
* */
typedef struct _HTC_SERVICE {
struct _HTC_SERVICE *pNext;
- /* Callback for processing receive messages. HTC calls this callback whenever a
+ /* Callback for processing receive messages. HTC calls this callback whenever a
* message arrives on the endpoint assigned to this service.
* HTC_BUFFER is a chain of buffers containing a full application message.
* HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */
- void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx);
+ void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx);
/* callback to process completed send buffers */
- void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx);
+ void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx);
/* optional callback when a connection request occurs.
- * The EndpointID is the assigned endpoint, the callback returns a connect
+ * The EndpointID is the assigned endpoint, the callback returns a connect
* response status code to allow or disallow the connection.
* pDataIn points to the optional meta data supplied in the connection request
- * pDataOut points to a buffer to send back meta data
+ * pDataOut points to a buffer to send back meta data
* If no callback is supplied, HTC assumes the connect is allowed */
A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService,
- HTC_ENDPOINT_ID EndpointID,
- A_UINT8 *pDataIn,
+ HTC_ENDPOINT_ID EndpointID,
+ A_UINT8 *pDataIn,
int LengthIn,
A_UINT8 *pDataOut,
- int *pLengthOut);
+ int *pLengthOut);
A_UINT16 ServiceID; /* service ID to match connection requests */
A_UINT16 ServiceFlags; /* service flags */
A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */
A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer
- data. This should be set to the smallest HTC buffer that can be sent
+ data. This should be set to the smallest HTC buffer that can be sent
through the service. The service can disable trailer data insertion
by setting this value to 0. */
void *ServiceCtx;
typedef struct _HTC_BUF_CONTEXT {
A_UINT8 end_point;
- A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */
+ A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */
} HTC_BUF_CONTEXT;
typedef void* htc_handle_t;
* setup complete function, supplied by HTC caller at HTC_init time.
* HTC calls this function after the host has indicated that the service connection
* phase is complete.
- *
+ *
*/
typedef void (* HTC_SETUP_COMPLETE_CB)(void);
struct htc_apis {
- htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig);
+ htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig);
void (* _HTC_Shutdown)(htc_handle_t);
void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *);
void (* _HTC_Ready)(htc_handle_t);
void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t);
void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t);
- void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t);
+ void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t);
int (* _HTC_GetReservedHeadroom)(htc_handle_t handle);
-
+
/* These APIs below are for patch purpose only */
void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context);
void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context);
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * @File:
- *
+ * @File:
+ *
* @Abstract: internal data and structure definitions for HTC
- *
- * @Notes:
+ *
+ * @Notes:
*/
#ifndef HTC_INTERNAL_H_
(sizeof(HTC_RECORD_HDR)) * 2 ) + \
HTC_HDR_LENGTH, \
sizeof(A_UINT32)))
-/* minimum allocation for a credit message */
+/* minimum allocation for a credit message */
#define MIN_CREDIT_BUFFER_ALLOC_SIZE (MIN_BUF_SIZE_FOR_RPTS)
/* max ctrl buffers size for a setup message */
#define HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS 3 /* an EP should not have more than this many outstanding reports */
-#define HTC_FLAGS_CRPT_EP_MASK 0x1F /* if the message is a credit report this is the endpoint
+#define HTC_FLAGS_CRPT_EP_MASK 0x1F /* if the message is a credit report this is the endpoint
that issued it */
#define HTC_FLAGS_CREDIT_RPT (1 << 5) /* the buffer was a credit report */
#define HTC_FLAGS_BUF_HDR (1 << 6) /* the buffer was manipulated and a header added */
#define HTC_FLAGS_RECV_END_MSG (1 << 7) /* this buffer is the last buffer for the recev
- message (used for recv pause logic) */
-
+ message (used for recv pause logic) */
+
#define HTC_MAILBOX 0 /* we use mailbox 0 for all communications */
#define HTC_ANY_ENDPOINT_MASK 0xFFFFFFFF
#define HTC_LOOKAHEAD_POST_VALID 0x55
typedef struct _HTC_ENDPOINT {
A_INT16 CreditsToReturn; /* credits that are ready to be returned to the host */
HTC_SERVICE *pService; /* service that is bound to this endpoint */
-#ifdef HTC_PAUSE_RESUME_REF_COUNTING
+#ifdef HTC_PAUSE_RESUME_REF_COUNTING
int PauseRefCount; /* reference count */
#endif
A_INT16 CreditReturnThreshhold; /* threshold before credits are returned via NULL pkts,
- this reduces dribbling effect */
- A_INT16 CreditsConsumed; /* number of credits consumed (outstanding) on the endpoint */
- A_UINT16 ConnectionFlags; /* HTC connection flags */
- int PendingCreditReports; /* no. of pending credit reports issued by this endpoint */
+ this reduces dribbling effect */
+ A_INT16 CreditsConsumed; /* number of credits consumed (outstanding) on the endpoint */
+ A_UINT16 ConnectionFlags; /* HTC connection flags */
+ int PendingCreditReports; /* no. of pending credit reports issued by this endpoint */
A_UINT8 DownLinkPipeID; /* The pipe ID to be use for the direction: target -> host */
A_UINT8 UpLinkPipeID; /* The pipe ID to be use for the direction: host -> target */
} HTC_ENDPOINT;
pool_handle_t PoolHandle;
// Left a door for extension the structure
- void *pReserved;
+ void *pReserved;
} HTC_CONTEXT;
#define HTC_STATE_SETUP_COMPLETE (1 << 0) /* HTC host-target setup is complete */
*
* By convention, hostless boards set INTERFACE to SDIO, and INFO to
* something OTHER than SDIO_NORMAL or 0.
- *
+ *
* Layout of Board HW Cfg Info is below. These values are captured at
* reset and made available to software.
*
((void *)((((A_UINT32)(addr)) & ~A_MIPS_KSEG_MASK) | A_MIPS_KSEG_CACHED))
/* Read/Write a 32-bit AR6000 SOC register, specified by its physical address */
-#define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr)))
+#define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr)))
#define A_SOC_ADDR_WRITE(addr, val) \
do { \
#define A_UNCACHED_ADDR(addr) (addr)
#define A_CACHED_ADDR(addr) (addr)
-#define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)(addr)))
+#define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)(addr)))
#define A_SOC_ADDR_WRITE(addr, val) \
do { \
HF_TIMER_CONTROL_RESET_MASK); \
} while (0)
-/*
+/*
* Turn it OFF when you're done:
*/
#define A_TIMESTAMP_DISABLE() A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, 0)
*/
/**
* @defgroup adf_nbuf_public network buffer API
- */
+ */
/**
* @ingroup adf_nbuf_public
* @file adf_nbuf.h
* This file defines the network buffer abstraction.
- */
+ */
#ifndef _ADF_NBUF_H
#define _ADF_NBUF_H
* - need space in adf_drv's software descriptor
* - are typically created during adf_drv_create
* - need to be created before any API(adf_nbuf_map) that uses them
- *
+ *
* @param[in] osdev os device
* @param[out] dmap map handle
- *
+ *
* @return status of the operation
*/
static inline a_status_t
/**
* @brief Delete a dmap map
- *
+ *
* @param[in] osdev os device
* @param[in] dmap
*/
* @return status of the operation
*/
static inline a_status_t
-adf_nbuf_map(adf_os_device_t osdev,
- adf_os_dma_map_t bmap,
- adf_nbuf_t buf,
+adf_nbuf_map(adf_os_device_t osdev,
+ adf_os_dma_map_t bmap,
+ adf_nbuf_t buf,
adf_os_dma_dir_t dir)
{
return __adf_nbuf_map(osdev, bmap, buf, dir);
* @param[in] dir DMA direction
*/
static inline void
-adf_nbuf_unmap(adf_os_device_t osdev,
- adf_os_dma_map_t bmap,
+adf_nbuf_unmap(adf_os_device_t osdev,
+ adf_os_dma_map_t bmap,
adf_os_dma_dir_t dir)
{
__adf_nbuf_unmap(osdev, bmap, dir);
/**
* @brief returns information about the mapped buf
- *
+ *
* @param[in] bmap map handle
* @param[out] sg map info
*/
* The nbuf created is guarenteed to have only 1 physical segment
*
* @param[in] hdl platform device object
- * @param[in] size data buffer size for this adf_nbuf including max header
+ * @param[in] size data buffer size for this adf_nbuf including max header
* size
* @param[in] reserve headroom to start with.
* @param[in] align alignment for the start buffer.
*
* @return The new adf_nbuf instance or NULL if there's not enough memory.
*/
-static inline adf_nbuf_t
+static inline adf_nbuf_t
adf_nbuf_alloc(adf_os_size_t size,
int reserve,
int align)
* buf. Note that this can allocate a new buffer, or
* change geometry of the orignial buffer. The new buffer
* is returned in the (new_buf).
- *
+ *
* @param[in] buf (older buffer)
* @param[in] headroom
- *
+ *
* @return newly allocated buffer
*/
static inline adf_nbuf_t
/**
* @brief expand the tailroom to the new tailroom, but the buffer
* remains the same
- *
+ *
* @param[in] buf buffer
* @param[in] tailroom new tailroom
- *
+ *
* @return expanded buffer or NULL on failure
*/
static inline adf_nbuf_t
* having an extra API is that some OS do this in more
* optimized way, rather than calling realloc (head/tail)
* back to back.
- *
+ *
* @param[in] buf buffer
- * @param[in] headroom new headroom
+ * @param[in] headroom new headroom
* @param[in] tailroom new tailroom
- *
+ *
* @return expanded buffer
*/
static inline adf_nbuf_t
* effect, it also "linearizes" a buffer (which is
* perhaps why you'll use it mostly). It creates a
* writeable copy.
- *
+ *
* @param[in] buf source nbuf to copy from
- *
+ *
* @return the new nbuf
*/
static inline adf_nbuf_t
/**
* @brief link two nbufs, the new buf is piggybacked into the
* older one.
- *
+ *
* @param[in] dst buffer to piggyback into
* @param[in] src buffer to put
- *
+ *
* @return status of the call
*/
static inline void
/**
* @brief clone the nbuf (copy is readonly)
- *
+ *
* @param[in] buf nbuf to clone from
- *
+ *
* @return cloned buffer
*/
-static inline adf_nbuf_t
+static inline adf_nbuf_t
adf_nbuf_clone(adf_nbuf_t buf)
{
return(__adf_nbuf_clone(buf));
* other users.If the nbuf is a clone then this function
* creates a new copy of the data. If the buffer is not
* a clone the original buffer is returned.
- *
+ *
* @param[in] buf source nbuf to create a writable copy from
- *
+ *
* @return new buffer which is writeable
*/
-static inline adf_nbuf_t
+static inline adf_nbuf_t
adf_nbuf_unshare(adf_nbuf_t buf)
{
return(__adf_nbuf_unshare(buf));
/**
* @brief return the amount of headroom int the current nbuf
- *
+ *
* @param[in] buf buffer
- *
+ *
* @return amount of head room
*/
static inline a_uint32_t
/**
* @brief return the amount of tail space available
- *
+ *
* @param[in] buf buffer
- *
- * @return amount of tail room
+ *
+ * @return amount of tail room
*/
static inline a_uint32_t
adf_nbuf_tailroom(adf_nbuf_t buf)
/**
- *
+ *
* @brief trim data out from the end
*
* @param[in] buf buf instance
/**
* @brief test whether the nbuf is cloned or not
- *
+ *
* @param[in] buf buffer
- *
+ *
* @return TRUE if it is cloned, else FALSE
*/
static inline a_bool_t
/**
* @brief return the frag pointer & length of the frag
- *
+ *
* @param[in] buf buffer
* @param[out] sg this will return all the frags of the nbuf
- *
+ *
*/
-static inline void
-adf_nbuf_frag_info(adf_nbuf_t buf, adf_os_sglist_t *sg)
+static inline void
+adf_nbuf_frag_info(adf_nbuf_t buf, adf_os_sglist_t *sg)
{
__adf_nbuf_frag_info(buf, sg);
}
/**
* @brief return the data pointer & length of the header
- *
+ *
* @param[in] buf nbuf
* @param[out] addr data pointer
* @param[out] len length of the data
/**
* @brief get the priv pointer from the nbuf'f private space
- *
+ *
* @param[in] buf
- *
+ *
* @return data pointer to typecast into your priv structure
*/
static inline a_uint8_t *
/**
* @brief get the length of the queue
- *
+ *
* @param[in] head buf queue head
- *
+ *
* @return length of the queue
*/
static inline a_uint32_t
/**
* @brief get the first guy/packet in the queue
- *
+ *
* @param[in] head buf queue head
- *
+ *
* @return first buffer in queue
*/
-static inline adf_nbuf_t
+static inline adf_nbuf_t
adf_nbuf_queue_first(adf_nbuf_queue_t *head)
{
return (__adf_nbuf_queue_first(head));
/**
* @brief get the next guy/packet of the given buffer (or
* packet)
- *
+ *
* @param[in] buf buffer
- *
+ *
* @return next buffer/packet
*/
static inline adf_nbuf_t
/**
* @brief Check if the buf queue is empty
- *
+ *
* @param[in] nbq buf queue handle
*
* @return TRUE if queue is empty
/**
* @brief Gets the tx checksumming to be performed on this buf
- *
+ *
* @param[in] buf buffer
* @param[out] hdr_off the (tcp) header start
* @param[out] where the checksum offset
/**
* @brief Drivers that support hw checksumming use this to
* indicate checksum info to the stack.
- *
+ *
* @param[in] buf buffer
* @param[in] cksum checksum
*/
/**
* @brief Drivers that are capable of TCP Large segment offload
* use this to get the offload info out of an buf.
- *
+ *
* @param[in] buf buffer
* @param[out] tso offload info
*/
/**
* @brief This function extracts the vid & priority from an
* nbuf
- *
- *
+ *
+ *
* @param[in] hdl net handle
* @param[in] buf buffer
* @param[in] vlan vlan header
- *
+ *
* @return status of the operation
*/
static inline a_status_t
-adf_nbuf_get_vlan_info(adf_net_handle_t hdl, adf_nbuf_t buf,
+adf_nbuf_get_vlan_info(adf_net_handle_t hdl, adf_nbuf_t buf,
adf_net_vlanhdr_t *vlan)
{
return __adf_nbuf_get_vlan_info(hdl, buf, vlan);
*/
/**
- * @mainpage
+ * @mainpage
* @section Introduction
- * The Atheros Driver Framework provides a mechanism to run the Atheros
+ * The Atheros Driver Framework provides a mechanism to run the Atheros
* WLAN driver on a variety of Operating Systems and Platforms. It achieves
* this by abstracting all OS-specific and platform-specific functionality
* the driver requires. This ensures the core logic in the driver is OS-
* This component abstracts the OS network buffer. See @ref adf_nbuf_public for details.
* @subsection sec3 OS services
* This component abstracts any OS services. See @ref adf_os_public for details.
- */
+ */
#ifndef _ADF_NET_H
#define _ADF_NET_H
/*
* check for a NULL handle
* */
-#define ADF_NET_NULL __ADF_NET_NULL
+#define ADF_NET_NULL __ADF_NET_NULL
/**
* @brief this register the driver to the shim, but won't get
* any handle until create device is called.
- *
+ *
* @param[in] drv driver info structure
- *
+ *
* @return status of operation
*/
-static inline a_status_t
+static inline a_status_t
adf_net_register_drv(adf_drv_info_t *drv)
{
return(__adf_net_register_drv(drv));
/**
* @brief deregister the driver from the shim
- *
+ *
* @param[in] name driver name passed in adf_drv_info_t
*
* @see adf_net_register_drv()
/**
* @brief register a real device with the kernel
- *
+ *
* @param[in] hdl driver handle for this device
* @param[in] op per-device switch structure
* @param[in] info basic device information
- *
+ *
* @return opaque device handle
*/
-static inline adf_net_handle_t
-adf_net_dev_create(adf_drv_handle_t hdl,
- adf_dev_sw_t *op,
+static inline adf_net_handle_t
+adf_net_dev_create(adf_drv_handle_t hdl,
+ adf_dev_sw_t *op,
adf_net_dev_info_t *info)
{
return (__adf_net_dev_create(hdl, op, info));
/**
* @brief register a virtual device with the kernel.
* A virtual device is always backed by a real device.
- *
+ *
* @param[in] dev_hdl opaque device handle for the real device
* @param[in] hdl driver handle for this virtual device
* @param[in] op per-virtual-device switch structure
* @param[in] info basic virtual device information
- *
+ *
* @return opaque device handle
*
* @see adf_net_dev_create()
*/
-static inline adf_net_handle_t
-adf_net_vdev_create(adf_net_handle_t dev_hdl,
- adf_drv_handle_t hdl,
- adf_vdev_sw_t *op,
- adf_net_dev_info_t *info)
+static inline adf_net_handle_t
+adf_net_vdev_create(adf_net_handle_t dev_hdl,
+ adf_drv_handle_t hdl,
+ adf_vdev_sw_t *op,
+ adf_net_dev_info_t *info)
{
return (__adf_net_vdev_create(dev_hdl, hdl, op, info));
}
/**
* @brief Checks if the interface is running or not
- *
+ *
* @param[in] hdl opaque device handle
- *
+ *
* @return true if running, false if not
*/
static inline a_bool_t
/**
* @brief Checks if the interface is up or not
- *
+ *
* @param[in] hdl opaque device handle
- *
+ *
* @return true if up, false if not
*/
static inline a_bool_t
/**
* @brief check whether the carrier is available or not
- *
+ *
* @param[in] hdl opaque device handle
- *
+ *
* @return a_bool_t true if available, false if not
*/
-static inline a_bool_t
+static inline a_bool_t
adf_net_carrier_ok(adf_net_handle_t hdl)
{
return(__adf_net_carrier_ok(hdl));
/**
* @brief inform the networking stack that the link is down
- *
+ *
* @param[in] hdl opaque device handle
*/
-static inline void
+static inline void
adf_net_carrier_off(adf_net_handle_t hdl)
{
__adf_net_carrier_off(hdl);
/**
* @brief inform the networking stack that the link is up
- *
+ *
* @param[in] hdl opaque device handle
- *
+ *
* @see adf_net_carrier_off()
*/
-static inline void
+static inline void
adf_net_carrier_on(adf_net_handle_t hdl)
{
__adf_net_carrier_on(hdl);
*/
/**
- * @brief inform the networking stack that the device is ready to receive
+ * @brief inform the networking stack that the device is ready to receive
* transmit packets. Typically called during init.
- *
+ *
* @param[in] hdl opaque device handle
*/
-static inline void
+static inline void
adf_net_start_queue(adf_net_handle_t hdl)
{
__adf_net_start_queue(hdl);
/**
* @brief inform the networking stack to stop sending transmit packets.
* Typically called if the driver runs out of resources for the device.
- *
+ *
* @param[in] hdl opaque device handle
*/
-static inline void
+static inline void
adf_net_stop_queue(adf_net_handle_t hdl)
{
__adf_net_stop_queue(hdl);
/**
* @brief inform the native stack to resume sending packets
* to transmit.Typically called when the driver has resources
- * available again for the device.
+ * available again for the device.
*
* @note adf_net_wake_queue() is the counterpart of adf_net_stop_queue()
*
* @param[in] hdl opaque device handle
*/
-static inline void
+static inline void
adf_net_wake_queue(adf_net_handle_t hdl)
{
__adf_net_wake_queue(hdl);
/**
* @brief Check the state of the queue
- *
+ *
* @param[in] hdl opaque device handle
- *
+ *
* @return true if stopped, false if not
*/
-static inline a_bool_t
+static inline a_bool_t
adf_net_queue_stopped(adf_net_handle_t hdl)
{
return(__adf_net_queue_stopped(hdl));
/**
* @brief get interface name
- *
+ *
* @param[in] hdl opaque device handle
- *
+ *
* @return name of interface
*/
static inline const a_uint8_t *
* @brief Get OS Handle from OS device object.
*
* @param[in] osdev OS device object
- *
+ *
* @return OS handle
- */
+ */
static inline adf_os_handle_t
adf_net_dev_to_os(adf_os_device_t osdev)
{
* @brief Get OS Handle from OS net handle.
*
* @param[in] osdev OS net handle
- *
+ *
* @return OS handle
- */
+ */
static inline adf_os_handle_t
adf_net_hdl_to_os(adf_net_handle_t hdl)
{
* @ingroup adf_net_public
* @file adf_net_sw.h
* This file defines the device and virtual device switch tables.
- */
+ */
#ifndef __ADF_NET_SW_H
#define __ADF_NET_SW_H
/**
* @brief Handler for device open - mandatory interface
*/
- a_status_t (*drv_open) (adf_drv_handle_t hdl);
+ a_status_t (*drv_open) (adf_drv_handle_t hdl);
/**
* @brief Handler for device close - mandatory interface
*/
/**
* @brief Handler for ioctl - mandatory interface
*/
- a_status_t (*drv_ioctl) (adf_drv_handle_t hdl, int num,
+ a_status_t (*drv_ioctl) (adf_drv_handle_t hdl, int num,
void *data);
/**
* @brief Handler for transmission timeout - mandatory interface
*/
a_status_t (*drv_wcmd) (adf_drv_handle_t hdl, adf_net_wcmd_type_t cmd,
adf_net_wcmd_data_t *data);
- /**
- * @brief Handler for polling if polling/deferred processing required -
+ /**
+ * @brief Handler for polling if polling/deferred processing required -
* optional interface
*/
- adf_net_poll_resp_t (*drv_poll) (adf_drv_handle_t hdl, int quota,
+ adf_net_poll_resp_t (*drv_poll) (adf_drv_handle_t hdl, int quota,
int *work_done);
/**
* @brief Handler for per cpu deffered callback (e.g. for RSS) - optional
* interface
*/
- adf_net_poll_resp_t (*drv_poll_cpu) (adf_drv_handle_t hdl, int quota,
+ adf_net_poll_resp_t (*drv_poll_cpu) (adf_drv_handle_t hdl, int quota,
int *work_done, void *arg);
/**
* @brief Handler for disabling receive interrupts for polling.
/**
- * @brief Indicates what features are supported by the interface.
+ * @brief Indicates what features are supported by the interface.
*/
#define ADF_NET_LINK_SUPP_10baseT_Half (1 << 0)
#define ADF_NET_LINK_SUPP_10baseT_Full (1 << 1)
ADF_NET_LINK_SUPP_1000baseT_Full)
/**
- * @brief Indicates what features are advertised by the interface.
+ * @brief Indicates what features are advertised by the interface.
*/
#define ADF_NET_LINK_ADV_10baseT_Half (1 << 0)
#define ADF_NET_LINK_ADV_10baseT_Full (1 << 1)
typedef struct adf_net_vid{
#if defined (ADF_LITTLE_ENDIAN_MACHINE)
a_uint16_t val:12;
- a_uint8_t res:4;
+ a_uint8_t res:4;
#elif defined (ADF_BIG_ENDIAN_MACHINE)
a_uint8_t res:4;
a_uint16_t val:12;
}adf_net_cmd_data_t;
/**
- * @brief For polled devices, adf_drv responds with one of the following status in
+ * @brief For polled devices, adf_drv responds with one of the following status in
* its poll function.
*/
typedef enum {
ADF_IEEE80211_SCAN = __ADF_IEEE80211_SCAN,
ADF_IEEE80211_REPLAY = __ADF_IEEE80211_REPLAY,
ADF_IEEE80211_MICHAEL = __ADF_IEEE80211_MICHAEL,
- ADF_IEEE80211_REJOIN = __ADF_IEEE80211_REJOIN,
+ ADF_IEEE80211_REJOIN = __ADF_IEEE80211_REJOIN,
ADF_CUSTOM_PUSH_BUTTON = __ADF_CUSTOM_PUSH_BUTTON
}adf_net_wireless_event_t;
*/
/**
* Copyright (c) Atheros Communications Inc. 2002-2008
- *
+ *
*/
#ifndef __ADF_NET_WCMD_H
* Defines
*/
#define ADF_NET_WCMD_NAME_SIZE __ADF_OS_NAME_SIZE
-#define ADF_NET_WCMD_NICK_NAME 32 /**< Max Device nick name size*/
-#define ADF_NET_WCMD_MODE_NAME_LEN 6
+#define ADF_NET_WCMD_NICK_NAME 32 /**< Max Device nick name size*/
+#define ADF_NET_WCMD_MODE_NAME_LEN 6
#define ADF_NET_WCMD_IE_MAXLEN 256 /** Max Len for IE */
#define ADF_NET_WCMD_MAX_BITRATES 32
* @brief key set/get info
*/
#define ADF_NET_WCMD_KEYBUF_SIZE 16
-#define ADF_NET_WCMD_MICBUF_SIZE 16/**< space for tx+rx keys */
+#define ADF_NET_WCMD_MICBUF_SIZE 16/**< space for tx+rx keys */
#define ADF_NET_WCMD_KEY_DEFAULT 0x80/**< default xmit key */
#define ADF_NET_WCMD_ADDR_LEN 6
#define ADF_NET_WCMD_KEYDATA_SZ \
*/
#define ADF_NET_WCMD_VAPKEY_XMIT 0x01/**< xmit */
#define ADF_NET_WCMD_VAPKEY_RECV 0x02/**< recv */
-#define ADF_NET_WCMD_VAPKEY_GROUP 0x04/**< WPA group*/
-#define ADF_NET_WCMD_VAPKEY_SWCRYPT 0x10/**< Encrypt/decrypt*/
+#define ADF_NET_WCMD_VAPKEY_GROUP 0x04/**< WPA group*/
+#define ADF_NET_WCMD_VAPKEY_SWCRYPT 0x10/**< Encrypt/decrypt*/
#define ADF_NET_WCMD_VAPKEY_SWMIC 0x20/**< Enmic/Demic */
#define ADF_NET_WCMD_VAPKEY_DEFAULT 0x80/**< Default key */
* @brief Ethtool specific
*/
#define ADF_NET_WCMD_BUSINFO_LEN 32
-#define ADF_NET_WCMD_DRIVSIZ 32
-#define ADF_NET_WCMD_VERSIZ 32
-#define ADF_NET_WCMD_FIRMSIZ 32
+#define ADF_NET_WCMD_DRIVSIZ 32
+#define ADF_NET_WCMD_VERSIZ 32
+#define ADF_NET_WCMD_FIRMSIZ 32
/**
* *******************************Enums******************
*/
*/
typedef enum adf_net_wcmd_type{
/* net80211 */
- ADF_NET_WCMD_GET_RTS_THRES,
- ADF_NET_WCMD_SET_RTS_THRES,
- ADF_NET_WCMD_GET_FRAGMENT,
- ADF_NET_WCMD_SET_FRAGMENT,
- ADF_NET_WCMD_GET_VAPMODE,
+ ADF_NET_WCMD_GET_RTS_THRES,
+ ADF_NET_WCMD_SET_RTS_THRES,
+ ADF_NET_WCMD_GET_FRAGMENT,
+ ADF_NET_WCMD_SET_FRAGMENT,
+ ADF_NET_WCMD_GET_VAPMODE,
ADF_NET_WCMD_SET_VAPMODE,
- ADF_NET_WCMD_GET_BSSID,
- ADF_NET_WCMD_SET_BSSID,
- ADF_NET_WCMD_GET_NICKNAME,
- ADF_NET_WCMD_SET_NICKNAME,
- ADF_NET_WCMD_GET_FREQUENCY,
- ADF_NET_WCMD_SET_FREQUENCY,
- ADF_NET_WCMD_GET_ESSID,
- ADF_NET_WCMD_SET_ESSID,
- ADF_NET_WCMD_GET_TX_POWER,
+ ADF_NET_WCMD_GET_BSSID,
+ ADF_NET_WCMD_SET_BSSID,
+ ADF_NET_WCMD_GET_NICKNAME,
+ ADF_NET_WCMD_SET_NICKNAME,
+ ADF_NET_WCMD_GET_FREQUENCY,
+ ADF_NET_WCMD_SET_FREQUENCY,
+ ADF_NET_WCMD_GET_ESSID,
+ ADF_NET_WCMD_SET_ESSID,
+ ADF_NET_WCMD_GET_TX_POWER,
ADF_NET_WCMD_SET_TX_POWER,
ADF_NET_WCMD_GET_PARAM,
ADF_NET_WCMD_SET_PARAM,
ADF_NET_WCMD_SET_ENC,
ADF_NET_WCMD_GET_KEY,
ADF_NET_WCMD_SET_KEY,
- ADF_NET_WCMD_GET_SCAN,
- ADF_NET_WCMD_SET_SCAN,
- ADF_NET_WCMD_GET_MODE,
- ADF_NET_WCMD_SET_MODE,
- ADF_NET_WCMD_GET_CHAN_LIST,
- ADF_NET_WCMD_SET_CHAN_LIST,
- ADF_NET_WCMD_GET_WMM_PARAM,
- ADF_NET_WCMD_SET_WMM_PARAM,
+ ADF_NET_WCMD_GET_SCAN,
+ ADF_NET_WCMD_SET_SCAN,
+ ADF_NET_WCMD_GET_MODE,
+ ADF_NET_WCMD_SET_MODE,
+ ADF_NET_WCMD_GET_CHAN_LIST,
+ ADF_NET_WCMD_SET_CHAN_LIST,
+ ADF_NET_WCMD_GET_WMM_PARAM,
+ ADF_NET_WCMD_SET_WMM_PARAM,
ADF_NET_WCMD_GET_VAPNAME,
ADF_NET_WCMD_GET_IC_CAPS,
ADF_NET_WCMD_GET_RETRIES,
ADF_NET_WCMD_GET_DEV_DIALOG,
ADF_NET_WCMD_GET_DEV_PHYERR,
ADF_NET_WCMD_GET_DEV_CWM,
- ADF_NET_WCMD_GET_DEV_ETHTOOL,
+ ADF_NET_WCMD_GET_DEV_ETHTOOL,
ADF_NET_WCMD_SET_DEV_MAC,
ADF_NET_WCMD_SET_DEV_CAP,/*ATH_CAP*/
/* Device write specific */
ADF_NET_WCMD_PARAM_FAST_CC,/**< fast channel change */
/**
* 11n A-MPDU, A-MSDU support
- */
+ */
ADF_NET_WCMD_PARAM_AMPDU,/**< 11n a-mpdu support */
ADF_NET_WCMD_PARAM_AMPDU_LIMIT,/**< a-mpdu length limit */
ADF_NET_WCMD_PARAM_AMPDU_DENSITY,/**< a-mpdu density */
ADF_NET_WCMD_PARAM_RB,/**< Switch in/out of RB */
/**
* RB Detection knobs.
- */
+ */
ADF_NET_WCMD_PARAM_RB_DETECT,/**< Do RB detection */
ADF_NET_WCMD_PARAM_RB_SKIP_THRESHOLD,/**< seqno-skip-by-1s to detect */
ADF_NET_WCMD_PARAM_RB_TIMEOUT,/**< (in ms) to restore non-RB */
ADF_NET_WCMD_WMMPARAMS_AIFS,
ADF_NET_WCMD_WMMPARAMS_TXOPLIMIT,
ADF_NET_WCMD_WMMPARAMS_ACM,
- ADF_NET_WCMD_WMMPARAMS_NOACKPOLICY,
+ ADF_NET_WCMD_WMMPARAMS_NOACKPOLICY,
}adf_net_wcmd_wmmparams_t;
/**
ADF_NET_WCMD_TXPOW_DBM = 0,/**< dBm */
ADF_NET_WCMD_TXPOW_MWATT = 0x1,/**< mW */
ADF_NET_WCMD_TXPOW_RELATIVE = 0x2,/**< Arbitrary units */
- ADF_NET_WCMD_TXPOW_TYPE = 0xFF,/**< Type of value */
- ADF_NET_WCMD_TXPOW_RANGE = 0x1000/**< Range (min - max) */
+ ADF_NET_WCMD_TXPOW_TYPE = 0xFF,/**< Type of value */
+ ADF_NET_WCMD_TXPOW_RANGE = 0x1000/**< Range (min - max) */
}adf_net_wcmd_txpow_flags_t;
/**
* @brief Retry flags
ADF_NET_WCMD_RETRY_MAX = 0x2,/**< Maximum */
ADF_NET_WCMD_RETRY_RELATIVE = 0x4,/**< Not in seconds/ms/us */
ADF_NET_WCMD_RETRY_SHORT = 0x10,/**< Short packets */
- ADF_NET_WCMD_RETRY_LONG = 0x20,/**< Long packets */
+ ADF_NET_WCMD_RETRY_LONG = 0x20,/**< Long packets */
ADF_NET_WCMD_RETRY_MODIFIER = 0xFF,/**< Modify a parameter */
ADF_NET_WCMD_RETRY_LIMIT = 0x1000,/**< Max retries*/
ADF_NET_WCMD_RETRY_LIFETIME = 0x2000,/**< Max retries us*/
ADF_NET_WCMD_CWMEVENT_EXTCHRESUME,/**< ext channel sensing resume */
ADF_NET_WCMD_CWMEVENT_DESTCW20, /**< dest channel width changed to 20 */
ADF_NET_WCMD_CWMEVENT_DESTCW40, /**< dest channel width changed to 40 */
- ADF_NET_WCMD_CWMEVENT_MAX
+ ADF_NET_WCMD_CWMEVENT_MAX
} adf_net_wcmd_cwm_event_t;
/**
ADF_NET_WCMD_ETHTOOL_SWOL,/**< Set wake-on-lan options. */
ADF_NET_WCMD_ETHTOOL_GMSGLVL,/**< Get driver message level */
ADF_NET_WCMD_ETHTOOL_SMSGLVL,/**< Set driver msg level */
- ADF_NET_WCMD_ETHTOOL_NWAY_RST,/**< Restart autonegotiation. */
+ ADF_NET_WCMD_ETHTOOL_NWAY_RST,/**< Restart autonegotiation. */
ADF_NET_WCMD_ETHTOOL_GEEPROM,/**< Get EEPROM data */
ADF_NET_WCMD_ETHTOOL_SEEPROM,/** < Set EEPROM data. */
ADF_NET_WCMD_ETHTOOL_GCOALESCE,/** < Get coalesce config */
* @brief Link quality info
*/
typedef struct adf_net_wcmd_linkqty{
- a_uint8_t qual;/*link quality(retries, SNR, missed beacons)*/
+ a_uint8_t qual;/*link quality(retries, SNR, missed beacons)*/
a_uint8_t level;/*Signal level (dBm) */
a_uint8_t noise;/*Noise level (dBm) */
a_uint8_t updated;/*Update flag*/
* @brief VAP parameter range info
*/
typedef struct adf_net_wcmd_vapparam_range{
-
+
/**
* @brief Informative stuff (to choose between different
* interface) In theory this value should be the maximum
* benchmark...
*/
a_uint32_t throughput;/**< To give an idea... */
-
+
/** @brief NWID (or domain id) */
a_uint32_t min_nwid;/**< Min NWID to set */
a_uint32_t max_nwid;/**< Max NWID to set */
* quality level (using a geometric subdivision centered on the
* average). I expect that people doing the user space apps will
* feedback us on which value we need to put in each
- * driver...
+ * driver...
*/
- adf_net_wcmd_linkqty_t avg_qual;
+ adf_net_wcmd_linkqty_t avg_qual;
/**@brief Rates */
a_uint8_t num_bitrates; /**< Number of entries in the list */
a_uint16_t txpower_capa;/**< options supported */
a_uint8_t num_txpower;/**< Number of entries in the list */
a_int32_t txpower[ADF_NET_WCMD_MAX_TXPOWER];/**< in bps */
-
+
/**@brief Wireless Extension version info */
a_uint8_t we_version_compiled;/**< Must be WIRELESS_EXT */
a_uint8_t we_version_source;/**< Last update of source */
-
+
/**@brief Retry limits and lifetime */
a_uint16_t retry_capa;/**< retry options supported */
a_uint16_t retry_flags;/**< decode max/min retry limit*/
a_int32_t max_retry;/**< Max retries */
a_int32_t min_r_time;/**< Min retry lifetime */
a_int32_t max_r_time;/**< Max retry lifetime */
-
+
/**@brief Frequency */
a_uint16_t num_channels;/**< Num channels [0 - (num - 1)] */
a_uint8_t num_frequency;/**< Num entries*/
* numbers, because each entry contain its channel index
*/
adf_net_wcmd_freq_t freq[ADF_NET_WCMD_MAX_FREQ];
-
+
a_uint32_t enc_capa; /**< IW_ENC_CAPA_* bit field */
}adf_net_wcmd_vapparam_range_t;
/**
typedef adf_net_ie_info_t adf_net_wcmd_optie_t;
/**
- * @brief status of VAP interface
- */
+ * @brief status of VAP interface
+ */
typedef struct adf_net_wcmd_vapstats{
a_uint8_t status;/**< Status*/
adf_net_wcmd_linkqty_t qual;/**< Quality of the link*/
- adf_net_wcmd_discard_t discard;/**< Packet discarded counts */
+ adf_net_wcmd_discard_t discard;/**< Packet discarded counts */
adf_net_wcmd_miss_t miss;/**< Packet missed counts */
} adf_net_wcmd_vapstats_t;
* @brief MLME
*/
typedef struct adf_net_wcmd_mlme{
- adf_net_wcmd_mlme_op_type_t op;/**< operation to perform */
+ adf_net_wcmd_mlme_op_type_t op;/**< operation to perform */
a_uint8_t reason;/**< 802.11 reason code */
//a_uint8_t macaddr[ADF_NET_WCMD_ADDR_LEN];
adf_net_ethaddr_t mac;
}adf_net_wcmd_chaninfo_t;
/**
- * @brief wmm-param info
- */
+ * @brief wmm-param info
+ */
typedef struct adf_net_wcmd_wmmparaminfo{
adf_net_wcmd_wmmparams_t cmd;
a_uint32_t ac;
}adf_net_wcmd_txpower_t;
/**
- * @brief tx-power-limit info
- */
+ * @brief tx-power-limit info
+ */
typedef a_uint32_t adf_net_wcmd_txpowlimit_t;
*/
typedef struct adf_net_wcmd_vaplist{
a_uint8_t list[ADF_NET_WCMD_MAX_AP];
- a_uint32_t len;
+ a_uint32_t len;
}adf_net_wcmd_vaplist_t;
/**
* @brief list of stations
/**
* @brief ath caps info
*/
-typedef struct adf_net_wcmd_devcap{
- a_int32_t cap;
- a_int32_t setting;
-}adf_net_wcmd_devcap_t;
+typedef struct adf_net_wcmd_devcap{
+ a_int32_t cap;
+ a_int32_t setting;
+}adf_net_wcmd_devcap_t;
/**
* @brief station stats
a_uint64_t ns_rx_bytes;/**< rx data count (bytes) */
a_uint64_t ns_rx_beacons;/**< rx beacon frames */
a_uint32_t ns_rx_proberesp;/**< rx probe response frames */
-
+
a_uint32_t ns_rx_dup;/**< rx discard 'cuz dup */
a_uint32_t ns_rx_noprivacy;/**< rx w/ wep but privacy off */
a_uint32_t ns_rx_wepfail;/**< rx wep processing failed */
a_uint32_t ns_rx_decryptcrc;/**< rx decrypt failed on crc */
a_uint32_t ns_rx_unauth;/**< rx on unauthorized port */
a_uint32_t ns_rx_unencrypted;/**< rx unecrypted w/ privacy */
-
+
a_uint32_t ns_tx_data;/**< tx data frames */
a_uint32_t ns_tx_mgmt;/**< tx management frames */
a_uint32_t ns_tx_ucast;/**< tx unicast frames */
a_uint64_t ns_tx_bytes;/**< tx data count (bytes) */
a_uint32_t ns_tx_probereq;/**< tx probe request frames */
a_uint32_t ns_tx_uapsd;/**< tx on uapsd queue */
-
+
a_uint32_t ns_tx_novlantag;/**< tx discard 'cuz no tag */
a_uint32_t ns_tx_vlanmismatch;/**< tx discard 'cuz bad tag */
-
+
a_uint32_t ns_tx_eosplost;/**< uapsd EOSP retried out */
-
+
a_uint32_t ns_ps_discard;/**< ps discard 'cuz of age */
-
+
a_uint32_t ns_uapsd_triggers;/**< uapsd triggers */
-
+
/* MIB-related state */
a_uint32_t ns_tx_assoc;/**< [re]associations */
a_uint32_t ns_tx_assoc_fail;/**< [re]association failures */
/**
- * @brief ampdu info
- */
+ * @brief ampdu info
+ */
typedef struct adf_net_wcmd_ampdu_trc {
a_uint32_t tr_head;
a_uint32_t tr_tail;
} adf_net_wcmd_ampdu_trc_t;
/**
- * @brief phy stats info
- */
+ * @brief phy stats info
+ */
typedef struct adf_net_wcmd_phystats{
a_uint32_t ast_watchdog;/**< device reset by watchdog */
a_uint32_t ast_hardware;/**< fatal hardware error interrupts */
} adf_net_wcmd_phystats_t;
/**
- * @brief diag info
- */
+ * @brief diag info
+ */
typedef struct adf_net_wcmd_diag{
a_int8_t ad_name[ADF_NET_WCMD_NAME_SIZE];/**< if name*/
a_uint16_t ad_id;
typedef struct adf_net_wcmd_cwmdbg{
adf_net_wcmd_cwm_cmd_t dc_cmd;/**< dbg commands*/
adf_net_wcmd_cwm_event_t dc_arg;/**< events*/
-} adf_net_wcmd_cwmdbg_t;
+} adf_net_wcmd_cwmdbg_t;
/**
* @brief device cwm info
a_int8_t driver[ADF_NET_WCMD_DRIVSIZ];/**< driver short name */
a_int8_t version[ADF_NET_WCMD_VERSIZ];/**< driver ver string */
a_int8_t fw_version[ADF_NET_WCMD_FIRMSIZ];/**< firmware ver string*/
- a_int8_t bus_info[ADF_NET_WCMD_BUSINFO_LEN];/**< Bus info */
+ a_int8_t bus_info[ADF_NET_WCMD_BUSINFO_LEN];/**< Bus info */
a_int8_t reserved1[32];
a_int8_t reserved2[16];
a_uint32_t n_stats;/**< number of u64's from ETHTOOL_GSTATS */
- a_uint32_t testinfo_len;
+ a_uint32_t testinfo_len;
a_uint32_t eedump_len;/**< Size of data from EEPROM(bytes) */
a_uint32_t regdump_len;/**< Size of data from REG(bytes) */
}adf_net_wcmd_ethtool_t ;
adf_net_wcmd_ethtool_t drv;
}adf_net_wcmd_ethtool_info_t;
-/**
- * @brief vap create flag info
- */
+/**
+ * @brief vap create flag info
+ */
typedef enum adf_net_wcmd_vapcreate_flags{
ADF_NET_WCMD_CLONE_BSSID=0x1,/**< allocate unique mac/bssid */
- ADF_NET_WCMD_NO_STABEACONS/**< Do not setup the sta beacon timers*/
+ ADF_NET_WCMD_NO_STABEACONS/**< Do not setup the sta beacon timers*/
}adf_net_wcmd_vapcreate_flags_t;
/**
a_uint64_t tx_dropped;/**< no space available in linux */
a_uint64_t multicast;/**< multicast packets received */
a_uint64_t collisions;
-
+
/* detailed rx_errors: */
a_uint64_t rx_length_errors;
a_uint64_t rx_over_errors;/**< receiver ring buff overflow */
a_uint64_t rx_frame_errors;/**< recv'd frame alignment error */
a_uint64_t rx_fifo_errors;/**< recv'r fifo overrun */
a_uint64_t rx_missed_errors;/**< receiver missed packet */
-
+
/* detailed tx_errors */
a_uint64_t tx_aborted_errors;
a_uint64_t tx_carrier_errors;
a_uint64_t tx_fifo_errors;
a_uint64_t tx_heartbeat_errors;
a_uint64_t tx_window_errors;
-
+
/* for cslip etc */
a_uint64_t rx_compressed;
a_uint64_t tx_compressed;
/**
* @brief ioctl structure to configure the wireless interface.
- */
+ */
typedef struct adf_net_wcmd{
char if_name[ADF_NET_WCMD_NAME_SIZE];/**< Iface name*/
adf_net_wcmd_type_t type; /**< Type of wcmd */
- adf_net_wcmd_data_t data; /**< Data */
+ adf_net_wcmd_data_t data; /**< Data */
} adf_net_wcmd_t;
/**
* @brief helper macros
a_uint8_t chan;
a_uint8_t ttbt;
}adf_net_wcmd_chansw_t;
-/**
+/**
* ***************************Unresoloved*******************
*/
// typedef struct adf_net_wcmd_chansw_info{
// a_uint8_t chan;
// a_uint8_t ttbt;
// }adf_net_wcmd_chansw_info_t;
-//
+//
/**
* @brief ath mac info
*/
// typedef struct {
// a_uint16_t sa_family;/**< address family, AF_xxx*/
-// a_int8_t sa_data[ADF_NET_WCMD_ADDR_LEN];/**< 14 bytes address */
+// a_int8_t sa_data[ADF_NET_WCMD_ADDR_LEN];/**< 14 bytes address */
// }adf_net_wcmd_ath_mac_info_t;
#endif
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/**
+/**
* @ingroup adf_os_public
* @file adf_os_atomic.h
* This file abstracts an atomic counter.
*/
-
+
#ifndef _ADF_OS_ATOMIC_H
#define _ADF_OS_ATOMIC_H
*/
typedef __adf_os_atomic_t adf_os_atomic_t;
-/**
+/**
* @brief Initialize an atomic type variable
* @param[in] v a pointer to an opaque atomic variable
*/
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/**
+/**
* @ingroup adf_os_public
* @file adf_os_bitops.h
* This file abstracts bit-level operations on a stream of bytes.
* Note that nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
-static inline void adf_os_test_and_set_bit_a(a_uint32_t nr,
+static inline void adf_os_test_and_set_bit_a(a_uint32_t nr,
volatile a_uint32_t *addr)
{
__adf_os_test_and_set_bit_a(nr, addr);
* Note that nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
-static inline void adf_os_test_and_set_bit(a_uint32_t nr,
+static inline void adf_os_test_and_set_bit(a_uint32_t nr,
volatile a_uint32_t *addr)
{
__adf_os_test_and_set_bit(nr, addr);
* Note that nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
-static inline void adf_os_test_and_clear_bit_a(a_uint32_t nr,
+static inline void adf_os_test_and_clear_bit_a(a_uint32_t nr,
volatile a_uint32_t *addr)
{
__adf_os_test_and_clear_bit_a(nr, addr);
* Note that nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
-static inline void adf_os_test_and_clear_bit(a_uint32_t nr,
+static inline void adf_os_test_and_clear_bit(a_uint32_t nr,
volatile a_uint32_t *addr)
{
__adf_os_test_and_clear_bit(nr, addr);
* Note that nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
-static inline void adf_os_test_and_change_bit_a(a_uint32_t nr,
+static inline void adf_os_test_and_change_bit_a(a_uint32_t nr,
volatile a_uint32_t *addr)
{
__adf_os_test_and_change_bit_a(nr, addr);
* Note that nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
-static inline void adf_os_test_and_change_bit(a_uint32_t nr,
+static inline void adf_os_test_and_change_bit(a_uint32_t nr,
volatile a_uint32_t *addr)
{
__adf_os_test_and_change_bit(nr, addr);
/**
* @brief Representation of a cipher context.
- */
+ */
typedef __adf_os_cipher_t adf_os_cipher_t;
/**
* @brief Types of crypto algorithms
- */
+ */
typedef enum adf_os_crypto_alg{
ADF_OS_CRYPTO_AES = __ADF_OS_CRYPTO_AES,
ADF_OS_CRYPTO_OTHER = __ADF_OS_CRYPTO_OTHER,
/**
* @brief allocate the cipher context
* @param[in] type crypto algorithm
- *
+ *
* @return the new cipher context
*/
static inline adf_os_cipher_t
/**
* @brief free the cipher context
- *
+ *
* @param[in] cipher cipher context
*/
static inline void
/**
* @brief set the key for cipher context with length keylen
- *
+ *
* @param[in] cipher cipher context
* @param[in] key key material
* @param[in] keylen length of key material
- *
+ *
* @return a_uint32_t
*/
static inline a_uint32_t
/**
* @brief encrypt the data with AES
- *
+ *
* @param[in] cipher cipher context
* @param[in] src unencrypted data
* @param[out] dst encrypted data
/**
* TODO This implements work queues (worker threads, kernel threads etc.).
- * Note that there is no cancel on a scheduled work. You cannot free a work
+ * Note that there is no cancel on a scheduled work. You cannot free a work
* item if its queued. You cannot know if a work item is queued or not unless
* its running, whence you know its not queued.
*
* so if, say, a module is asked to unload itself, how exactly will it make
- * sure that the work's not queued, for OS'es that dont provide such a
+ * sure that the work's not queued, for OS'es that dont provide such a
* mechanism??
*/
/**
* @brief Representation of a work queue.
- */
+ */
typedef __adf_os_work_t adf_os_work_t;
/**
* @brief Representation of a bottom half.
- */
+ */
typedef __adf_os_bh_t adf_os_bh_t;
/**
* @brief This initiallizes the Bottom half deferred handler
- *
+ *
* @param[in] hdl OS handle
* @param[in] bh bottom instance
* @param[in] func deferred function to run at bottom half interrupt
* context.
* @param[in] arg argument for the deferred function
*/
-static inline void
+static inline void
adf_os_init_bh(adf_os_handle_t hdl, adf_os_bh_t *bh,
adf_os_defer_fn_t func,void *arg)
{
/**
* @brief schedule a bottom half (DPC)
- *
+ *
* @param[in] hdl OS handle
* @param[in] bh bottom instance
*/
-static inline void
+static inline void
adf_os_sched_bh(adf_os_handle_t hdl, adf_os_bh_t *bh)
{
__adf_os_sched_bh(hdl, bh);
/**
* @brief disable the bh (synchronous)
- *
+ *
* @param[in] hdl OS handle
* @param[in] bh bottom instance
*/
-static inline void
+static inline void
adf_os_disable_bh(adf_os_handle_t hdl, adf_os_bh_t *bh)
{
__adf_os_disable_bh(hdl,bh);
/**
* @brief allocate a work/task queue, This runs in non-interrupt
* context, so can be preempted by H/W & S/W intr
- *
+ *
* @param[in] hdl OS handle
* @param[in] work work instance
* @param[in] func deferred function to run at bottom half non-interrupt
* context.
* @param[in] arg argument for the deferred function
*/
-static inline void
+static inline void
adf_os_init_work(adf_os_handle_t hdl, adf_os_work_t *work,
adf_os_defer_fn_t func, void *arg)
{
/**
* @brief Schedule a deferred task on non-interrupt context
- *
+ *
* @param[in] hdl OS handle
* @param[in] work work instance
*/
-static inline void
+static inline void
adf_os_sched_work(adf_os_handle_t hdl, adf_os_work_t *work)
{
__adf_os_sched_work(hdl, work);
*@param[in] hdl OS handle
*@param[in] work work instance
*/
-static inline void
-adf_os_disable_work(adf_os_handle_t hdl, adf_os_work_t *work)
+static inline void
+adf_os_disable_work(adf_os_handle_t hdl, adf_os_work_t *work)
{
__adf_os_disable_work(hdl, work);
}
* @param[in] size DMA buffer size
* @param[in] coherent 0 => cached.
* @param[out] dmap opaque coherent memory handle
- *
+ *
* @return returns the virtual address of the memory
*/
static inline void *
-adf_os_dmamem_alloc(adf_os_device_t osdev,
- adf_os_size_t size,
- a_bool_t coherent,
+adf_os_dmamem_alloc(adf_os_device_t osdev,
+ adf_os_size_t size,
+ a_bool_t coherent,
adf_os_dma_map_t *dmap)
{
return __adf_os_dmamem_alloc(osdev, size, coherent, dmap);
/**
* @brief Free a previously mapped DMA buffer
- *
+ *
* @param[in] osdev platform device instance
* @param[in] size DMA buffer size
* @param[in] coherent 0 => cached.
* @param[in] op op code for sync type, (see @ref adf_os_types.h)
*/
static inline void
-adf_os_dmamem_cache_sync(adf_os_device_t osdev,
- adf_os_dma_map_t dmap,
+adf_os_dmamem_cache_sync(adf_os_device_t osdev,
+ adf_os_dma_map_t dmap,
adf_os_cache_sync_t op)
{
__adf_os_dmamem_cache_sync(osdev, dmap, op);
/**
* @brief Get the cpu cache line size
- *
+ *
* @return The CPU cache line size in bytes.
*/
static inline adf_os_size_t
/**
* @brief locks the spinlock mutex in soft irq context
- *
+ *
* @param[in] lock spinlock object pointer
*/
static inline void
/**
* @brief unlocks the spinlock mutex in soft irq context
- *
+ *
* @param[in] lock spinlock object pointer
*/
static inline void
* @param[in] lock spinlock to be held for the critical region
* @param[in] func critical region function that to be executed
* @param[in] context context of the critical region function
- *
+ *
* @return Boolean status returned by the critical region function
*/
static inline a_bool_t
* @param[in] src source address
* @param[in] size buffer size
*/
-static inline void
+static inline void
adf_os_mem_move(void *dst, void *src, adf_os_size_t size)
{
__adf_os_mem_move(dst,src,size);
/**
* @brief Fill a memory buffer
- *
+ *
* @param[in] buf buffer to be filled
* @param[in] b byte to fill
* @param[in] size buffer size
/**
* @brief Zero a memory buffer
- *
+ *
* @param[in] buf buffer to be zeroed
* @param[in] size buffer size
*/
/**
* @brief Specify the module's entry point.
- */
+ */
#define adf_os_virt_module_init(_mod_init_func) __adf_os_virt_module_init(_mod_init_func)
/**
* @brief Specify the module's exit point.
- */
+ */
#define adf_os_virt_module_exit(_mod_exit_func) __adf_os_virt_module_exit(_mod_exit_func)
/**
* @brief Specify the module's dependency on another module.
- */
+ */
#define adf_os_module_dep(_name,_dep) __adf_os_module_dep(_name,_dep)
/**
* @brief Export a symbol from a module.
- */
+ */
#define adf_os_export_symbol(_sym) __adf_os_export_symbol(_sym)
-
+
/**
* @brief Module parameter of type integer.
- */
+ */
#define ADF_OS_PARAM_TYPE_INT32 __ADF_OS_PARAM_TYPE_INT32
/**
* @brief Module parameter of type string.
- */
+ */
#define ADF_OS_PARAM_TYPE_STRING __ADF_OS_PARAM_TYPE_STRING
/**
- * @brief Declare a module parameter.
+ * @brief Declare a module parameter.
*
* @param[in] name name of the parameter
* @param[in] type type of the parameter
* Only two types are supported
* ADF_OS_PARAM_TYPE_STRING
* ADF_OS_PARAM_TYPE_INT32
- * For example, say, the parameters name "my_int" and "my_name" are of
- * variables of type int and string respectively. Then you would declare them
+ * For example, say, the parameters name "my_int" and "my_name" are of
+ * variables of type int and string respectively. Then you would declare them
* as follows:
* @code
* adf_os_declare_param(my_int, ADF_OS_PARAM_TYPE_INT32);
* adf_os_read_param(my_name, &softc->sc_my_name);
* @endcode
*
- * or
+ * or
* @code
* st = adf_os_read_param(my_int, &softc->sc_my_int);
* @endcode
/**
* @brief Define the entry point for the PCI module.
- */
+ */
#define adf_os_pci_module_init(_fn) __adf_os_pci_module_init(_fn)
/**
* @brief Define the exit point for the PCI module.
- */
+ */
#define adf_os_pci_module_exit(_fn) __adf_os_pci_module_exit(_fn)
/**
* @brief Setup the following driver information: name, PCI IDs of devices
* supported and some device handlers.
- */
+ */
#define adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume) \
__adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume)
* @param[out] val value read
*
* @return status of operation
- */
-static inline int
+ */
+static inline int
adf_os_pci_config_read8(adf_os_device_t osdev, int offset, a_uint8_t *val)
{
return __adf_os_pci_config_read8(osdev, offset, val);
* @param[in] val value to write
*
* @return status of operation
- */
-static inline int
+ */
+static inline int
adf_os_pci_config_write8(adf_os_device_t osdev, int offset, a_uint8_t val)
{
return __adf_os_pci_config_write8(osdev, offset, val);
* @param[out] val value read
*
* @return status of operation
- */
-static inline int
+ */
+static inline int
adf_os_pci_config_read16(adf_os_device_t osdev, int offset, a_uint16_t *val)
{
return __adf_os_pci_config_read16(osdev, offset, val);
* @param[in] val value to write
*
* @return status of operation
- */
-static inline int
+ */
+static inline int
adf_os_pci_config_write16(adf_os_device_t osdev, int offset, a_uint16_t val)
{
return __adf_os_pci_config_write16(osdev, offset, val);
* @param[out] val value read
*
* @return status of operation
- */
-static inline int
+ */
+static inline int
adf_os_pci_config_read32(adf_os_device_t osdev, int offset, a_uint32_t *val)
{
return __adf_os_pci_config_read32(osdev, offset, val);
* @param[in] val value to write
*
* @return status of operation
- */
-static inline int
+ */
+static inline int
adf_os_pci_config_write32(adf_os_device_t osdev, int offset, a_uint32_t val)
{
return __adf_os_pci_config_write32(osdev, offset, val);
/**
* @brief Specify the module's entry point.
- */
+ */
#define adf_os_pseudo_module_init(_fn) __adf_os_pseudo_module_init(_fn)
/**
* @brief Specify the module's exit point.
- */
+ */
#define adf_os_pseudo_module_exit(_fn) __adf_os_pseudo_module_exit(_fn)
/**
* @brief Setup the following driver information: name, pseudo IDs of devices
* supported and some device handlers.
- */
+ */
#define adf_os_pseudo_set_drv_info(_name, _ifname, _pseudo_ids, _attach, _detach, \
_suspend, _resume) \
__adf_os_pseudo_set_drv_info(_name, _ifname, _pseudo_ids, \
*/
/**
* @defgroup adf_os_public OS abstraction API
- */
+ */
/**
* @ingroup adf_os_public
#include <adf_os_types_pvt.h>
/**
- * @brief basic data types.
+ * @brief basic data types.
*/
typedef enum {
A_FALSE,
- A_TRUE
+ A_TRUE
}a_bool_t;
typedef __a_uint8_t a_uint8_t;
/**
* @brief count the number of ticks elapsed from the time when
* the system booted
- *
+ *
* @return ticks
*/
static inline unsigned long
*
* @param[in] ticks number of ticks
* @return time in milliseconds
- */
+ */
static inline a_uint32_t
adf_os_ticks_to_msecs(unsigned long ticks)
{
*
* @param[in] time in milliseconds
* @return number of ticks
- */
+ */
static inline unsigned long
adf_os_msecs_to_ticks(a_uint32_t msecs)
{
/**
* @brief Check if _a is later than _b.
- */
+ */
#define adf_os_time_after(_a, _b) __adf_os_time_after(_a, _b)
/**
* @brief Check if _a is prior to _b.
- */
+ */
#define adf_os_time_before(_a, _b) __adf_os_time_before(_a, _b)
/**
* @brief Check if _a atleast as recent as _b, if not later.
- */
+ */
#define adf_os_time_after_eq(_a, _b) __adf_os_time_after_eq(_a, _b)
#endif
-
+
/**
* @brief Initialize a timer
- *
+ *
* @param[in] hdl OS handle
* @param[in] timer timer object pointer
* @param[in] func timer function
/**
* @brief Start a one-shot timer
- *
+ *
* @param[in] timer timer object pointer
* @param[in] msec expiration period in milliseconds
*/
* @brief Cancel a timer
*
* @param[in] timer timer object pointer
- *
+ *
* @retval TRUE timer was cancelled and deactived
* @retval FALSE timer was cancelled but already got fired.
*/
#define ADF_OS_MAX_SCATTER __ADF_OS_MAX_SCATTER
/**
* @brief Max number of scatter-gather segments.
- */
+ */
#define ADF_OS_MAX_SGLIST 4
/**
* @brief denotes structure is packed.
- */
+ */
#define adf_os_packed __adf_os_packed
/**
/**
* @brief DMA mapping object.
- */
+ */
typedef __adf_os_dma_map_t adf_os_dma_map_t;
/**
* @brief DMA address.
- */
+ */
typedef __adf_os_dma_addr_t adf_os_dma_addr_t;
/**
* @brief DMA size.
- */
+ */
typedef __adf_os_dma_size_t adf_os_dma_size_t;
/**
* @brief Information inside a DMA map.
- */
+ */
typedef struct adf_os_dmamap_info{
a_uint32_t nsegs; /**< total number mapped segments*/
struct __dma_segs{
adf_os_dma_addr_t paddr; /**< physical(dma'able) address of the segment*/
adf_os_dma_size_t len; /**< length of the segment*/
- } dma_segs[ADF_OS_MAX_SCATTER];
+ } dma_segs[ADF_OS_MAX_SCATTER];
}adf_os_dmamap_info_t;
/**
* @brief Representation of a scatter-gather list.
- */
+ */
typedef struct adf_os_sglist{
a_uint32_t nsegs; /**< total number of segments*/
struct __sg_segs{
* operations, where reading a network packet or
* storage sector corresponds to a read operation in
* bus_dma.
- *
+ *
* ADF_SYNC_PREREAD Perform any synchronization
* required prior to an update
* of host memory by the DMA
} a_status_t;
/**
- * @brief An ecore needs to provide a table of all pci device/vendor id's it
+ * @brief An ecore needs to provide a table of all pci device/vendor id's it
* supports
*
* This table should be terminated by a NULL entry , i.e. {0}
/**
* @brief Representation of a h/w resource.
- */
+ */
typedef struct {
a_uint64_t start;
a_uint64_t end;
/**
* @brief Representation of bus registration data.
- */
+ */
typedef union {
adf_os_pci_dev_id_t *pci;
void *raw;
/**
* @brief Representation of data required for attach.
- */
+ */
typedef union {
adf_os_pci_dev_id_t pci;
void *raw;
/**
* @brief Types of buses.
- */
+ */
typedef enum {
ADF_OS_BUS_TYPE_PCI = 1,
ADF_OS_BUS_TYPE_GENERIC,
/**
* @brief IRQ handler response codes.
- */
+ */
typedef enum {
ADF_OS_IRQ_NONE,
ADF_OS_IRQ_HANDLED,
/**
* @brief DMA mask types.
- */
+ */
typedef enum {
ADF_OS_DMA_MASK_32BIT,
ADF_OS_DMA_MASK_64BIT,
* ADF_OS_DMA_FROM_DEVICE (data going from memory to device)
*/
typedef enum {
- ADF_OS_DMA_TO_DEVICE = __ADF_OS_DMA_TO_DEVICE,
- ADF_OS_DMA_FROM_DEVICE = __ADF_OS_DMA_FROM_DEVICE,
+ ADF_OS_DMA_TO_DEVICE = __ADF_OS_DMA_TO_DEVICE,
+ ADF_OS_DMA_FROM_DEVICE = __ADF_OS_DMA_FROM_DEVICE,
} adf_os_dma_dir_t;
/*
/**
* @brief Prototype of IRQ function.
- */
-typedef adf_os_irq_resp_t (*adf_os_drv_intr)(adf_drv_handle_t hdl);
+ */
+typedef adf_os_irq_resp_t (*adf_os_drv_intr)(adf_drv_handle_t hdl);
/**
* @brief The OS print routine.
- */
+ */
#define adf_os_print __adf_os_print
/**
/**
* @brief driver specific functions
*/
- adf_drv_handle_t (*drv_attach) (adf_os_resource_t *res, int count,
- adf_os_attach_data_t *data,
+ adf_drv_handle_t (*drv_attach) (adf_os_resource_t *res, int count,
+ adf_os_attach_data_t *data,
adf_os_device_t osdev);
void (*drv_detach) (adf_drv_handle_t hdl);
void (*drv_suspend) (adf_drv_handle_t hdl, adf_os_pm_t pm);
#define adf_os_likely(_expr) __adf_os_likely(_expr)
/**
- * @brief read memory barrier.
+ * @brief read memory barrier.
*/
#define adf_os_wmb() __adf_os_wmb()
/**
- * @brief write memory barrier.
+ * @brief write memory barrier.
*/
#define adf_os_rmb() __adf_os_rmb()
/**
- * @brief read + write memory barrier.
+ * @brief read + write memory barrier.
*/
#define adf_os_mb() __adf_os_mb()
/**
* @brief return the lesser of a, b
- */
+ */
#define adf_os_min(_a, _b) __adf_os_min(_a, _b)
/**
* @brief return the larger of a, b
- */
+ */
#define adf_os_max(_a, _b) __adf_os_max(_a, _b)
/**
* @brief assert "expr" evaluates to true.
- */
+ */
#define adf_os_assert(expr) __adf_os_assert(expr)
/**
* @brief supply pseudo-random numbers
*/
-static inline void adf_os_get_rand(adf_os_handle_t hdl,
- a_uint8_t *ptr,
+static inline void adf_os_get_rand(adf_os_handle_t hdl,
+ a_uint8_t *ptr,
a_uint32_t len)
{
__adf_os_get_rand(hdl, ptr, len);
*/
/*
* @File: Magpie_api.h
- *
+ *
* @Abstract: Magpie FW api
- *
+ *
* @Notes:
*/
#define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type))
#define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type))
#define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran))
-#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no))
-#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no))
+#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no))
+#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no))
#define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type))
#define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf))
#define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no))
#define HIF_init(pConfig) A_INDIR(hif._init(pConfig))
#define HIF_shutdown(h) A_INDIR(hif._shutdown(h))
#define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig))
-#define HIF_start(h) A_INDIR(hif._start(h))
-#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list))
-#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf))
-#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf))
-#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h))
+#define HIF_start(h) A_INDIR(hif._start(h))
+#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list))
+#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf))
+#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf))
+#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h))
#define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe))
#define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe))
#define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h))
#define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h))
#define HTC_NotifyTargetInserted(h)
-#define HTC_NotifyTargetDetached(h)
+#define HTC_NotifyTargetDetached(h)
/* WMI SVC module */
#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api)
struct sflash_api sflash;
struct hif_api hif;
struct htc_apis htc;
- WMI_SVC_APIS wmi_svc_api;
+ WMI_SVC_APIS wmi_svc_api;
struct usbfifo_api usbfifo_api;
struct buf_pool_api buf_pool;
struct vbuf_api vbuf;
* be set to 0 -- only a single arena is currently supported.
*/
void *(* cmnos_allocram)(void *which_arena, A_UINT32 nbytes);
-
+
void (* cmnos_allocram_debug)(void);
};
int table;
};
-/*
+/*
* A_INIT() handles any initialization needed by the OS abstraction,
* and it clears the application's BSS, if necessary. (Application BSS
* is not cleared if the application is linked into a single image that
{
struct _A_os_linkage_check link_check;
unsigned int *clrptr;
-
+
if (&START_BSS != _A_MAGPIE_INDIRECTION_TABLE->cmnos.start_bss) {
/* Clear BSS */
for (clrptr = &START_BSS; clrptr < &END_BSS; clrptr++) {
A_CMN(timer._timer_run())
#define A_PCI_BOOT_INIT() \
- A_CMN(pci.pci_boot_init())
+ A_CMN(pci.pci_boot_init())
#define A_GMAC_BOOT_INIT() \
- A_CMN(gmac.gmac_boot_init())
+ A_CMN(gmac.gmac_boot_init())
#if SYSTEM_MODULE_ALLOCRAM
/* Default size of ALLOCRAM area */
*/
/*
* @File: dma_engine_api.h
- *
+ *
* @Abstract: DMA Engine api
- *
+ *
* @Notes:
*/
{
struct zsDmaDesc* head;
struct zsDmaDesc* terminator;
-
+
/* Below are fields specific to TX */
VBUF *xmited_buf_head;
- VBUF *xmited_buf_tail;
+ VBUF *xmited_buf_tail;
};
/* hardware API table structure (API descriptions below) */
-struct dma_engine_api
+struct dma_engine_api
{
void (*_init)();
void (*_init_rx_queue)(struct zsDmaQueue *q);
-
+
void (*_init_tx_queue)(struct zsTxDmaQueue *q);
-
+
void (*_config_rx_queue)(struct zsDmaQueue *q, int num_desc, int buf_size);
-
+
void (*_xmit_buf)(struct zsTxDmaQueue *q, VBUF *buf);
-
+
void (*_flush_xmit)(struct zsDmaQueue *q);
-
+
VBUF* (*_reap_recv_buf)(struct zsDmaQueue *q);
-
+
void (*_return_recv_buf)(struct zsDmaQueue *q, VBUF *buf);
-
+
VBUF* (*_reap_xmited_buf)(struct zsTxDmaQueue *q);
-
+
void (*_swap_data)(struct zsDmaDesc* desc);
-
+
int (*_has_compl_packets)(struct zsDmaQueue *q);
-
+
void (*_desc_dump)(struct zsDmaQueue *q);
-
+
/* The functions below are for patchable */
struct zsDmaDesc* (*_get_packet)(struct zsDmaQueue* q);
void (*_reclaim_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc);
void (*_put_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc);
-
+
/* room to expand this table by another table */
void *pReserved;
};
A_UINT16 (*rx_init)(dma_engine_t eng_no, dma_iftype_t if_type);
void (*rx_config)(dma_engine_t eng_no, a_uint16_t num_desc,
a_uint16_t gran);
- void (*rx_start)(dma_engine_t eng_no);
+ void (*rx_start)(dma_engine_t eng_no);
A_UINT32 (*intr_status)(dma_iftype_t if_type);
A_UINT16 (*hard_xmit)(dma_engine_t eng_no, VBUF *buf);
void (*flush_xmit)(dma_engine_t eng_no);
/**
* @brief Install the DMA lib api's this for ROM patching
* support
- *
+ *
* @param apis
*/
void dma_lib_module_install(struct dma_lib_api *apis);
#define __EEPROM_API_H__
typedef enum {
- RET_SUCCESS = 0,
+ RET_SUCCESS = 0,
RET_NOT_INIT,
RET_NOT_EXIST,
RET_EEP_CORRUPT,
RET_EEP_OVERFLOW,
-
- // add return code from here
+
+ // add return code from here
RET_UNKNOWN
} T_EEP_RET;
*/
/*
* @File: HIF_api.h
- *
+ *
* @Abstract: Host Interface api
- *
+ *
* @Notes:
*/
/* hardware API table structure (API descriptions below) */
struct hif_api {
hif_handle_t (*_init)(HIF_CONFIG *pConfig);
-
+
void (* _shutdown)(hif_handle_t);
-
+
void (*_register_callback)(hif_handle_t, HIF_CALLBACK *);
-
+
int (*_get_total_credit_count)(hif_handle_t);
-
+
void (*_start)(hif_handle_t);
void (*_config_pipe)(hif_handle_t handle, int pipe, int creditCount);
-
+
int (*_send_buffer)(hif_handle_t handle, int pipe, adf_nbuf_t buf);
- void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf);
+ void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf);
//void (*_set_recv_bufsz)(int pipe, int bufsz);
//void (*_pause_recv)(int pipe);
//void (*_resume_recv)(int pipe);
int (*_is_pipe_supported)(hif_handle_t handle, int pipe);
-
+
int (*_get_max_msg_len)(hif_handle_t handle, int pipe);
-
+
int (*_get_reserved_headroom)(hif_handle_t handle);
-
+
void (*_isr_handler)(hif_handle_t handle);
-
+
void (*_get_default_pipe)(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink);
-
+
/* room to expand this table by another table */
void *pReserved;
};
#define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/
#define ETH_P_ATH 0x88bd
-
+
typedef enum hif_gmac_pipe{
HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/
HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/
#define PCI_MAX_PKT_LEN 1600
-#define PCI_MAX_DESC 2
-
+#define PCI_MAX_DESC 2
+
typedef enum hif_pci_pipe_rx{
HIF_PCI_PIPE_RX0, /*Normal Priority RX*/
HIF_PCI_PIPE_RX1,
#define _ROM_CFG_H_
/************************** FPGA version **************************/
-#define MAGPIE_FPGA_RAM_256K 0
+#define MAGPIE_FPGA_RAM_256K 0
/************************** SYSTEM WIDE ***************************/
/* Release Code :
#define WATCH_DOG_MAGIC_PATTERN_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x4) // 0x53fffc,magic pattern address
#define WATCH_DOG_RESET_COUNTER_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x8) // 0x53fff8,record the reset counter
#define DEBUG_SYSTEM_STATE_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0xc) // 0x53fff4,record the state of system
-#define CURRENT_PROGRAM_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x10) // 0x53fff0,reserved
+#define CURRENT_PROGRAM_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x10) // 0x53fff0,reserved
#define WATCH_DOG_MAGIC_PATTERN (*((volatile u32_t*)(WATCH_DOG_MAGIC_PATTERN_ADDR)))
#define WATCH_DOG_RESET_COUNTER (*((volatile u32_t*)(WATCH_DOG_RESET_COUNTER_ADDR)))
/* instruction port area */
#define SYS_I_R0M_REGION_0_BASE 0x8e0000
-
+
#define SYS_I_RAM_REGION_0_BASE 0x900000
#define SYS_I_RAM_REGION_1_BASE (SYS_I_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_I_RAM_REGION_2_BASE (SYS_I_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_I_RAM_REGION_3_BASE (SYS_I_RAM_REGION_2_BASE+SYS_RAM_BLOCK_SIZE)
-
-/* data port area */
+
+/* data port area */
#define SYS_D_R0M_REGION_0_BASE 0x4e0000
-
+
#define SYS_D_RAM_REGION_0_BASE 0x500000
#define SYS_D_RAM_REGION_1_BASE (SYS_D_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_D_RAM_REGION_2_BASE (SYS_D_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
#define USB_DEVICE_PID_SIZE 1 // PID SIZE, 1 halfword offset
#define USB_DEVICE_VID_SIZE 1 // VID SIZE, 1 halfword offset
-
+
#define USB_DESC_IN_EEPROM_FLAG_OFFSET USB_DESCRIPTOR_ADDR
#define USB_DEVICE_DESCRIPTOR_OFFSET (USB_DESC_IN_EEPROM_FLAG_OFFSET+USB_DESC_IN_EEPROM_SIZE)
#define USB_STRING00_DESCRIPTOR_OFFSET (USB_DEVICE_DESCRIPTOR_OFFSET+USB_DEVICE_DESCRIPTOR_SIZE)
#define _MEM_ADDRS_H_
#define SYS_ROM_BLOCK_SIZE (32*1024)
-#if MAGPIE_FPGA_RAM_256K == 1
+#if MAGPIE_FPGA_RAM_256K == 1
#define SYS_ROM_BLOCK_NUM 2 //ram 256K version is also rom 64k version
#else
#define SYS_ROM_BLOCK_NUM 3
#endif
#define SYS_ROM_SIZE (SYS_ROM_BLOCK_SIZE*SYS_ROM_BLOCK_NUM)
-
+
#if MAGPIE_FPGA_RAM_256K == 1
#define SYS_RAM_BLOCK_SIZE 64*1024
-#else
+#else
#define SYS_RAM_BLOCK_SIZE 40*1024
#endif
/* instruction port area */
#define SYS_I_R0M_REGION_0_BASE 0x8e0000
-
+
#define SYS_I_RAM_REGION_0_BASE 0x900000
#define SYS_I_RAM_REGION_1_BASE (SYS_I_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_I_RAM_REGION_2_BASE (SYS_I_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_I_RAM_REGION_3_BASE (SYS_I_RAM_REGION_2_BASE+SYS_RAM_BLOCK_SIZE)
-
-/* data port area */
+
+/* data port area */
#define SYS_D_R0M_REGION_0_BASE 0x4e0000
-
+
#define SYS_D_RAM_REGION_0_BASE 0x500000
#define SYS_D_RAM_REGION_1_BASE (SYS_D_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_D_RAM_REGION_2_BASE (SYS_D_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
#define USB_DEVICE_PID_SIZE 1 // PID SIZE, 1 halfword offset
#define USB_DEVICE_VID_SIZE 1 // VID SIZE, 1 halfword offset
-
+
#define USB_DESC_IN_EEPROM_FLAG_OFFSET USB_DESCRIPTOR_ADDR
#define USB_DEVICE_DESCRIPTOR_OFFSET (USB_DESC_IN_EEPROM_FLAG_OFFSET+USB_DESC_IN_EEPROM_SIZE)
#define USB_STRING00_DESCRIPTOR_OFFSET (USB_DEVICE_DESCRIPTOR_OFFSET+USB_DEVICE_DESCRIPTOR_SIZE)
} wb[MAGPIE_REGDUMP_FRAMES];
};
-typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
+typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
#define RD_SIZE sizeof(CPU_exception_frame_t)
#endif
* XTensa CPU state
* This must match the state saved by the target exception handler.
*/
-
+
#define RD_SIZE sizeof(CPU_exception_frame_t)
/*
#if defined(_ROM_)
#include "rom_cfg.h"
-#if MAGPIE_FPGA_RAM_256K == 1
-#undef MAX_BUF_NUM
+#if MAGPIE_FPGA_RAM_256K == 1
+#undef MAX_BUF_NUM
#define MAX_BUF_NUM 100
#endif
#endif
#undef SYSTEM_MODULE_DBG
-#undef MOVE_PRINT_TO_RAM
+#undef MOVE_PRINT_TO_RAM
#ifdef _DEBUG_BUILD_
#define SYSTEM_MODULE_DBG 1
#define MOVE_PRINT_TO_RAM 1
#else
#define SYSTEM_MODULE_DBG 0
-#define MOVE_PRINT_TO_RAM 1
+#define MOVE_PRINT_TO_RAM 1
#endif
#undef SYSTEM_MODULE_SFLASH
#define SYSTEM_MODULE_SFLASH 0
*/
/*
* @File: VBUF_api.h
- *
+ *
* @Abstract: Host Interface api
- *
+ *
* @Notes:
*/
typedef struct _VBUF
{
VDESC *desc_list;
- struct _VBUF *next_buf;
- A_UINT16 buf_length;
+ struct _VBUF *next_buf;
+ A_UINT16 buf_length;
A_UINT8 reserved[2];
- A_UINT8 ctx[MAX_BUF_CTX_LEN];
+ A_UINT8 ctx[MAX_BUF_CTX_LEN];
} VBUF;
#define VBUF_GET_DATA_ADDR(vbuf) (vbuf->desc_list->buf_addr + vbuf->desc_list->data_offset)
void (*_free_vbuf)(VBUF *buf);
/* room to expand this table by another table */
- void *pReserved;
+ void *pReserved;
};
extern void vbuf_module_install(struct vbuf_api *apis);
*/
/*
* @File: VBUF_api.h
- *
+ *
* @Abstract: Host Interface api
- *
+ *
* @Notes:
*/
A_UINT16 data_offset;
A_UINT16 data_size;
A_UINT16 control;
- A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE];
+ A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE];
} VDESC;
#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4)))
void (*_swap_vdesc)(VDESC *dest, VDESC *src);
/* room to expand this table by another table */
- void *pReserved;
+ void *pReserved;
};
extern void vdesc_module_install(struct vdesc_api *apis);
-#endif
+#endif
*/
/*
* @File: Magpie_api.h
- *
+ *
* @Abstract: Magpie FW api
- *
+ *
* @Notes:
*/
#define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type))
#define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type))
#define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran))
-#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no))
-#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no))
+#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no))
+#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no))
#define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type))
#define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf))
#define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no))
#define HIF_init(pConfig) A_INDIR(hif._init(pConfig))
#define HIF_shutdown(h) A_INDIR(hif._shutdown(h))
#define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig))
-#define HIF_start(h) A_INDIR(hif._start(h))
-#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list))
-#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf))
-#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf))
-#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h))
+#define HIF_start(h) A_INDIR(hif._start(h))
+#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list))
+#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf))
+#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf))
+#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h))
#define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe))
#define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe))
#define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h))
#define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h))
#define HTC_NotifyTargetInserted(h)
-#define HTC_NotifyTargetDetached(h)
+#define HTC_NotifyTargetDetached(h)
/* WMI SVC module */
#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api)
//#endif
struct hif_api hif;
struct htc_apis htc;
- WMI_SVC_APIS wmi_svc_api;
+ WMI_SVC_APIS wmi_svc_api;
struct usbfifo_api usbfifo_api;
struct buf_pool_api buf_pool;
-#ifdef MAGPIE_FW_BUILD
+#ifdef MAGPIE_FW_BUILD
struct vbuf_api vbuf;
struct vdesc_api vdesc;
struct allocram_api allocram;
-#endif
+#endif
struct dma_engine_api dma_engine;
struct dma_lib_api dma_lib;
*/
/*
* (c) Copyright Atheros Communications
- * FreeBSD specific prototypes
+ * FreeBSD specific prototypes
*/
#ifndef _ADF_NBUF_PVT_H
#define _ADF_NBUF_PVT_H
//#include <adf_nbuf_api.h>
#define __ADF_NBUF_NULL NULL
-#define __ADF_NBUF_CTX_BUF
+#define __ADF_NBUF_CTX_BUF
typedef VBUF * __adf_nbuf_t;
*/
typedef struct __adf_nbuf_qhead {
VBUF *head;
- VBUF *tail;
+ VBUF *tail;
a_uint32_t qlen;
}__adf_nbuf_qhead_t;
typedef __adf_nbuf_qhead_t __adf_nbuf_queue_t;
-__adf_nbuf_t
-__adf_nbuf_alloc(adf_os_size_t size,
- a_uint32_t reserve, a_uint32_t align);
+__adf_nbuf_t
+__adf_nbuf_alloc(adf_os_size_t size,
+ a_uint32_t reserve, a_uint32_t align);
-void
+void
__adf_nbuf_free(__adf_nbuf_t buf);
#ifndef _ROM_
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t size);
-
-a_uint8_t *
+
+a_uint8_t *
__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t size);
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t size);
#endif
-void
+void
__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t size);
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_realloc_headroom(__adf_nbuf_t buf,
- a_uint32_t headroom);
-
-__adf_nbuf_t
-__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf,
+ a_uint32_t headroom);
+
+__adf_nbuf_t
+__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf,
a_uint32_t tailroom);
-
-__adf_nbuf_t
+
+__adf_nbuf_t
__adf_nbuf_expand(__adf_nbuf_t buf,
a_uint32_t headroom, a_uint32_t tailroom);
-
-__adf_nbuf_t
+
+__adf_nbuf_t
__adf_nbuf_copy(__adf_nbuf_t src);
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_unshare(__adf_nbuf_t src);
-void
+void
__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg);
#ifndef _ROM_
-a_uint8_t *
+a_uint8_t *
__adf_nbuf_get_priv(__adf_nbuf_t buf);
#endif
-void
-__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead,
+void
+__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead,
__adf_nbuf_t buf);
-
-__adf_nbuf_t
+
+__adf_nbuf_t
__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead);
-a_uint32_t
-__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf,
- a_uint8_t **hdr_off,
+a_uint32_t
+__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf,
+ a_uint8_t **hdr_off,
a_uint8_t **where);
-
-void
+
+void
__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum);
-void
+void
__adf_nbuf_get_tso_info(__adf_nbuf_t buf, adf_nbuf_tso_t *tso);
-a_status_t
-__adf_nbuf_get_vlan_info(adf_net_handle_t hdl,
- __adf_nbuf_t buf,
- adf_net_vlanhdr_t *vlan);
-
-void
+a_status_t
+__adf_nbuf_get_vlan_info(adf_net_handle_t hdl,
+ __adf_nbuf_t buf,
+ adf_net_vlanhdr_t *vlan);
+
+void
__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg);
/**
* @brief return the last mbuf
- *
+ *
* @param m0
- *
+ *
* @return struct mbuf*
*/
#ifndef _ROM_
-VDESC *
+VDESC *
__adf_nbuf_last(VBUF *buf);
#endif
/**
* @brief num bytes in the head
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes available
*/
#ifndef _ROM_
/**
* @brief num of bytes available in the tail excluding the priv
* portion
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes
*/
#ifndef _ROM_
-a_uint32_t
+a_uint32_t
__adf_nbuf_tailroom(__adf_nbuf_t buf);
#endif
/**
* @brief get the entire packet length
- *
+ *
* @param adf_nbuf
- *
+ *
* @return total length of packet (sum of all frag lengths)
- */
+ */
#ifndef _ROM_
a_uint32_t
__adf_nbuf_len(__adf_nbuf_t buf);
/**
* @brief Clone the nbuf (will not create writeable copies)
- *
+ *
* @param adf_nbuf
- *
+ *
* @return Read-only copy of the nbuf (including clusters)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_clone(__adf_nbuf_t src);
void
/*
* @brief check if the mbuf is cloned or not
- *
+ *
* @param buf
- *
+ *
* @return a_bool_t
*/
a_bool_t
*/
#ifndef _ROM_
void
-__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
+__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
a_uint32_t *len);
#endif
* @brief init the queue
* @param qhead
*/
-void
+void
__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead);
/**
* @brief return the length of queue
* @param adf_qhead
- *
+ *
* @return length
- *
+ *
*/
-a_uint32_t
+a_uint32_t
__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead);
/**
* @brief returns the first guy in the Q
* @param qhead
- *
+ *
* @return (NULL if the Q is empty)
*/
#ifndef _ROM_
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead);
/**
* @brief return the next packet from packet chain
- *
+ *
* @param buf (packet)
- *
+ *
* @return (NULL if no packets are there)
*/
-__adf_nbuf_t
+__adf_nbuf_t
__adf_nbuf_queue_next(__adf_nbuf_t buf);
#endif
/**
* @brief check if the queue is empty or not
- *
+ *
* @param qhead
- *
+ *
* @return a_bool_t
*/
-a_bool_t
+a_bool_t
__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead);
__adf_nbuf_t
* @brief This will return the header's addr & m_len
*/
static inline void
-__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
+__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr,
a_uint32_t *len)
{
VDESC *desc = buf->desc_list;
-
+
*addr = desc->buf_addr + desc->data_offset;
- *len = desc->data_size;
+ *len = desc->data_size;
}
/**
* @brief return the last mbuf
- *
+ *
* @param m0
- *
+ *
* @return struct mbuf*
*/
-static inline VDESC *
+static inline VDESC *
__adf_nbuf_last(VBUF *buf)
{
VDESC *desc = buf->desc_list;
-
+
//for(; desc->next_desc != NULL; desc = desc->next_desc)
// ;
while(desc->next_desc != NULL)
{
desc = desc->next_desc;
}
-
+
return desc;
}
/**
* @brief num bytes in the head
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes available
*/
static inline a_uint32_t
/**
* @brief num of bytes available in the tail excluding the priv
* portion
- *
+ *
* @param adf_nbuf
- *
+ *
* @return num of bytes
*/
-static inline a_uint32_t
+static inline a_uint32_t
__adf_nbuf_tailroom(__adf_nbuf_t buf)
{
VDESC *last_desc = __adf_nbuf_last(buf);
-
+
return last_desc->buf_size - last_desc->data_offset - last_desc->data_size;
}
/**
* @brief get the entire packet length
- *
+ *
* @param adf_nbuf
- *
+ *
* @return total length of packet (sum of all frag lengths)
- */
+ */
static inline a_uint32_t
__adf_nbuf_len(__adf_nbuf_t buf)
{
- return buf->buf_length;
+ return buf->buf_length;
}
/**
* @brief put data in the head
- *
+ *
* @param buf
* @param len (how much data to put)
- *
+ *
* @return new data pointer ,NULL if the len is more than the
* space available in the head frag.
*/
-static inline a_uint8_t *
+static inline a_uint8_t *
__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t len)
{
- a_uint8_t *ptr = NULL;
+ a_uint8_t *ptr = NULL;
VDESC *desc = buf->desc_list;
-
+
desc->data_offset -= len;
desc->data_size += len;
buf->buf_length += len;
}
/**
- *
+ *
* @brief add data in the end of tail
- *
+ *
* @param buf
* @param len (how much data to put)
- *
+ *
* @return previous tail (data+len),NULL if the len is more than
* space available
*/
{
a_uint8_t *tail = NULL;
VDESC *last_desc = __adf_nbuf_last(buf);
-
+
tail = last_desc->buf_addr + last_desc->data_offset + last_desc->data_size;
last_desc->data_size += len;
buf->buf_length += len;
-
+
return tail;
}
/**
* @brief strip data from head
- *
+ *
* @param adf_nbuf
* @param len (how much data to rip)
- *
+ *
* @return new data pointer
*/
-static inline a_uint8_t *
+static inline a_uint8_t *
__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t len)
{
a_uint8_t *ptr = NULL;
VDESC *desc = buf->desc_list;
-
+
desc->data_offset += len;
desc->data_size -= len;
buf->buf_length -= len;
ptr = desc->buf_addr + desc->data_offset;
-
+
return ptr;
}
/**
* @brief retrieve the priv space pointer from nbuf
- *
+ *
* @param buf (nbuf to attach the priv space)
- *
+ *
* @return uint8_t* ( pointer to the data )
*/
static inline a_uint8_t *
/**
* @brief returns the first guy in the Q
* @param qhead
- *
+ *
* @return (NULL if the Q is empty)
*/
-static inline __adf_nbuf_t
+static inline __adf_nbuf_t
__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead)
{
return qhead->head;
}
/**
* @brief return the next packet from packet chain
- *
+ *
* @param buf (packet)
- *
+ *
* @return (NULL if no packets are there)
*/
-static inline __adf_nbuf_t
+static inline __adf_nbuf_t
__adf_nbuf_queue_next(__adf_nbuf_t buf)
{
return buf->next_buf;
* be set to 0 -- only a single arena is currently supported.
*/
void *(* cmnos_allocram)(void *which_arena, A_UINT32 nbytes);
-
+
void (* cmnos_allocram_debug)(void);
};
/* HIF support */
#define HIF_MODULE_INSTALL() hif_module_install(&_A_OS_INDIRECTION_TABLE->hif)
#define HIF_init(pConfig) A_INDIR(hif._init(pConfig))
-#define HIF_start() A_INDIR(hif._start())
-#define HIF_config_pipe(pipe, desc_list) A_INDIR(hif._config_pipe(pipe, desc_list))
-#define HIF_send_buffer(pipe, buf) A_INDIR(hif._send_buffer(pipe, buf))
-#define HIF_return_recv_buf(pipe, buf) A_INDIR(hif._return_recv_buf(pipe, buf))
-#define HIF_isr_handler() A_INDIR(hif._isr_handler())
+#define HIF_start() A_INDIR(hif._start())
+#define HIF_config_pipe(pipe, desc_list) A_INDIR(hif._config_pipe(pipe, desc_list))
+#define HIF_send_buffer(pipe, buf) A_INDIR(hif._send_buffer(pipe, buf))
+#define HIF_return_recv_buf(pipe, buf) A_INDIR(hif._return_recv_buf(pipe, buf))
+#define HIF_isr_handler() A_INDIR(hif._isr_handler())
#define HIF_is_pipe_supported(pipe) A_INDIR(hif._is_pipe_supported(pipe))
/* VBUF APIs */
*/
typedef struct _A_athos_indirection_table {
_A_cmnos_indirection_table_t cmnos;
-
+
/* TBD: to be added */
struct hif_api hif;
struct vbuf_api vbuf;
struct vdesc_api vdesc;
struct htc_apis htc;
- //WMI_SVC_APIS wmi_svc_api;
+ //WMI_SVC_APIS wmi_svc_api;
} _A_athos_indirection_table_t;
#if 1
};
-/*
+/*
* A_INIT() handles any initialization needed by the OS abstraction,
* and it clears the application's BSS, if necessary. (Application BSS
* is not cleared if the application is linked into a single image that
{
struct _A_os_linkage_check link_check;
unsigned int *clrptr;
-
+
if (&START_BSS != _A_MAGPIE_INDIRECTION_TABLE->cmnos.start_bss) {
/* Clear BSS */
for (clrptr = &START_BSS; clrptr < &END_BSS; clrptr++) {
*/
/*
* @File: buf_pool_api.h
- *
+ *
* @Abstract: BUF Pool api
- *
+ *
* @Notes:
*/
/* endpoint defines */
typedef enum
{
- POOL_ID_HTC_CONTROL = 0,
- POOL_ID_WMI_SVC_CMD_REPLY = 1,
+ POOL_ID_HTC_CONTROL = 0,
+ POOL_ID_WMI_SVC_CMD_REPLY = 1,
POOL_ID_WMI_SVC_EVENT = 2,
POOL_ID_WLAN_RX_BUF = 3,
- POOL_ID_MAX = 10
+ POOL_ID_MAX = 10
} BUF_POOL_ID;
typedef void* pool_handle_t;
/* hardware API table structure (API descriptions below) */
struct buf_pool_api {
pool_handle_t (*_init)(adf_os_handle_t handle);
-
+
void (*_shutdown)(pool_handle_t handle);
-
+
void (*_create_pool)(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize);
-
+
adf_nbuf_t (*_alloc_buf)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve);
-
+
adf_nbuf_t (*_alloc_buf_align)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align);
-
+
void (*_free_buf)(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf);
-
+
/* room to expand this table by another table */
- void *pReserved;
+ void *pReserved;
};
extern void buf_pool_module_install(struct buf_pool_api *apis);
A_UINT32 (* _refclk_speed_get)(void);
A_UINT32 (* _milliseconds)(void);
void (* _sysclk_change)(void);
-
+
void (* _clock_tick)(void);
};
A_CMN(timer._timer_run())
#define A_GMAC_BOOT_INIT() \
- A_CMN(gmac.gmac_boot_init())
+ A_CMN(gmac.gmac_boot_init())
#if SYSTEM_MODULE_ALLOCRAM
/* Default size of ALLOCRAM area */
*/
/*
* @File: dma_engine_api.h
- *
+ *
* @Abstract: DMA Engine api
- *
+ *
* @Notes:
*/
{
struct zsDmaDesc* head;
struct zsDmaDesc* terminator;
-
+
/* Below are fields specific to TX */
VBUF *xmited_buf_head;
- VBUF *xmited_buf_tail;
+ VBUF *xmited_buf_tail;
};
/* hardware API table structure (API descriptions below) */
-struct dma_engine_api
+struct dma_engine_api
{
void (*_init)();
void (*_init_rx_queue)(struct zsDmaQueue *q);
-
+
void (*_init_tx_queue)(struct zsTxDmaQueue *q);
-
+
void (*_config_rx_queue)(struct zsDmaQueue *q, int num_desc, int buf_size);
-
+
void (*_xmit_buf)(struct zsTxDmaQueue *q, VBUF *buf);
-
+
void (*_flush_xmit)(struct zsDmaQueue *q);
-
+
VBUF* (*_reap_recv_buf)(struct zsDmaQueue *q);
-
+
void (*_return_recv_buf)(struct zsDmaQueue *q, VBUF *buf);
-
+
VBUF* (*_reap_xmited_buf)(struct zsTxDmaQueue *q);
-
+
void (*_swap_data)(struct zsDmaDesc* desc);
-
+
int (*_has_compl_packets)(struct zsDmaQueue *q);
-
+
void (*_desc_dump)(struct zsDmaQueue *q);
-
+
/* The functions below are for patchable */
struct zsDmaDesc* (*_get_packet)(struct zsDmaQueue* q);
void (*_reclaim_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc);
void (*_put_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc);
-
+
/* room to expand this table by another table */
void *pReserved;
};
A_UINT16 (*rx_init)(dma_engine_t eng_no, dma_iftype_t if_type);
void (*rx_config)(dma_engine_t eng_no, a_uint16_t num_desc,
a_uint16_t gran);
- void (*rx_start)(dma_engine_t eng_no);
+ void (*rx_start)(dma_engine_t eng_no);
A_UINT32 (*intr_status)(dma_iftype_t if_type);
A_UINT16 (*hard_xmit)(dma_engine_t eng_no, VBUF *buf);
void (*flush_xmit)(dma_engine_t eng_no);
/**
* @brief Install the DMA lib api's this for ROM patching
* support
- *
+ *
* @param apis
*/
void dma_lib_module_install(struct dma_lib_api *apis);
typedef enum {
- RET_SUCCESS = 0,
+ RET_SUCCESS = 0,
RET_NOT_INIT,
RET_NOT_EXIST,
RET_EEP_CORRUPT,
RET_EEP_OVERFLOW,
-
- // add return code from here
+
+ // add return code from here
RET_UNKNOWN
}T_EEP_RET;
*/
/*
* @File: HIF_api.h
- *
+ *
* @Abstract: Host Interface api
- *
+ *
* @Notes:
*/
/* hardware API table structure (API descriptions below) */
struct hif_api {
hif_handle_t (*_init)(HIF_CONFIG *pConfig);
-
+
void (* _shutdown)(hif_handle_t);
-
+
void (*_register_callback)(hif_handle_t, HIF_CALLBACK *);
-
+
int (*_get_total_credit_count)(hif_handle_t);
-
+
void (*_start)(hif_handle_t);
void (*_config_pipe)(hif_handle_t handle, int pipe, int creditCount);
-
+
int (*_send_buffer)(hif_handle_t handle, int pipe, adf_nbuf_t buf);
- void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf);
+ void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf);
//void (*_set_recv_bufsz)(int pipe, int bufsz);
//void (*_pause_recv)(int pipe);
//void (*_resume_recv)(int pipe);
int (*_is_pipe_supported)(hif_handle_t handle, int pipe);
-
+
int (*_get_max_msg_len)(hif_handle_t handle, int pipe);
-
+
int (*_get_reserved_headroom)(hif_handle_t handle);
-
+
void (*_isr_handler)(hif_handle_t handle);
-
+
void (*_get_default_pipe)(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink);
-
+
/* room to expand this table by another table */
void *pReserved;
};
#define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/
#define ETH_P_ATH 0x88bd
-
+
typedef enum hif_gmac_pipe{
HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/
HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/
MAC_CFG2_PREAMBLE = (7 << 12),/*Default Preamble Length*/
};
enum __gmac_reg_mii_cfg{
- MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/
+ MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/
};
#define MII_ADDR_RESET_ENABLE_AUTONEG (1 << 12)
#define MII_ADDR_RESET_ENABLE_LOOPBACK (1<<14)
#define MII_ADDR_RESET_SOFT_RESET (1<<15)
-/* flags for autonegotiaion register MII_ADDR_AUTONEG_ADV,
+/* flags for autonegotiaion register MII_ADDR_AUTONEG_ADV,
All writes to this register should be followed by a soft
reset on the phy
The list is not exhaustive, only required fields added
FIFO_CFG4_RX_ALL = 0x3ffff,/*receive all frames*/
};
enum __gmac_reg_if_ctrl{
- IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/
+ IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/
};
}__attribute__((packed));
/**
* @brief this is will be in big endian format
- */
+ */
struct __athhdr{
#ifdef LITTLE_ENDIAN
A_UINT8 proto:6,
res:2;
-#else
+#else
A_UINT8 res:2,
proto:6;
-#endif
+#endif
A_UINT8 res_lo;
A_UINT16 res_hi;
}__attribute__((packed));
#define PCI_MAX_DATA_PKT_LEN 1664
#define PCI_MAX_CMD_PKT_LEN 512
-#define PCI_MAX_BOOT_DESC 2
-
+#define PCI_MAX_BOOT_DESC 2
+
typedef enum hif_pci_pipe_rx{
HIF_PCI_PIPE_RX0, /*Normal Priority RX*/
HIF_PCI_PIPE_RX1,
hif_handle_t (*pci_init)(HIF_CONFIG *pConfig);
void (*pci_reset)(void);
void (*pci_enable)(void);
- void (*pci_reap_xmitted)(__pci_softc_t *sc,
+ void (*pci_reap_xmitted)(__pci_softc_t *sc,
dma_engine_t eng_no);
void (*pci_reap_recv)(__pci_softc_t *sc, dma_engine_t eng_no);
A_UINT8 (*pci_get_pipe)(dma_engine_t eng);
/* the mailbox hardware layer context */
typedef struct _HIF_USB_CONTEXT {
- HIF_CALLBACK hifCb;
+ HIF_CALLBACK hifCb;
struct zsDmaQueue dnQ;
struct zsTxDmaQueue upQ;
#if SYSTEM_MODULE_HP_EP5
//struct VBUF_QUEUE upVbufQ;
VBUF *cmdQueue;
struct VBUF_QUEUE eventBufQ;
-
+
// Left a door for extension the structure
- void *pReserved;
+ void *pReserved;
} HIF_USB_CONTEXT;
void hif_usb_module_install(struct hif_api *apis);
-
+
#endif
-/*\r
- * Copyright (c) 2013 Qualcomm Atheros, Inc.\r
- *\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted (subject to the limitations in the\r
- * disclaimer below) provided that the following conditions are met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- *\r
- * * Neither the name of Qualcomm Atheros nor the names of its\r
- * contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE\r
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT\r
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\r
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\r
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE\r
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN\r
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-#ifndef __HTC_API_H__\r
-#define __HTC_API_H__\r
-\r
-#include <osapi.h>\r
-#include <htc.h>\r
-//#include <htc_buf.h>\r
-//#include <htc_services.h>\r
-#include <adf_nbuf.h>\r
-#include <buf_pool_api.h>\r
-\r
-#define HTC_HDR_SZ HTC_HDR_LENGTH\r
-#define HTC_BUFSZ_MAX_SEND 2048\r
-\r
-typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx);\r
-typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx);\r
- \r
-/* HTC service structure :\r
- * the caller is required to allocate storage for the service structure and register the\r
- * structure using HTC_RegisterService() The service must set the following fields:\r
- * ProcessRecvMsg\r
- * ProcessSendBufferComplete\r
- * ProcessConnect\r
- * ServiceID\r
- * MaxSvcMsgSize (for message validation)\r
- * */\r
-typedef struct _HTC_SERVICE {\r
- struct _HTC_SERVICE *pNext;\r
- /* Callback for processing receive messages. HTC calls this callback whenever a \r
- * message arrives on the endpoint assigned to this service.\r
- * HTC_BUFFER is a chain of buffers containing a full application message.\r
- * HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */\r
- //void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); \r
- void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); \r
- /* callback to process completed send buffers */\r
- //void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); \r
- void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); \r
- /* optional callback when a connection request occurs.\r
- * The EndpointID is the assigned endpoint, the callback returns a connect \r
- * response status code to allow or disallow the connection.\r
- * pDataIn points to the optional meta data supplied in the connection request\r
- * pDataOut points to a buffer to send back meta data \r
- * If no callback is supplied, HTC assumes the connect is allowed */\r
- A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService,\r
- HTC_ENDPOINT_ID EndpointID, \r
- A_UINT8 *pDataIn, \r
- int LengthIn,\r
- A_UINT8 *pDataOut,\r
- int *pLengthOut); \r
- A_UINT16 ServiceID; /* service ID to match connection requests */\r
- A_UINT16 ServiceFlags; /* service flags */\r
- A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */\r
- A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer\r
- data. This should be set to the smallest HTC buffer that can be sent \r
- through the service. The service can disable trailer data insertion\r
- by setting this value to 0. */\r
- void *ServiceCtx;\r
-} HTC_SERVICE;\r
-\r
-#define HTC_SERVICE_FLAGS_CONNECTED (1 << 0) /* service has at least 1 connection */\r
-\r
-#define IS_SERVICE_CONNECTED(s) ((s)->ServiceFlags & HTC_SERVICE_FLAGS_CONNECTED)\r
-\r
- /* configuration settings for the WMI service */\r
-typedef struct _HTC_CONFIG {\r
- int CreditSize; /* */\r
- int CreditNumber;\r
- //int ControlDownLinkPipeID;\r
- //int ControlUpLinkPipeID;\r
- adf_os_handle_t OSHandle;\r
- hif_handle_t HIFHandle;\r
- pool_handle_t PoolHandle;\r
-} HTC_CONFIG;\r
-\r
-typedef struct _HTC_BUF_CONTEXT {\r
- A_UINT8 end_point;\r
- A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */ \r
-} HTC_BUF_CONTEXT;\r
-\r
-typedef void* htc_handle_t;\r
-\r
-/*\r
- * setup complete function, supplied by HTC caller at HTC_init time.\r
- * HTC calls this function after the host has indicated that the service connection\r
- * phase is complete.\r
- * \r
- */\r
-typedef void (* HTC_SETUP_COMPLETE_CB)(void);\r
-\r
-struct htc_apis {\r
- htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig); \r
- void (* _HTC_Shutdown)(htc_handle_t);\r
- void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *);\r
- void (* _HTC_Ready)(htc_handle_t);\r
- void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t);\r
- void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t);\r
- void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); \r
- int (* _HTC_GetReservedHeadroom)(htc_handle_t handle);\r
- \r
- //void (* _HTC_PauseRecv)(HTC_ENDPOINT_ID EndpointID);\r
- //void (* _HTC_ResumeRecv)(HTC_ENDPOINT_ID EndpointID);\r
- //void (* _HTC_AddBufferResources)(int buffers);\r
- \r
- /* These APIs below are for patch purpose only */\r
- void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context);\r
- void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context);\r
- void (*_HTC_ControlSvcProcessMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *arg);\r
- void (*_HTC_ControlSvcProcessSendComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg);\r
- \r
- void *pReserved; /* for expansion if need be */\r
-};\r
-\r
-extern void htc_module_install(struct htc_apis *pAPIs);\r
-\r
-#endif /* _HTC_API_H__ */\r
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __HTC_API_H__
+#define __HTC_API_H__
+
+#include <osapi.h>
+#include <htc.h>
+//#include <htc_buf.h>
+//#include <htc_services.h>
+#include <adf_nbuf.h>
+#include <buf_pool_api.h>
+
+#define HTC_HDR_SZ HTC_HDR_LENGTH
+#define HTC_BUFSZ_MAX_SEND 2048
+
+typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx);
+typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx);
+
+/* HTC service structure :
+ * the caller is required to allocate storage for the service structure and register the
+ * structure using HTC_RegisterService() The service must set the following fields:
+ * ProcessRecvMsg
+ * ProcessSendBufferComplete
+ * ProcessConnect
+ * ServiceID
+ * MaxSvcMsgSize (for message validation)
+ * */
+typedef struct _HTC_SERVICE {
+ struct _HTC_SERVICE *pNext;
+ /* Callback for processing receive messages. HTC calls this callback whenever a
+ * message arrives on the endpoint assigned to this service.
+ * HTC_BUFFER is a chain of buffers containing a full application message.
+ * HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */
+ //void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *);
+ void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx);
+ /* callback to process completed send buffers */
+ //void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *);
+ void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx);
+ /* optional callback when a connection request occurs.
+ * The EndpointID is the assigned endpoint, the callback returns a connect
+ * response status code to allow or disallow the connection.
+ * pDataIn points to the optional meta data supplied in the connection request
+ * pDataOut points to a buffer to send back meta data
+ * If no callback is supplied, HTC assumes the connect is allowed */
+ A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService,
+ HTC_ENDPOINT_ID EndpointID,
+ A_UINT8 *pDataIn,
+ int LengthIn,
+ A_UINT8 *pDataOut,
+ int *pLengthOut);
+ A_UINT16 ServiceID; /* service ID to match connection requests */
+ A_UINT16 ServiceFlags; /* service flags */
+ A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */
+ A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer
+ data. This should be set to the smallest HTC buffer that can be sent
+ through the service. The service can disable trailer data insertion
+ by setting this value to 0. */
+ void *ServiceCtx;
+} HTC_SERVICE;
+
+#define HTC_SERVICE_FLAGS_CONNECTED (1 << 0) /* service has at least 1 connection */
+
+#define IS_SERVICE_CONNECTED(s) ((s)->ServiceFlags & HTC_SERVICE_FLAGS_CONNECTED)
+
+ /* configuration settings for the WMI service */
+typedef struct _HTC_CONFIG {
+ int CreditSize; /* */
+ int CreditNumber;
+ //int ControlDownLinkPipeID;
+ //int ControlUpLinkPipeID;
+ adf_os_handle_t OSHandle;
+ hif_handle_t HIFHandle;
+ pool_handle_t PoolHandle;
+} HTC_CONFIG;
+
+typedef struct _HTC_BUF_CONTEXT {
+ A_UINT8 end_point;
+ A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */
+} HTC_BUF_CONTEXT;
+
+typedef void* htc_handle_t;
+
+/*
+ * setup complete function, supplied by HTC caller at HTC_init time.
+ * HTC calls this function after the host has indicated that the service connection
+ * phase is complete.
+ *
+ */
+typedef void (* HTC_SETUP_COMPLETE_CB)(void);
+
+struct htc_apis {
+ htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig);
+ void (* _HTC_Shutdown)(htc_handle_t);
+ void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *);
+ void (* _HTC_Ready)(htc_handle_t);
+ void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t);
+ void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t);
+ void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t);
+ int (* _HTC_GetReservedHeadroom)(htc_handle_t handle);
+
+ //void (* _HTC_PauseRecv)(HTC_ENDPOINT_ID EndpointID);
+ //void (* _HTC_ResumeRecv)(HTC_ENDPOINT_ID EndpointID);
+ //void (* _HTC_AddBufferResources)(int buffers);
+
+ /* These APIs below are for patch purpose only */
+ void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context);
+ void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context);
+ void (*_HTC_ControlSvcProcessMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *arg);
+ void (*_HTC_ControlSvcProcessSendComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg);
+
+ void *pReserved; /* for expansion if need be */
+};
+
+extern void htc_module_install(struct htc_apis *pAPIs);
+
+#endif /* _HTC_API_H__ */
A_INTR_USB_DMA,
A_INTR_ERROR,
/* add intr above here */
- A_INTR_NUM
+ A_INTR_NUM
}A_INUM_INTR_T;
//////////////////////////////////////////////////////////////////
* An Interrupt Service Routine, which must be called
* directly in interrupt context (not delayed), and which
* must be very small and may not have access to all OS
- * functions. These are for use only when interrupt
+ * functions. These are for use only when interrupt
* latency is critical; otherwise, an A_handler_t ("dsr")
* is preferable.
*/
void (* _intr_mask_inum)(uint32_t inum);
void (* _intr_unmask_inum)(uint32_t inum);
void (* _intr_attach_isr)(uint32_t inum, A_isr_t isr, void *arg);
-/*
+/*
BOOLEAN (*_intr_dsrs_pending)(void);
void (* _intr_handle_pending_dsrs)(void);
uint32_t (* _intr_nmi)(void *);
-/*\r
- * Copyright (c) 2013 Qualcomm Atheros, Inc.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted (subject to the limitations in the\r
- * disclaimer below) provided that the following conditions are met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- *\r
- * * Neither the name of Qualcomm Atheros nor the names of its\r
- * contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE\r
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT\r
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\r
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\r
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE\r
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN\r
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-/*************************************************************************/\r
-/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */\r
-/* */\r
-/* Module Name : reg_defs.h */\r
-/* */\r
-/* Abstract */\r
-/* This file contains the register addr and marco definition. */\r
-/* */\r
-/* NOTES */\r
-/* None */\r
-/* */\r
-/*************************************************************************/\r
-#ifndef _REG_DEFS_H_\r
-#define _REG_DEFS_H_\r
-\r
-#include "dt_defs.h"\r
-\r
-#define BIT_SET(bit) (1<<bit)\r
-#define BIT_CLR(bit) (0<<bit)\r
-\r
-/***** REGISTER BASE ADDRESS DEFINITION *****/\r
-#define RESET_VECTOR_ADDRESS 0x8e0000\r
-/********************************************/\r
-\r
-/***** REGISTER BASE ADDRESS DEFINITION *****/\r
-#define USB_CTRL_BASE_ADDRESS 0x00010000\r
-//#define PCIE_BASE_ADDRESS 0x00020000\r
-#define RST_BASE_ADDRESS 0x00050000\r
-#define UART_BASE_ADDRESS 0x00051000\r
-#define GPIO_BASE_ADDRESS 0x00052000\r
-#define HOST_DMA_BASE_ADDRESS 0x00053000\r
-#define GMAC_BASE_ADDRESS 0x00054000\r
-#define USB_DMA_BASE_ADDRESS 0x00055000\r
-#define CPU_PLL_BASE_ADDRESS 0x00056000\r
-#define SPI_REG_BASE_ADDRESS 0x0005B000\r
-#define EEPROM_BASE_ADDRESS 0x1f000000\r
-#define WLAN_BASE_ADDRESS 0x10ff0000\r
-/*******************************************************************************/\r
-/* Reset Register*/\r
-#define MAGPEI_REG_RST_BASE_ADDR RST_BASE_ADDRESS\r
-\r
-#define REG_GENERAL_TIMER_OFFSET 0x0\r
-#define REG_GENERAL_TIMER_RELOAD_OFFSET 0x4\r
-#define REG_WATCHDOG_TIMER_CONTROL_OFFSET 0x8\r
-#define REG_WATCHDOG_TIMER_OFFSET 0xC\r
-#define REG_RESET_OFFSET 0x10\r
-#define REG_BOOTSTRAP 0x14\r
-#define REG_AHB_ARB 0x18\r
-#define REG_REVISION_ID 0x90\r
-\r
-\r
-#define MAGPEI_REG_RST_GENERAL_TIMER_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_OFFSET)\r
-#define MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_RELOAD_OFFSET)\r
-#define MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_CONTROL_OFFSET)\r
-#define MAGPIE_REG_RST_WDT_TIMER_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_OFFSET)\r
-#define MAGPIE_REG_RST_RESET_ADDR (RST_BASE_ADDRESS+REG_RESET_OFFSET)\r
-#define MAGPIE_REG_RST_BOOTSTRAP_ADDR (RST_BASE_ADDRESS+REG_BOOTSTRAP)\r
-#define MAGPIE_REG_AHB_ARB_ADDR (RST_BASE_ADDRESS+REG_AHB_ARB)\r
-#define MAGPIE_REG_REVISION_ID_ADDR (RST_BASE_ADDRESS+REG_REVISION_ID)\r
-\r
-#define MAGPEI_REG_RST_GENERAL_TIMER (*((volatile u32_t*)(MAGPEI_REG_RST_GENERAL_TIMER_ADDR)))\r
-#define MAGPIE_REG_RST_GENERAL_TIMER_RLD (*((volatile u32_t*)(MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR)))\r
-#define MAGPIE_REG_RST_WDT_TIMER_CTRL (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR)))\r
-#define MAGPIE_REG_RST_WDT_TIMER (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_ADDR)))\r
-#define MAGPIE_REG_RST_RESET (*((volatile u32_t*)(MAGPIE_REG_RST_RESET_ADDR)))\r
-#define MAGPIE_REG_RST_BOOTSTRAP (*((volatile u32_t*)(MAGPIE_REG_RST_BOOTSTRAP_ADDR)))\r
-#define MAGPIE_REG_AHB_ARB (*((volatile u32_t*)(MAGPIE_REG_AHB_ARB_ADDR)))\r
-#define MAGPIE_REG_REVISION_ID (*((volatile u32_t*)(MAGPIE_REG_REVISION_ID_ADDR)))\r
-\r
-\r
-/*******************************************************************************/\r
-/* USB DMA Register*/\r
-\r
-#define MAGPIE_REG_USB_INTERRUPT_ADDR USB_DMA_BASE_ADDRESS\r
-#define MAGPIE_REG_USB_INTERRUPT_MASK_ADDR (USB_DMA_BASE_ADDRESS + 0x4)\r
-\r
-#define MAGPIE_REG_USB_RX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x800)\r
-#define MAGPIE_REG_USB_RX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x804)\r
-#define MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x808)\r
-#define MAGPIE_REG_USB_RX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x814)\r
-#define MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x818)\r
-#define MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x81C)\r
-\r
-#define MAGPIE_REG_USB_RX1_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x900)\r
-#define MAGPIE_REG_USB_RX1_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x904)\r
-#define MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x908)\r
-#define MAGPIE_REG_USB_RX1_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x914)\r
-#define MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x918)\r
-#define MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x91C)\r
-\r
-#define MAGPIE_REG_USB_RX2_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa00)\r
-#define MAGPIE_REG_USB_RX2_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa04)\r
-#define MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xa08)\r
-#define MAGPIE_REG_USB_RX2_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xa14)\r
-#define MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xa18)\r
-#define MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xa1C)\r
-\r
-#define MAGPIE_REG_USB_TX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC00)\r
-#define MAGPIE_REG_USB_TX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC04)\r
-#define MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xC08)\r
-#define MAGPIE_REG_USB_TX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xC10)\r
-#define MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xC14)\r
-#define MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xC18)\r
-\r
-#define MAGPIE_REG_USB_INTERRUPT_TX0_END (1<<24) //0x1000000\r
-#define MAGPIE_REG_USB_INTERRUPT_TX0_COMPL (1<<16) //0x10000\r
-#define MAGPIE_REG_USB_INTERRUPT_RX2_END (1<<10) //0x00400\r
-#define MAGPIE_REG_USB_INTERRUPT_RX1_END (1<<9) //0x00200\r
-#define MAGPIE_REG_USB_INTERRUPT_RX0_END (1<<8) //0x0100\r
-#define MAGPIE_REG_USB_INTERRUPT_RX2_COMPL (1<<2) //0x00004\r
-\r
-#define MAGPIE_REG_USB_INTERRUPT_RX1_COMPL (1<<1) //0x00002\r
-#define MAGPIE_REG_USB_INTERRUPT_RX0_COMPL (1<<0) //0x00001\r
-\r
-\r
-#define MAGPIE_REG_USB_INTERRUPT (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_ADDR)))\r
-#define MAGPIE_REG_USB_INTERRUPT_MASK (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_MASK_ADDR)))\r
-\r
-#define MAGPIE_REG_USB_RX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DESC_START_ADDR)))\r
-#define MAGPIE_REG_USB_RX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DMA_START_ADDR)))\r
-#define MAGPIE_REG_USB_RX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR)))\r
-#define MAGPIE_REG_USB_RX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_STATE_ADDR)))\r
-#define MAGPIE_REG_USB_RX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR)))\r
-#define MAGPIE_REG_USB_RX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR)))\r
-\r
-\r
-#define MAGPIE_REG_USB_RX1_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DESC_START_ADDR)))\r
-#define MAGPIE_REG_USB_RX1_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DMA_START_ADDR)))\r
-#define MAGPIE_REG_USB_RX1_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR)))\r
-#define MAGPIE_REG_USB_RX1_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_STATE_ADDR)))\r
-#define MAGPIE_REG_USB_RX1_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR)))\r
-#define MAGPIE_REG_USB_RX1_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR)))\r
-\r
-#define MAGPIE_REG_USB_RX2_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DESC_START_ADDR)))\r
-#define MAGPIE_REG_USB_RX2_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DMA_START_ADDR)))\r
-#define MAGPIE_REG_USB_RX2_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR)))\r
-#define MAGPIE_REG_USB_RX2_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_STATE_ADDR)))\r
-#define MAGPIE_REG_USB_RX2_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR)))\r
-#define MAGPIE_REG_USB_RX2_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR)))\r
-\r
-\r
-#define MAGPIE_REG_USB_TX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DESC_START_ADDR)))\r
-#define MAGPIE_REG_USB_TX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DMA_START_ADDR)))\r
-#define MAGPIE_REG_USB_TX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR)))\r
-#define MAGPIE_REG_USB_TX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_STATE_ADDR)))\r
-#define MAGPIE_REG_USB_TX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR)))\r
-#define MAGPIE_REG_USB_TX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR)))\r
-\r
-\r
-\r
-/*******************************************************************************/\r
-/* CPU PLL Register*/\r
-\r
-#define REG_CPU_PLL_OFFSET 0x0\r
-#define REG_CPU_PLL_BYPASS_OFFSET 0x4\r
-#define REG_USB_DIVIDE_OFFSET 0x8\r
-#define REG_ETH_PLL_OFFSET 0xC\r
-#define REG_ETH_PLL_BYPASS_OFFSET 0x10\r
-#define REG_ETH_TXRX_DIVIDE_OFFSET 0x14\r
-#define REG_ETH_XTAL_DIVIDE_OFFSET 0x18\r
-#define REG_PCIE_PLL_CONFIG_OFFSET 0x1C\r
-#define REG_PCIE_DITHER_DIV_MAX_OFFSET 0x20\r
-#define REG_PCIE_PLL_DITHER_DIV_MIN_OFFSET 0x24\r
-#define REG_PCIE_PLL_DITHER_STEP_OFFSET 0x28\r
-#define REG_CURRENT_PCIE_PLL_DITHER_OFFSET 0x2c\r
-#define REG_USB_SUSPEND_ENABLE_OFFSET 0x30\r
-\r
-\r
-#define MAGPIE_REG_CPU_PLL_ADDR (CPU_PLL_BASE_ADDRESS + REG_CPU_PLL_OFFSET)\r
-#define MAGPIE_REG_CPU_PLL_BYPASS_ADDR (CPU_PLL_BASE_ADDRESS + REG_CPU_PLL_BYPASS_OFFSET)\r
-#define MAGPIE_REG_USB_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_USB_DIVIDE_OFFSET)\r
-#define MAGPIE_REG_ETH_PLL_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_PLL_OFFSET)\r
-#define MAGPIE_REG_ETH_PLL_BYPASS_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_PLL_BYPASS_OFFSET)\r
-#define MAGPIE_REG_ETH_TXRX_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_TXRX_DIVIDE_OFFSET)\r
-#define MAGPIE_REG_ETH_XTAL_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_XTAL_DIVIDE_OFFSET)\r
-#define MAGPIE_REG_PCIE_PLL_CONFIG_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_CONFIG_OFFSET)\r
-#define MAGPIE_REG_PCIE_DITHER_DIV_MAX_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_DITHER_DIV_MAX_OFFSET)\r
-#define MAGPIE_REG_PCIE_PLL_DITHER_DIV_MIN_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_DITHER_DIV_MIN_OFFSET)\r
-#define MAGPIE_REG_PCIE_PLL_DITHER_STEP_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_DITHER_STEP_OFFSET)\r
-#define MAGPIE_REG_CURRENT_PCIE_PLL_DITHER_ADDR (CPU_PLL_BASE_ADDRESS + REG_CURRENT_PCIE_PLL_DITHER_OFFSET)\r
-#define MAGPIE_REG_SUSPEND_ENABLE_ADDR (CPU_PLL_BASE_ADDRESS + REG_USB_SUSPEND_ENABLE_OFFSET)\r
-\r
-\r
-/*******************************************************************************/\r
-/* GPIO Register*/\r
-\r
-#define REG_GPIO_OE 0x0\r
-#define REG_GPIO_IN 0x4\r
-#define REG_GPIO_OUT 0x8\r
-#define REG_GPIO_SET 0xC\r
-#define REG_GPIO_CLEAR 0x10\r
-#define REG_GPIO_INT 0x14\r
-#define REG_GPIO_INT_TYPE 0x18\r
-#define REG_GPIO_INT_POLARITY 0x1C\r
-#define REG_GPIO_PENDING 0x20\r
-#define REG_GPIO_INT_MASK 0x24\r
-#define REG_GPIO_FUNCTION 0x28\r
-\r
-\r
-#define MAGPIE_REG_GPIO_OE (GPIO_BASE_ADDRESS + REG_GPIO_OE)\r
-#define MAGPIE_REG_GPIO_IN (GPIO_BASE_ADDRESS + REG_GPIO_IN)\r
-#define MAGPIE_REG_GPIO_OUT (GPIO_BASE_ADDRESS + REG_GPIO_OUT)\r
-#define MAGPIE_REG_GPIO_SET (GPIO_BASE_ADDRESS + REG_GPIO_SET)\r
-#define MAGPIE_REG_GPIO_CLEAR (GPIO_BASE_ADDRESS + REG_GPIO_CLEAR)\r
-#define MAGPIE_REG_GPIO_INT (GPIO_BASE_ADDRESS + REG_GPIO_INT)\r
-#define MAGPIE_REG_GPIO_INT_TYPE (GPIO_BASE_ADDRESS + REG_GPIO_INT_TYPE)\r
-#define MAGPIE_REG_GPIO_INT_POLARITY (GPIO_BASE_ADDRESS + REG_GPIO_INT_POLARITY)\r
-#define MAGPIE_REG_GPIO_PENDING (GPIO_BASE_ADDRESS + REG_GPIO_PENDING)\r
-#define MAGPIE_REG_GPIO_INT_MASK (GPIO_BASE_ADDRESS + REG_GPIO_INT_MASK)\r
-#define MAGPIE_REG_GPIO_FUNCTION (GPIO_BASE_ADDRESS + REG_GPIO_FUNCTION)\r
-\r
-\r
-/*******************************************************************************/\r
-/* SPI Flash Register*/\r
-#define MAGPEI_REG_SPI_BASE_ADDR SPI_REG_BASE_ADDRESS\r
-\r
-#define REG_SPI_CS_OFFSET 0x0\r
-#define REG_SPI_AO_OFFSET 0x4\r
-#define REG_SPI_D_OFFSET 0x8\r
-#define REG_SPI_CLKDIV_OFFSET 0x1C\r
-\r
-#define MAGPIE_REG_SPI_CS_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_CS_OFFSET)\r
-#define MAGPIE_REG_SPI_AO_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_AO_OFFSET)\r
-#define MAGPIE_REG_SPI_D_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_D_OFFSET)\r
-#define MAGPIE_REG_SPI_CLKDIV_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_CLKDIV_OFFSET)\r
-\r
-#endif\r
-\r
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*************************************************************************/
+/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
+/* */
+/* Module Name : reg_defs.h */
+/* */
+/* Abstract */
+/* This file contains the register addr and marco definition. */
+/* */
+/* NOTES */
+/* None */
+/* */
+/*************************************************************************/
+#ifndef _REG_DEFS_H_
+#define _REG_DEFS_H_
+
+#include "dt_defs.h"
+
+#define BIT_SET(bit) (1<<bit)
+#define BIT_CLR(bit) (0<<bit)
+
+/***** REGISTER BASE ADDRESS DEFINITION *****/
+#define RESET_VECTOR_ADDRESS 0x8e0000
+/********************************************/
+
+/***** REGISTER BASE ADDRESS DEFINITION *****/
+#define USB_CTRL_BASE_ADDRESS 0x00010000
+//#define PCIE_BASE_ADDRESS 0x00020000
+#define RST_BASE_ADDRESS 0x00050000
+#define UART_BASE_ADDRESS 0x00051000
+#define GPIO_BASE_ADDRESS 0x00052000
+#define HOST_DMA_BASE_ADDRESS 0x00053000
+#define GMAC_BASE_ADDRESS 0x00054000
+#define USB_DMA_BASE_ADDRESS 0x00055000
+#define CPU_PLL_BASE_ADDRESS 0x00056000
+#define SPI_REG_BASE_ADDRESS 0x0005B000
+#define EEPROM_BASE_ADDRESS 0x1f000000
+#define WLAN_BASE_ADDRESS 0x10ff0000
+/*******************************************************************************/
+/* Reset Register*/
+#define MAGPEI_REG_RST_BASE_ADDR RST_BASE_ADDRESS
+
+#define REG_GENERAL_TIMER_OFFSET 0x0
+#define REG_GENERAL_TIMER_RELOAD_OFFSET 0x4
+#define REG_WATCHDOG_TIMER_CONTROL_OFFSET 0x8
+#define REG_WATCHDOG_TIMER_OFFSET 0xC
+#define REG_RESET_OFFSET 0x10
+#define REG_BOOTSTRAP 0x14
+#define REG_AHB_ARB 0x18
+#define REG_REVISION_ID 0x90
+
+
+#define MAGPEI_REG_RST_GENERAL_TIMER_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_OFFSET)
+#define MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR (RST_BASE_ADDRESS+REG_GENERAL_TIMER_RELOAD_OFFSET)
+#define MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_CONTROL_OFFSET)
+#define MAGPIE_REG_RST_WDT_TIMER_ADDR (RST_BASE_ADDRESS+REG_WATCHDOG_TIMER_OFFSET)
+#define MAGPIE_REG_RST_RESET_ADDR (RST_BASE_ADDRESS+REG_RESET_OFFSET)
+#define MAGPIE_REG_RST_BOOTSTRAP_ADDR (RST_BASE_ADDRESS+REG_BOOTSTRAP)
+#define MAGPIE_REG_AHB_ARB_ADDR (RST_BASE_ADDRESS+REG_AHB_ARB)
+#define MAGPIE_REG_REVISION_ID_ADDR (RST_BASE_ADDRESS+REG_REVISION_ID)
+
+#define MAGPEI_REG_RST_GENERAL_TIMER (*((volatile u32_t*)(MAGPEI_REG_RST_GENERAL_TIMER_ADDR)))
+#define MAGPIE_REG_RST_GENERAL_TIMER_RLD (*((volatile u32_t*)(MAGPIE_REG_RST_GENERAL_TIMER_RLD_ADDR)))
+#define MAGPIE_REG_RST_WDT_TIMER_CTRL (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR)))
+#define MAGPIE_REG_RST_WDT_TIMER (*((volatile u32_t*)(MAGPIE_REG_RST_WDT_TIMER_ADDR)))
+#define MAGPIE_REG_RST_RESET (*((volatile u32_t*)(MAGPIE_REG_RST_RESET_ADDR)))
+#define MAGPIE_REG_RST_BOOTSTRAP (*((volatile u32_t*)(MAGPIE_REG_RST_BOOTSTRAP_ADDR)))
+#define MAGPIE_REG_AHB_ARB (*((volatile u32_t*)(MAGPIE_REG_AHB_ARB_ADDR)))
+#define MAGPIE_REG_REVISION_ID (*((volatile u32_t*)(MAGPIE_REG_REVISION_ID_ADDR)))
+
+
+/*******************************************************************************/
+/* USB DMA Register*/
+
+#define MAGPIE_REG_USB_INTERRUPT_ADDR USB_DMA_BASE_ADDRESS
+#define MAGPIE_REG_USB_INTERRUPT_MASK_ADDR (USB_DMA_BASE_ADDRESS + 0x4)
+
+#define MAGPIE_REG_USB_RX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x800)
+#define MAGPIE_REG_USB_RX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x804)
+#define MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x808)
+#define MAGPIE_REG_USB_RX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x814)
+#define MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x818)
+#define MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x81C)
+
+#define MAGPIE_REG_USB_RX1_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0x900)
+#define MAGPIE_REG_USB_RX1_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0x904)
+#define MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0x908)
+#define MAGPIE_REG_USB_RX1_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0x914)
+#define MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0x918)
+#define MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0x91C)
+
+#define MAGPIE_REG_USB_RX2_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa00)
+#define MAGPIE_REG_USB_RX2_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xa04)
+#define MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xa08)
+#define MAGPIE_REG_USB_RX2_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xa14)
+#define MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xa18)
+#define MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xa1C)
+
+#define MAGPIE_REG_USB_TX0_DESC_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC00)
+#define MAGPIE_REG_USB_TX0_DMA_START_ADDR (USB_DMA_BASE_ADDRESS + 0xC04)
+#define MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR (USB_DMA_BASE_ADDRESS + 0xC08)
+#define MAGPIE_REG_USB_TX0_STATE_ADDR (USB_DMA_BASE_ADDRESS + 0xC10)
+#define MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR (USB_DMA_BASE_ADDRESS + 0xC14)
+#define MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR (USB_DMA_BASE_ADDRESS + 0xC18)
+
+#define MAGPIE_REG_USB_INTERRUPT_TX0_END (1<<24) //0x1000000
+#define MAGPIE_REG_USB_INTERRUPT_TX0_COMPL (1<<16) //0x10000
+#define MAGPIE_REG_USB_INTERRUPT_RX2_END (1<<10) //0x00400
+#define MAGPIE_REG_USB_INTERRUPT_RX1_END (1<<9) //0x00200
+#define MAGPIE_REG_USB_INTERRUPT_RX0_END (1<<8) //0x0100
+#define MAGPIE_REG_USB_INTERRUPT_RX2_COMPL (1<<2) //0x00004
+
+#define MAGPIE_REG_USB_INTERRUPT_RX1_COMPL (1<<1) //0x00002
+#define MAGPIE_REG_USB_INTERRUPT_RX0_COMPL (1<<0) //0x00001
+
+
+#define MAGPIE_REG_USB_INTERRUPT (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_ADDR)))
+#define MAGPIE_REG_USB_INTERRUPT_MASK (*((volatile u32_t*)(MAGPIE_REG_USB_INTERRUPT_MASK_ADDR)))
+
+#define MAGPIE_REG_USB_RX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DESC_START_ADDR)))
+#define MAGPIE_REG_USB_RX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_DMA_START_ADDR)))
+#define MAGPIE_REG_USB_RX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_BURST_SIZE_ADDR)))
+#define MAGPIE_REG_USB_RX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_STATE_ADDR)))
+#define MAGPIE_REG_USB_RX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR)))
+#define MAGPIE_REG_USB_RX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX0_SWAP_DATA_ADDR)))
+
+
+#define MAGPIE_REG_USB_RX1_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DESC_START_ADDR)))
+#define MAGPIE_REG_USB_RX1_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_DMA_START_ADDR)))
+#define MAGPIE_REG_USB_RX1_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_BURST_SIZE_ADDR)))
+#define MAGPIE_REG_USB_RX1_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_STATE_ADDR)))
+#define MAGPIE_REG_USB_RX1_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR)))
+#define MAGPIE_REG_USB_RX1_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX1_SWAP_DATA_ADDR)))
+
+#define MAGPIE_REG_USB_RX2_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DESC_START_ADDR)))
+#define MAGPIE_REG_USB_RX2_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_DMA_START_ADDR)))
+#define MAGPIE_REG_USB_RX2_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_BURST_SIZE_ADDR)))
+#define MAGPIE_REG_USB_RX2_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_STATE_ADDR)))
+#define MAGPIE_REG_USB_RX2_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR)))
+#define MAGPIE_REG_USB_RX2_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_RX2_SWAP_DATA_ADDR)))
+
+
+#define MAGPIE_REG_USB_TX0_DESC_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DESC_START_ADDR)))
+#define MAGPIE_REG_USB_TX0_DMA_START (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_DMA_START_ADDR)))
+#define MAGPIE_REG_USB_TX0_BURST_SIZE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_BURST_SIZE_ADDR)))
+#define MAGPIE_REG_USB_TX0_STATE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_STATE_ADDR)))
+#define MAGPIE_REG_USB_TX0_CUR_TRACE (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR)))
+#define MAGPIE_REG_USB_TX0_SWAP_DATA (*((volatile u32_t*)(MAGPIE_REG_USB_TX0_SWAP_DATA_ADDR)))
+
+
+
+/*******************************************************************************/
+/* CPU PLL Register*/
+
+#define REG_CPU_PLL_OFFSET 0x0
+#define REG_CPU_PLL_BYPASS_OFFSET 0x4
+#define REG_USB_DIVIDE_OFFSET 0x8
+#define REG_ETH_PLL_OFFSET 0xC
+#define REG_ETH_PLL_BYPASS_OFFSET 0x10
+#define REG_ETH_TXRX_DIVIDE_OFFSET 0x14
+#define REG_ETH_XTAL_DIVIDE_OFFSET 0x18
+#define REG_PCIE_PLL_CONFIG_OFFSET 0x1C
+#define REG_PCIE_DITHER_DIV_MAX_OFFSET 0x20
+#define REG_PCIE_PLL_DITHER_DIV_MIN_OFFSET 0x24
+#define REG_PCIE_PLL_DITHER_STEP_OFFSET 0x28
+#define REG_CURRENT_PCIE_PLL_DITHER_OFFSET 0x2c
+#define REG_USB_SUSPEND_ENABLE_OFFSET 0x30
+
+
+#define MAGPIE_REG_CPU_PLL_ADDR (CPU_PLL_BASE_ADDRESS + REG_CPU_PLL_OFFSET)
+#define MAGPIE_REG_CPU_PLL_BYPASS_ADDR (CPU_PLL_BASE_ADDRESS + REG_CPU_PLL_BYPASS_OFFSET)
+#define MAGPIE_REG_USB_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_USB_DIVIDE_OFFSET)
+#define MAGPIE_REG_ETH_PLL_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_PLL_OFFSET)
+#define MAGPIE_REG_ETH_PLL_BYPASS_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_PLL_BYPASS_OFFSET)
+#define MAGPIE_REG_ETH_TXRX_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_TXRX_DIVIDE_OFFSET)
+#define MAGPIE_REG_ETH_XTAL_DIVIDE_ADDR (CPU_PLL_BASE_ADDRESS + REG_ETH_XTAL_DIVIDE_OFFSET)
+#define MAGPIE_REG_PCIE_PLL_CONFIG_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_CONFIG_OFFSET)
+#define MAGPIE_REG_PCIE_DITHER_DIV_MAX_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_DITHER_DIV_MAX_OFFSET)
+#define MAGPIE_REG_PCIE_PLL_DITHER_DIV_MIN_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_DITHER_DIV_MIN_OFFSET)
+#define MAGPIE_REG_PCIE_PLL_DITHER_STEP_ADDR (CPU_PLL_BASE_ADDRESS + REG_PCIE_PLL_DITHER_STEP_OFFSET)
+#define MAGPIE_REG_CURRENT_PCIE_PLL_DITHER_ADDR (CPU_PLL_BASE_ADDRESS + REG_CURRENT_PCIE_PLL_DITHER_OFFSET)
+#define MAGPIE_REG_SUSPEND_ENABLE_ADDR (CPU_PLL_BASE_ADDRESS + REG_USB_SUSPEND_ENABLE_OFFSET)
+
+
+/*******************************************************************************/
+/* GPIO Register*/
+
+#define REG_GPIO_OE 0x0
+#define REG_GPIO_IN 0x4
+#define REG_GPIO_OUT 0x8
+#define REG_GPIO_SET 0xC
+#define REG_GPIO_CLEAR 0x10
+#define REG_GPIO_INT 0x14
+#define REG_GPIO_INT_TYPE 0x18
+#define REG_GPIO_INT_POLARITY 0x1C
+#define REG_GPIO_PENDING 0x20
+#define REG_GPIO_INT_MASK 0x24
+#define REG_GPIO_FUNCTION 0x28
+
+
+#define MAGPIE_REG_GPIO_OE (GPIO_BASE_ADDRESS + REG_GPIO_OE)
+#define MAGPIE_REG_GPIO_IN (GPIO_BASE_ADDRESS + REG_GPIO_IN)
+#define MAGPIE_REG_GPIO_OUT (GPIO_BASE_ADDRESS + REG_GPIO_OUT)
+#define MAGPIE_REG_GPIO_SET (GPIO_BASE_ADDRESS + REG_GPIO_SET)
+#define MAGPIE_REG_GPIO_CLEAR (GPIO_BASE_ADDRESS + REG_GPIO_CLEAR)
+#define MAGPIE_REG_GPIO_INT (GPIO_BASE_ADDRESS + REG_GPIO_INT)
+#define MAGPIE_REG_GPIO_INT_TYPE (GPIO_BASE_ADDRESS + REG_GPIO_INT_TYPE)
+#define MAGPIE_REG_GPIO_INT_POLARITY (GPIO_BASE_ADDRESS + REG_GPIO_INT_POLARITY)
+#define MAGPIE_REG_GPIO_PENDING (GPIO_BASE_ADDRESS + REG_GPIO_PENDING)
+#define MAGPIE_REG_GPIO_INT_MASK (GPIO_BASE_ADDRESS + REG_GPIO_INT_MASK)
+#define MAGPIE_REG_GPIO_FUNCTION (GPIO_BASE_ADDRESS + REG_GPIO_FUNCTION)
+
+
+/*******************************************************************************/
+/* SPI Flash Register*/
+#define MAGPEI_REG_SPI_BASE_ADDR SPI_REG_BASE_ADDRESS
+
+#define REG_SPI_CS_OFFSET 0x0
+#define REG_SPI_AO_OFFSET 0x4
+#define REG_SPI_D_OFFSET 0x8
+#define REG_SPI_CLKDIV_OFFSET 0x1C
+
+#define MAGPIE_REG_SPI_CS_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_CS_OFFSET)
+#define MAGPIE_REG_SPI_AO_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_AO_OFFSET)
+#define MAGPIE_REG_SPI_D_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_D_OFFSET)
+#define MAGPIE_REG_SPI_CLKDIV_ADDR (MAGPEI_REG_SPI_BASE_ADDR + REG_SPI_CLKDIV_OFFSET)
+
+#endif
+
/****************************** UART ******************************/
#define UART_INPUT_CLK SYSTEM_CLK
-#define UART_DEFAULT_BAUD 19200
+#define UART_DEFAULT_BAUD 19200
#define UART_RETRY_COUNT 10000
/****************************** USB *******************************/
#define WATCH_DOG_MAGIC_PATTERN_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x4) // 0x53fffc,magic pattern address
#define WATCH_DOG_RESET_COUNTER_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x8) // 0x53fff8,record the reset counter
#define DEBUG_SYSTEM_STATE_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0xc) // 0x53fff4,record the state of system
-#define CURRENT_PROGRAM_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x10) // 0x53fff0,reserved
+#define CURRENT_PROGRAM_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x10) // 0x53fff0,reserved
#define WATCH_DOG_MAGIC_PATTERN (*((volatile u32_t*)(WATCH_DOG_MAGIC_PATTERN_ADDR)))
#define WATCH_DOG_RESET_COUNTER (*((volatile u32_t*)(WATCH_DOG_RESET_COUNTER_ADDR)))
#define _MEM_ADDRS_H_
#define SYS_ROM_BLOCK_SIZE (32*1024)
-#if MAGPIE_FPGA_RAM_256K == 1
+#if MAGPIE_FPGA_RAM_256K == 1
#define SYS_ROM_BLOCK_NUM 2 //ram 256K version is also rom 64k version
#else
#define SYS_ROM_BLOCK_NUM 3
#endif
#define SYS_ROM_SIZE (SYS_ROM_BLOCK_SIZE*SYS_ROM_BLOCK_NUM)
-
+
#if MAGPIE_FPGA_RAM_256K == 1
#define SYS_RAM_BLOCK_SIZE 64*1024
-#else
+#else
#define SYS_RAM_BLOCK_SIZE 40*1024
#endif
/* instruction port area */
#define SYS_I_R0M_REGION_0_BASE 0x8e0000
-
+
#define SYS_I_RAM_REGION_0_BASE 0x900000
#define SYS_I_RAM_REGION_1_BASE (SYS_I_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_I_RAM_REGION_2_BASE (SYS_I_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_I_RAM_REGION_3_BASE (SYS_I_RAM_REGION_2_BASE+SYS_RAM_BLOCK_SIZE)
-
-/* data port area */
+
+/* data port area */
#define SYS_D_R0M_REGION_0_BASE 0x4e0000
-
+
#define SYS_D_RAM_REGION_0_BASE 0x500000
#define SYS_D_RAM_REGION_1_BASE (SYS_D_RAM_REGION_0_BASE+SYS_RAM_BLOCK_SIZE)
#define SYS_D_RAM_REGION_2_BASE (SYS_D_RAM_REGION_1_BASE+SYS_RAM_BLOCK_SIZE)
#define USB_DEVICE_PID_SIZE 1 // PID SIZE, 1 halfword offset
#define USB_DEVICE_VID_SIZE 1 // VID SIZE, 1 halfword offset
-
+
#define USB_DESC_IN_EEPROM_FLAG_OFFSET USB_DESCRIPTOR_ADDR
#define USB_DEVICE_DESCRIPTOR_OFFSET (USB_DESC_IN_EEPROM_FLAG_OFFSET+USB_DESC_IN_EEPROM_SIZE)
#define USB_STRING00_DESCRIPTOR_OFFSET (USB_DEVICE_DESCRIPTOR_OFFSET+USB_DEVICE_DESCRIPTOR_SIZE)
} wb[MAGPIE_REGDUMP_FRAMES];
};
-typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
+typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
#define RD_SIZE sizeof(CPU_exception_frame_t)
#endif
* XTensa CPU state
* This must match the state saved by the target exception handler.
*/
-
+
#define RD_SIZE sizeof(CPU_exception_frame_t)
/*
-/*\r
- * Copyright (c) 2013 Qualcomm Atheros, Inc.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted (subject to the limitations in the\r
- * disclaimer below) provided that the following conditions are met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- *\r
- * * Neither the name of Qualcomm Atheros nor the names of its\r
- * contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE\r
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT\r
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\r
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\r
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE\r
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN\r
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-/*************************************************************************/\r
-/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */\r
-/* */\r
-/* Module Name : sys_cfg.h */\r
-/* */\r
-/* Abstract */\r
-/* This file contains definition of platform and sysmte config . */\r
-/* */\r
-/* NOTES */\r
-/* None */\r
-/* */\r
-/*************************************************************************/\r
-\r
-#ifndef _SYS_CFG_H_\r
-#define _SYS_CFG_H_\r
-\r
-/************************** FPGA version **************************/\r
-#define MAGPIE_FPGA_RAM_256K 1\r
-\r
-/************************** ROM DEFINE ***************************/\r
-\r
-#if defined(_ROM_)\r
-#include "rom_cfg.h"\r
-\r
-#if MAGPIE_FPGA_RAM_256K == 1 \r
-#undef MAX_BUF_NUM \r
-#define MAX_BUF_NUM 100\r
-#endif\r
-\r
-#elif defined(_RAM_)\r
-\r
-#include "rom_cfg.h"\r
-#include "magpie_mem.h"\r
-\r
-/************************* Resource DEFS ***********************/\r
-#define MAX_DESC_NUM 100\r
-\r
-#ifdef RX_SCATTER\r
-#define MAX_BUF_NUM 60\r
-#else\r
-#define MAX_BUF_NUM 40\r
-#endif\r
-\r
-#if MAGPIE_FPGA_RAM_256K == 1 \r
-#undef MAX_BUF_NUM \r
-#define MAX_BUF_NUM 100\r
-#endif\r
-\r
-#undef SYSTEM_MODULE_DBG\r
-#define SYSTEM_MODULE_DBG 1\r
-\r
-/************************* WLAN DEFS ***************************/\r
-#define MAGPIE_ENABLE_WLAN 1\r
-#define MAGPIE_ENABLE_PCIE 1\r
-#define MAGPIE_ENABLE_WLAN_IN_TARGET 0\r
-#define MAGPIE_ENABLE_WLAN_SELF_TX 0\r
-#define MAGPIE_ENABLE_WLAN_RATE_CTRL 1\r
-#define WLAN_MAX_RXBUF 15\r
-#define WLAN_MAX_TXBUF 10\r
-\r
-/****************************** WATCH DOG *******************************/\r
-#define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds\r
-\r
-#endif\r
-\r
-\r
-#endif /* _SYS_CFG_H_ */\r
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*************************************************************************/
+/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
+/* */
+/* Module Name : sys_cfg.h */
+/* */
+/* Abstract */
+/* This file contains definition of platform and sysmte config . */
+/* */
+/* NOTES */
+/* None */
+/* */
+/*************************************************************************/
+
+#ifndef _SYS_CFG_H_
+#define _SYS_CFG_H_
+
+/************************** FPGA version **************************/
+#define MAGPIE_FPGA_RAM_256K 1
+
+/************************** ROM DEFINE ***************************/
+
+#if defined(_ROM_)
+#include "rom_cfg.h"
+
+#if MAGPIE_FPGA_RAM_256K == 1
+#undef MAX_BUF_NUM
+#define MAX_BUF_NUM 100
+#endif
+
+#elif defined(_RAM_)
+
+#include "rom_cfg.h"
+#include "magpie_mem.h"
+
+/************************* Resource DEFS ***********************/
+#define MAX_DESC_NUM 100
+
+#ifdef RX_SCATTER
+#define MAX_BUF_NUM 60
+#else
+#define MAX_BUF_NUM 40
+#endif
+
+#if MAGPIE_FPGA_RAM_256K == 1
+#undef MAX_BUF_NUM
+#define MAX_BUF_NUM 100
+#endif
+
+#undef SYSTEM_MODULE_DBG
+#define SYSTEM_MODULE_DBG 1
+
+/************************* WLAN DEFS ***************************/
+#define MAGPIE_ENABLE_WLAN 1
+#define MAGPIE_ENABLE_PCIE 1
+#define MAGPIE_ENABLE_WLAN_IN_TARGET 0
+#define MAGPIE_ENABLE_WLAN_SELF_TX 0
+#define MAGPIE_ENABLE_WLAN_RATE_CTRL 1
+#define WLAN_MAX_RXBUF 15
+#define WLAN_MAX_TXBUF 10
+
+/****************************** WATCH DOG *******************************/
+#define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds
+
+#endif
+
+
+#endif /* _SYS_CFG_H_ */
uint16_t (*_uart_char_get)(uint8_t* ch);
void (*_uart_str_out)(uint8_t* str);
void (*_uart_task)(void);
- uint32_t (*_uart_status)(void);\r
+ uint32_t (*_uart_status)(void);
void (*_uart_config)(uint16_t flag);
void (*_uart_hwinit)(uint32_t freq, uint32_t baud);
//void (*_uart_config)(uint8_t cmd, void *pData);
*/
/*
* @File: VBUF_api.h
- *
+ *
* @Abstract: Host Interface api
- *
+ *
* @Notes:
*/
typedef struct _VBUF
{
VDESC *desc_list;
- struct _VBUF *next_buf;
- A_UINT16 buf_length;
+ struct _VBUF *next_buf;
+ A_UINT16 buf_length;
A_UINT8 reserved[2];
- A_UINT8 ctx[MAX_BUF_CTX_LEN];
- //A_UINT8 end_point;
- //A_UINT8 reserved[1];
+ A_UINT8 ctx[MAX_BUF_CTX_LEN];
+ //A_UINT8 end_point;
+ //A_UINT8 reserved[1];
} VBUF;
#define VBUF_GET_DATA_ADDR(vbuf) (vbuf->desc_list->buf_addr + vbuf->desc_list->data_offset)
void (*_free_vbuf)(VBUF *buf);
/* room to expand this table by another table */
- void *pReserved;
+ void *pReserved;
};
extern void vbuf_module_install(struct vbuf_api *apis);
A_UINT16 data_offset;
A_UINT16 data_size;
A_UINT16 control;
- A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE];
+ A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE];
} VDESC;
//#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4)))
void (*_swap_vdesc)(VDESC *dest, VDESC *src);
//void (*_free_vdesc)(void);
/* room to expand this table by another table */
- void *pReserved;
+ void *pReserved;
};
extern void vdesc_module_install(struct vdesc_api *apis);
-#endif
+#endif
/*
* Intentional Misaligned Load special "addresses".
- * Loads from misaligned addresses have special semantics,
+ * Loads from misaligned addresses have special semantics,
* handled by the OS, depending on the lower nibble.
*
* NOTE1: word-aligned nibbles will not cause any exception,
#endif
#ifdef HTC_TRACE_MBOX_PAUSE
-#define A_ASSERT( __bool )
+#define A_ASSERT( __bool )
#else
/*
* Code space dedicated to asserts is minimal. We use an Intentional
// ep0 operation
void (*_usb_ep0_setup)(void);
-
+
void (*_usb_ep0_tx)(void);
void (*_usb_ep0_rx)(void);
BOOLEAN (*_usb_set_configuration)(void);
// standard/vendor command
- BOOLEAN (*_usb_standard_cmd)(void);
+ BOOLEAN (*_usb_standard_cmd)(void);
void (*_usb_vendor_cmd)(void);
void (*_usb_power_off)(void);
void (*_usb_reset_fifo)(void);
void (*_usb_gen_wdt)(void);
void (*_usb_jump_boot)(void);
-
+
BOOLEAN (*_usb_clr_feature)(void);
- BOOLEAN (*_usb_set_feature)(void);
+ BOOLEAN (*_usb_set_feature)(void);
BOOLEAN (*_usb_set_address)(void);
BOOLEAN (*_usb_get_descriptor)(void);
#define ZM_ADDR_CONV 0x0
#define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
-
+
#define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
#define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
#define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
#define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
-
+
#define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
#define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
#define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
-
+
#define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
#if (HS_C1_INTERFACE_NUMBER >= 1)
// Interface 0
#define HS_C1_I0_ALT_NUMBER 0X01
- #if (HS_C1_I0_ALT_NUMBER >= 1)
+ #if (HS_C1_I0_ALT_NUMBER >= 1)
// AlternateSetting 0X00
#define HS_C1_I0_A0_bInterfaceNumber 0X00
#define HS_C1_I0_A0_bAlternateSetting 0X00
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
(USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
-
+
#define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
(USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable
#define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable
#define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
(USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode
(USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable
+#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable
-#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable
+#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable
#define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode
USB_ENABLE_HP_DN_DMA();
#define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
- (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
+ (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));
#define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea
#define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea
*/
/*
* @File: HIF_api.h
- *
+ *
* @Abstract: Host Interface api
- *
+ *
* @Notes:
*/
/* callback to get the buf for receiving commands from USB FIFO */
VBUF* (*get_command_buf)(void);
/* callback when receiving a command */
- void (*recv_command)(VBUF *cmd);
+ void (*recv_command)(VBUF *cmd);
/* callback to get the buf for event to send to the host */
VBUF* (*get_event_buf)(void);
/* callback to indicate the event has been sent to the host */
void (*send_event_done)(VBUF *buf);
-
+
/* context used for all callbacks */
//void *context;
} USB_FIFO_CONFIG;
void (*_enable_event_isr)(void);
/* room to expand this table by another table */
- void *pReserved;
+ void *pReserved;
};
extern void usbfifo_module_install(struct usbfifo_api *apis);
A_DELAY_USECS(60); // wait for stable
- /* CPU & AHB settings */
+ /* CPU & AHB settings */
/*
* AHB clk = ( CPU clk / 2 )
*/
iowrite32_usb(ZM_EP3_DATA_OFFSET, exccause);
iowrite32_usb(ZM_EP3_DATA_OFFSET, pc);
iowrite32_usb(ZM_EP3_DATA_OFFSET, badvaddr);
-
+
mUSB_EP3_XFER_DONE();
}
#endif
A_ASSFAIL(&dump);
-#if defined(_ROM_)
+#if defined(_ROM_)
A_WDT_ENABLE();
#endif
while(1) ;
}
-void
+void
HTCControlSvcProcessMsg_patch(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf,
adf_nbuf_t pBuffers, void *arg)
{
}
/* Patch callback for check the endpoint ID is correct or not */
-void
+void
HTCMsgRecvHandler_patch(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context)
{
int eid;
a_uint32_t anblen;
adf_nbuf_t tmp_nbuf;
HTC_FRAME_HDR *pHTCHdr;
-
+
if (hdr_buf == ADF_NBUF_NULL) {
/* HTC hdr is not in the hdr_buf */
tmp_nbuf = buffer;
} else {
tmp_nbuf = hdr_buf;
}
-
- adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen);
- pHTCHdr = (HTC_FRAME_HDR *)anbdata;
-
+
+ adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen);
+ pHTCHdr = (HTC_FRAME_HDR *)anbdata;
+
eid = pHTCHdr->EndpointID;
-
+
if ((eid != 0) && (htc_complete_setup == 0)) {
A_PRINTF("\nHTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen);
A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n",
- *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3),
+ *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3),
*(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7),
- *(anbdata+8), *(anbdata+9), *(anbdata+10), *(anbdata+11));
+ *(anbdata+8), *(anbdata+9), *(anbdata+10), *(anbdata+11));
A_PRINTF("init_htc_handle = 0x%8x\n", init_htc_handle);
-
+
if (pHTCHdr->EndpointID == 1) {
A_PRINTF("Return WMI Command buffer\n");
HTC_ReturnBuffers(init_htc_handle, 1, tmp_nbuf);
} else {
if ((pHTCHdr->EndpointID < 0) || (pHTCHdr->EndpointID >= ENDPOINT_MAX)) {
A_PRINTF("HTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen);
- A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n",
- *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3),
+ A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n",
+ *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3),
*(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7));
if (anblen > 64) {
A_UINT8 *pData;
netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY, sizeof(WMI_CMD_HDR) + Length);
-
+
if (netbuf == ADF_NBUF_NULL) {
adf_os_print("%s: buffer allocation for event_id %x failed!\n", __FUNCTION__, cmd_id);
adf_os_assert(0);
void Magpie_init(void)
{
A_PRINTF("[+++Magpie_init]\n\r");
-
+
A_PRINTF("[+++VBUF_init(%d)]\n\r", MAX_BUF_NUM);
VBUF_init(MAX_BUF_NUM);
-
+
A_PRINTF("[+++VBUF_init(%d)]\n\r", MAX_DESC_NUM);
VDESC_init(MAX_DESC_NUM);
#if SYSTEM_MODULE_HP_EP6
HIF_config_pipe(hif_handle, HIF_USB_PIPE_MP_TX, 3);
#endif
-
+
A_PRINTF("[+++HIF_init(0)]\n\r");
HIF_start(hif_handle);
WMI_RegisterDispatchTable(Magpie_Sys_Commands_Tbl.pContext, &Magpie_Sys_Commands_Tbl);
#endif/* ZM_FM_LOOPBACK == 0 */
-#endif /* MAGPIE_ENABLE_WLAN */
+#endif /* MAGPIE_ENABLE_WLAN */
}
#endif /* #if MAGPIE==1 */
-/*\r
- * Copyright (c) 2013 Qualcomm Atheros, Inc.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted (subject to the limitations in the\r
- * disclaimer below) provided that the following conditions are met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- *\r
- * * Neither the name of Qualcomm Atheros nor the names of its\r
- * contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE\r
- * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT\r
- * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\r
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\r
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE\r
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN\r
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-#include "sys_cfg.h"\r
-#include "dt_defs.h"\r
-#include "reg_defs.h"\r
-\r
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "sys_cfg.h"
+#include "dt_defs.h"
+#include "reg_defs.h"
+
#include <rom.h>
-#include <osapi.h>\r
-#include <hif_api.h>\r
-#include <Magpie_api.h>\r
-#include <vdesc_api.h>\r
-#include <adf_os_mem.h> \r
-#include <adf_os_io.h>\r
-\r
-#include "hif_usb.h"\r
-\r
-/*\r
- * -- support more than 64 bytes command on ep4 -- \r
- */\r
-int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe)\r
-{\r
- switch(pipe) {\r
- case HIF_USB_PIPE_INTERRUPT:\r
- case HIF_USB_PIPE_COMMAND:\r
- return 512;\r
- \r
- default:\r
- return 1600;\r
- }\r
-}\r
-\r
-/*\r
- * -- move the usb_task to here --\r
- */\r
-void _HIFusb_isr_handler_patch(hif_handle_t h)\r
-{\r
- A_USB_FW_TASK();\r
-\r
+#include <osapi.h>
+#include <hif_api.h>
+#include <Magpie_api.h>
+#include <vdesc_api.h>
+#include <adf_os_mem.h>
+#include <adf_os_io.h>
+
+#include "hif_usb.h"
+
+/*
+ * -- support more than 64 bytes command on ep4 --
+ */
+int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe)
+{
+ switch(pipe) {
+ case HIF_USB_PIPE_INTERRUPT:
+ case HIF_USB_PIPE_COMMAND:
+ return 512;
+
+ default:
+ return 1600;
+ }
+}
+
+/*
+ * -- move the usb_task to here --
+ */
+void _HIFusb_isr_handler_patch(hif_handle_t h)
+{
+ A_USB_FW_TASK();
+
_HIFusb_isr_handler(h);
-}\r
-\r
-\r
-/*\r
- * -- reset usb dma --\r
- *\r
- * - make sure DMA_START bit0 is zero\r
- * - update DMA_START bit4 to 1\r
- * - update DESC_START_ADDR\r
- * - update DMA_START bit 0\r
- */\r
-void _HIFusb_start_patch(hif_handle_t handle) \r
-{\r
- MAGPIE_REG_USB_TX0_DMA_START = 0x0;\r
- MAGPIE_REG_USB_RX0_DMA_START = 0x0;\r
- MAGPIE_REG_USB_RX1_DMA_START = 0x0;\r
- MAGPIE_REG_USB_RX2_DMA_START = 0x0;\r
- \r
- while( 1 )\r
- {\r
- if(!MAGPIE_REG_USB_TX0_DMA_START &&\r
- !MAGPIE_REG_USB_RX0_DMA_START &&\r
- !MAGPIE_REG_USB_RX1_DMA_START &&\r
- !MAGPIE_REG_USB_RX2_DMA_START )\r
- {\r
- MAGPIE_REG_USB_TX0_DMA_START = MAGPIE_REG_USB_TX0_DMA_START|BIT4; \r
- MAGPIE_REG_USB_RX0_DMA_START = MAGPIE_REG_USB_RX0_DMA_START|BIT4;\r
- MAGPIE_REG_USB_RX1_DMA_START = MAGPIE_REG_USB_RX1_DMA_START|BIT4;\r
- MAGPIE_REG_USB_RX2_DMA_START = MAGPIE_REG_USB_RX2_DMA_START|BIT4;\r
- break;\r
- }\r
- }\r
+}
+
+
+/*
+ * -- reset usb dma --
+ *
+ * - make sure DMA_START bit0 is zero
+ * - update DMA_START bit4 to 1
+ * - update DESC_START_ADDR
+ * - update DMA_START bit 0
+ */
+void _HIFusb_start_patch(hif_handle_t handle)
+{
+ MAGPIE_REG_USB_TX0_DMA_START = 0x0;
+ MAGPIE_REG_USB_RX0_DMA_START = 0x0;
+ MAGPIE_REG_USB_RX1_DMA_START = 0x0;
+ MAGPIE_REG_USB_RX2_DMA_START = 0x0;
+
+ while( 1 )
+ {
+ if(!MAGPIE_REG_USB_TX0_DMA_START &&
+ !MAGPIE_REG_USB_RX0_DMA_START &&
+ !MAGPIE_REG_USB_RX1_DMA_START &&
+ !MAGPIE_REG_USB_RX2_DMA_START )
+ {
+ MAGPIE_REG_USB_TX0_DMA_START = MAGPIE_REG_USB_TX0_DMA_START|BIT4;
+ MAGPIE_REG_USB_RX0_DMA_START = MAGPIE_REG_USB_RX0_DMA_START|BIT4;
+ MAGPIE_REG_USB_RX1_DMA_START = MAGPIE_REG_USB_RX1_DMA_START|BIT4;
+ MAGPIE_REG_USB_RX2_DMA_START = MAGPIE_REG_USB_RX2_DMA_START|BIT4;
+ break;
+ }
+ }
_HIFusb_start(handle);
-}\r
+}
a_uint32_t ref_clk = 0;
extern a_uint32_t cticks;
-// clock change
+// clock change
//
void cmnos_clock_init_patch(a_uint32_t refclk)
{
{
a_uint32_t start_time = NOW();
unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us
-
+
while ( (NOW() - start_time) < num_ticks) {
/* busy spin */
;
a_uint32_t cmnos_milliseconds_patch(void)
{
cmnos_tick_patch();
-
+
return (cticks);
}
#define EMULATE_PCI_CONFIG
#endif
-#define PCI_CONFIG_BASE_ADDR 0x14000000
+#define PCI_CONFIG_BASE_ADDR 0x14000000
extern A_PCI_INIT_FUNC g_pci_init_func;
adf_drv_info_t* g_wlan_drv = NULL;
}
#define ATHEROS_VENDOR_ID 0x168c
-#define AR5416_DEVID_PCIE 0x24
+#define AR5416_DEVID_PCIE 0x24
void wlan_pci_probe(void)
{
__adf_softc_t *sc;
adf_os_resource_t drv_res = {0};
- adf_os_attach_data_t drv_data = {{0}};
+ adf_os_attach_data_t drv_data = {{0}};
int vendor_id;
int device_id;
#if MAGPIE_ENABLE_PCIE == 0
vendor_id = ATHEROS_VENDOR_ID;
device_id = AR5416_DEVID_PCIE;
-#else
+#else
vendor_id = wlan_pci_config_read(0, 2);
device_id = wlan_pci_config_read(2, 2);
-#endif
- A_PRINTF("<wlan_pci_probe>: Vendor id 0x%x Dev id 0x%x\n", vendor_id, device_id);
-
+#endif
+ A_PRINTF("<wlan_pci_probe>: Vendor id 0x%x Dev id 0x%x\n", vendor_id, device_id);
+
if (vendor_id != ATHEROS_VENDOR_ID) {
- A_PRINTF("<wlan_pci_probe>: Atheros card not found\n");
+ A_PRINTF("<wlan_pci_probe>: Atheros card not found\n");
return;
}
-
+
/**
* Allocate the sc & zero down
*/
A_PRINTF("Cannot malloc softc\n");
goto mem_fail;
}
-
-#define AR5416_DEVID_PCIE 0x24
+
+#define AR5416_DEVID_PCIE 0x24
drv_data.pci.device = AR5416_DEVID_PCIE;
drv_data.pci.vendor = 0x168c;
drv_data.pci.subvendor = 0;
drv_data.pci.subdevice = 0;
-
+
drv_res.start = (a_uint32_t) 0;
drv_res.end = 0;
drv_res.type = ADF_OS_RESOURCE_TYPE_MEM;
-
+
g_wlan_drv_handle = g_wlan_drv->drv_attach(&drv_res, 1, &drv_data, NULL);
-
+
return;
mem_fail:
- return;
+ return;
}
int wlan_pci_config_write(int offset, a_uint32_t val, int width)
{
-#if MAGPIE_ENABLE_PCIE == 1
+#if MAGPIE_ENABLE_PCIE == 1
unsigned long addr = ( PCI_CONFIG_BASE_ADDR + offset ) & 0xfffffffc;
- A_UINT8 *ptr = (A_UINT8 *)addr;
- A_UINT8 *valptr = (A_UINT8 *)&val;
+ A_UINT8 *ptr = (A_UINT8 *)addr;
+ A_UINT8 *valptr = (A_UINT8 *)&val;
int idx = offset & 0x3;
int i;
-
+
for (i = 0; i < width; i++) {
ptr[idx + i] = valptr[3-i];
- }
+ }
#endif
-
- return 0;
+
+ return 0;
}
int wlan_pci_config_read(int offset, int width)
{
-#if MAGPIE_ENABLE_PCIE == 0
- return 0;
+#if MAGPIE_ENABLE_PCIE == 0
+ return 0;
#else
unsigned long addr = ( PCI_CONFIG_BASE_ADDR + offset ) & 0xfffffffc;
unsigned long value = *((unsigned long *)addr);
- A_UINT8 *ptr = (A_UINT8 *)&value;
+ A_UINT8 *ptr = (A_UINT8 *)&value;
int idx = offset & 0x3;
int result = 0;
int i;
-
+
for (i = 0; i < width; i++) {
result |= (ptr[ 3 - (idx + i)] << (8*i));
- }
-
- return result;
-#endif
+ }
+
+ return result;
+#endif
}
void wlan_pci_isr()
*/
/*
* @File: wlan_pci.h
- *
- * @Abstract:
- *
+ *
+ * @Abstract:
+ *
* @Notes:
*/
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * @File:
- *
+ * @File:
+ *
* @Abstract: internal data and structure definitions for WMI service
- *
- * @Notes:
+ *
+ * @Notes:
*/
#ifndef WMI_INTERNAL_H_
#endif /* WMI_DEBUG */
#define EVT_PKT_IN_USE (1 << 0)
-#define EVT_PKT_IS_FREE(e) !((e)->Flags & EVT_PKT_IN_USE)
+#define EVT_PKT_IS_FREE(e) !((e)->Flags & EVT_PKT_IN_USE)
#define EVT_MARK_FREE(e) (e)->Flags &= ~EVT_PKT_IN_USE;
#define EVT_MARK_INUSE(e) (e)->Flags |= EVT_PKT_IN_USE
#define IS_EVT_CLASS_BUFFERED(ec) ((ec) != WMI_EVT_CLASS_DIRECT_BUFFER)
typedef struct _WMI_POOL_STATE {
int MaxAllocation; /* maximum allocations allowed for this pool */
int CurrentAllocation; /* current allocations outstanding */
-} WMI_POOL_STATE;
+} WMI_POOL_STATE;
typedef struct _WMI_SVC_CONTEXT {
htc_handle_t HtcHandle;
- pool_handle_t PoolHandle;
+ pool_handle_t PoolHandle;
int PendingEvents; /* no. of pending events */
HTC_SERVICE WMIControlService; /* registered control service */
HTC_ENDPOINT_ID ControlEp; /* endpoint assigned to us */
WMI_DISPATCH_TABLE *pDispatchHead; /* dispatch list head ptr */
- WMI_DISPATCH_TABLE *pDispatchTail; /* dispatch list tail ptr */
+ WMI_DISPATCH_TABLE *pDispatchTail; /* dispatch list tail ptr */
// Left a door for extension the structure
void *pReserved;
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
- * @File:
- *
+ * @File:
+ *
* @Abstract: Wireless Module Interface Service Implementation
- *
- * @Notes:
+ *
+ * @Notes:
*/
#include <osapi.h>
#include <Magpie_api.h>
#include <htc.h>
#include <htc_services.h>
#include <wmi_svc_api.h>
-#include <adf_os_mem.h>
+#include <adf_os_mem.h>
#include <adf_os_io.h>
#include "wmi_internal.h"
void *pContext;
WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)arg;
WMI_DISPATCH_TABLE *pCurrentTable;
- WMI_DISPATCH_ENTRY*pCurrentEntry;
+ WMI_DISPATCH_ENTRY*pCurrentEntry;
WMI_CMD_HANDLER pCmdHandler;
- A_UINT8* pCmdBuffer;
+ A_UINT8* pCmdBuffer;
int i;
A_UINT16 cmd;
A_UINT16 seq;
a_uint8_t *anbdata;
a_uint32_t anblen;
WMI_CMD_HDR *cmdHdr;
-
+
adf_os_assert(hdr_buf == ADF_NBUF_NULL);
do {
length = adf_nbuf_len(pHTCBuf);
if (length < sizeof(WMI_CMD_HDR)) {
- break;
+ break;
}
adf_nbuf_peek_header(pHTCBuf, &anbdata, &anblen);
-
+
pCurrentTable = pWMI->pDispatchHead;
length = length - sizeof(WMI_CMD_HDR);
-
+
cmdHdr = (WMI_CMD_HDR *)anbdata;
cmd = adf_os_ntohs(cmdHdr->commandId);
seq = adf_os_ntohs(cmdHdr->seqNo);
-
- pCmdBuffer = anbdata + sizeof(WMI_CMD_HDR);
+
+ pCmdBuffer = anbdata + sizeof(WMI_CMD_HDR);
pCmdHandler = NULL;
-
+
while (pCurrentTable != NULL) {
-
+
pContext = pCurrentTable->pContext;
pCurrentEntry = pCurrentTable->pTable;
-
+
/* scan table entries */
for (i = 0; i < pCurrentTable->NumberOfEntries; i++, pCurrentEntry++) {
if (pCurrentEntry->CmdID == cmd) {
/* found a match */
pCmdHandler = pCurrentEntry->pCmdHandler;
-
+
/* optionally check length */
if ((pCurrentEntry->CheckLength != 0) &&
(length < pCurrentEntry->CheckLength)) {
/* do not process command */
pCmdHandler = NULL;
}
- /* end search */
- break;
- }
- }
-
+ /* end search */
+ break;
+ }
+ }
+
if (pCmdHandler != NULL) {
/* found a handler */
break;
}
-
+
/* scan next table */
pCurrentTable = pCurrentTable->pNext;
}
-
+
if (NULL == pCmdHandler) {
- break;
+ break;
}
-
+
/* if we get here, we have a command handler to dispatch */
-
+
/* call dispatch function */
pCmdHandler(pContext, cmd, seq, pCmdBuffer, length);
-
+
} while (FALSE);
-
-
+
+
/* Invalidate the buffer (including HTC header). Note : we only need to invalidate up to the portion
- * that was used (cache invalidate will also round up to the nearest cache line).
+ * that was used (cache invalidate will also round up to the nearest cache line).
* The rest of the buffer should still be coherent.
* */
- HTC_ReturnBuffers(pWMI->HtcHandle, EndPt, pHTCBuf);
+ HTC_ReturnBuffers(pWMI->HtcHandle, EndPt, pHTCBuf);
}
/* send completion handler when any HTC buffers are returned */
WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)arg;
WMI_BUF_CONTEXT *ctx;
BUF_POOL_ID poolId;
-
+
ctx = (WMI_BUF_CONTEXT *)adf_nbuf_get_priv(pHTCBuf);
-
+
if ( ctx->EventClass == WMI_EVT_CLASS_CMD_EVENT ) {
poolId = POOL_ID_WMI_SVC_EVENT;
} else {
poolId = POOL_ID_WMI_SVC_CMD_REPLY;
}
-
+
BUF_Pool_free_buf(pWMI->PoolHandle, poolId, pHTCBuf);
}
static A_UINT8 WMIServiceConnect(HTC_SERVICE *pService,
- HTC_ENDPOINT_ID eid,
- A_UINT8 *pDataIn,
+ HTC_ENDPOINT_ID eid,
+ A_UINT8 *pDataIn,
int LengthIn,
A_UINT8 *pDataOut,
int *pLengthOut)
{
WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)pService->ServiceCtx;
-
+
/* save the eid to use */
pWMI->ControlEp = eid;
return HTC_SERVICE_SUCCESS;
}
/************** public APIS ********************************************/
-
+
static wmi_handle_t _WMI_Init(WMI_SVC_CONFIG *pWmiConfig)
{
WMI_SVC_CONTEXT *pWMI = NULL;
int eventSize = WMI_SVC_MAX_BUFFERED_EVENT_SIZE + sizeof(WMI_CMD_HDR) + HTC_HDR_SZ;
-
+
pWMI = (WMI_SVC_CONTEXT *)adf_os_mem_alloc(sizeof(WMI_SVC_CONTEXT));
if (pWMI == NULL) {
- return NULL;
+ return NULL;
}
-
+
pWMI->pDispatchHead = NULL;
pWMI->PoolHandle = pWmiConfig->PoolHandle;
- pWMI->HtcHandle = pWmiConfig->HtcHandle;
-
- BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_CMD_REPLY,
+ pWMI->HtcHandle = pWmiConfig->HtcHandle;
+
+ BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_CMD_REPLY,
pWmiConfig->MaxCmdReplyEvts, eventSize);
-
- BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_EVENT,
+
+ BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_EVENT,
pWmiConfig->MaxEventEvts, eventSize);
-
- /* NOTE: since RAM allocation is zero-initialized, there is nothing to do for the
+
+ /* NOTE: since RAM allocation is zero-initialized, there is nothing to do for the
* direct event pool */
-
+
/* register the WMI control service */
pWMI->WMIControlService.ProcessRecvMsg = A_INDIR(wmi_svc_api._WMI_RecvMessageHandler);
pWMI->WMIControlService.ProcessSendBufferComplete = A_INDIR(wmi_svc_api._WMI_SendCompleteHandler);
pWMI->WMIControlService.ProcessConnect = A_INDIR(wmi_svc_api._WMI_ServiceConnect);
pWMI->WMIControlService.MaxSvcMsgSize = WMI_SVC_MSG_SIZE + sizeof(WMI_CMD_HDR);
- /* all buffers that are sent through the control endpoint are at least WMI_SVC_MAX_BUFFERED_EVENT_SIZE
+ /* all buffers that are sent through the control endpoint are at least WMI_SVC_MAX_BUFFERED_EVENT_SIZE
* in size. Any WMI event that supplies a data buffer must insure that the space in the buffer
* is at least this size. */
- pWMI->WMIControlService.TrailerSpcCheckLimit = WMI_SVC_MAX_BUFFERED_EVENT_SIZE;
+ pWMI->WMIControlService.TrailerSpcCheckLimit = WMI_SVC_MAX_BUFFERED_EVENT_SIZE;
pWMI->WMIControlService.ServiceID = WMI_CONTROL_SVC;
pWMI->WMIControlService.ServiceCtx = pWMI;
HTC_RegisterService(pWmiConfig->HtcHandle, &pWMI->WMIControlService);
-
+
return pWMI;
}
WMI_DISPATCH_TABLE *pDispatchTable)
{
WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle;
-
+
if (NULL == pWMI->pDispatchHead) {
pWMI->pDispatchHead = pDispatchTable;
- pWMI->pDispatchTail = pDispatchTable;
+ pWMI->pDispatchTail = pDispatchTable;
} else {
/* link to the tail */
pWMI->pDispatchTail->pNext = pDispatchTable;
- pWMI->pDispatchTail = pDispatchTable;
+ pWMI->pDispatchTail = pDispatchTable;
}
}
static adf_nbuf_t _WMI_AllocEvent(wmi_handle_t handle, WMI_EVT_CLASS EventClass,
int Length)
-{
+{
BUF_POOL_ID poolId;
WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle;
adf_nbuf_t buf;
WMI_BUF_CONTEXT *ctx;
-
+
if ( EventClass == WMI_EVT_CLASS_CMD_EVENT ) {
poolId = POOL_ID_WMI_SVC_EVENT;
} else {
poolId = POOL_ID_WMI_SVC_CMD_REPLY;
}
-
- buf = BUF_Pool_alloc_buf(pWMI->PoolHandle,
- poolId,
+
+ buf = BUF_Pool_alloc_buf(pWMI->PoolHandle,
+ poolId,
sizeof(WMI_CMD_HDR) + HTC_GetReservedHeadroom(pWMI->HtcHandle));
-
+
if ( buf != NULL ) {
ctx = (WMI_BUF_CONTEXT *)adf_nbuf_get_priv(buf);
ctx->EventClass = EventClass;
return buf;
}
-static void _WMI_SendEvent(wmi_handle_t handle, adf_nbuf_t pEvt,
+static void _WMI_SendEvent(wmi_handle_t handle, adf_nbuf_t pEvt,
A_UINT16 EventId, A_UINT16 SeqNo, int Length)
{
WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle;
A_UINT8 *pBuffer;
-
+
pBuffer = adf_nbuf_push_head(pEvt, sizeof(WMI_CMD_HDR));
- A_SET_UINT16_FIELD(pBuffer, WMI_CMD_HDR, commandId, adf_os_htons(EventId));
+ A_SET_UINT16_FIELD(pBuffer, WMI_CMD_HDR, commandId, adf_os_htons(EventId));
A_SET_UINT16_FIELD(pBuffer, WMI_CMD_HDR, seqNo, adf_os_htons(SeqNo));
-
- HTC_SendMsg(pWMI->HtcHandle, pWMI->ControlEp, pEvt);
+
+ HTC_SendMsg(pWMI->HtcHandle, pWMI->ControlEp, pEvt);
}
static void _WMI_Shutdown(wmi_handle_t handle)
typedef enum WMI_EVT_CLASS {
WMI_EVT_CLASS_NONE = -1,
WMI_EVT_CLASS_CMD_EVENT = 0,
- WMI_EVT_CLASS_CMD_REPLY = 1,
+ WMI_EVT_CLASS_CMD_REPLY = 1,
WMI_EVT_CLASS_MAX
} WMI_EVT_CLASS;
int MaxCmdReplyEvts; /* total buffers for command replies */
int MaxEventEvts; /* total buffers for low priority events */
} WMI_SVC_CONFIG;
-
+
/* command dispatch entry */
typedef struct _WMI_DISPATCH_ENTRY {
WMI_CMD_HANDLER pCmdHandler; /* dispatch function */
A_UINT16 CmdID; /* WMI command to dispatch from */
- A_UINT16 CheckLength; /* expected length of command, set to 0 to bypass check */
+ A_UINT16 CheckLength; /* expected length of command, set to 0 to bypass check */
} WMI_DISPATCH_ENTRY;
/* dispatch table that is used to register a set of dispatch entries */
typedef struct _WMI_DISPATCH_TABLE {
struct _WMI_DISPATCH_TABLE *pNext; /* next dispatch, WMI-reserved */
- void *pContext; /* optional context that is passed to command handlers
+ void *pContext; /* optional context that is passed to command handlers
assigned to this dispatch table */
int NumberOfEntries; /* number of elements pointed to by pTable */
WMI_DISPATCH_ENTRY *pTable; /* start of table */
} WMI_DISPATCH_TABLE;
#define WMI_DISPATCH_ENTRY_COUNT(table) \
- (sizeof((table)) / sizeof(WMI_DISPATCH_ENTRY))
+ (sizeof((table)) / sizeof(WMI_DISPATCH_ENTRY))
/* handy macro to declare a dispatch table */
#define WMI_DECLARE_DISPATCH_TABLE(name,dispatchEntries) \
typedef struct _WMI_BUF_CONTEXT {
HTC_BUF_CONTEXT HtcBufCtx;
-
- WMI_EVT_CLASS EventClass; /* the event class this packet belongs to */
- A_UINT16 Flags; /* internal flags reserved for WMI */
+
+ WMI_EVT_CLASS EventClass; /* the event class this packet belongs to */
+ A_UINT16 Flags; /* internal flags reserved for WMI */
} WMI_BUF_CONTEXT;
/* ROM-version, eventually. For now, in RAM */
-
+
typedef void* wmi_handle_t;
-
+
/* the API table */
typedef struct _wmi_svc_apis {
wmi_handle_t (* _WMI_Init)(WMI_SVC_CONFIG *pWmiConfig);
void (* _WMI_SendCompleteHandler)(HTC_ENDPOINT_ID Endpt, adf_nbuf_t pHTCBuf, void *arg);
int (* _WMI_GetControlEp)(wmi_handle_t h);
void (* _WMI_Shutdown)(wmi_handle_t h);
-
+
/* */
void (*_WMI_RecvMessageHandler)(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t pHTCBuf, void *arg);
- A_UINT8 (*_WMI_ServiceConnect)(HTC_SERVICE *pService, HTC_ENDPOINT_ID eid,
- A_UINT8 *pDataIn,
+ A_UINT8 (*_WMI_ServiceConnect)(HTC_SERVICE *pService, HTC_ENDPOINT_ID eid,
+ A_UINT8 *pDataIn,
int LengthIn,
A_UINT8 *pDataOut,
int *pLengthOut);
-
+
void *pReserved; /* for expansion if need be */
} WMI_SVC_APIS;
*/
#define IEEE80211_AMPDU_LIMIT_MIN (1 * 1024)
#define IEEE80211_AMPDU_LIMIT_MAX (64 * 1024 - 1)
-#define IEEE80211_AMPDU_SUBFRAME_MIN 2
-#define IEEE80211_AMPDU_SUBFRAME_MAX 64
-#define IEEE80211_AMPDU_SUBFRAME_DEFAULT 32
+#define IEEE80211_AMPDU_SUBFRAME_MIN 2
+#define IEEE80211_AMPDU_SUBFRAME_MAX 64
+#define IEEE80211_AMPDU_SUBFRAME_DEFAULT 32
#define IEEE80211_AMSDU_LIMIT_MAX 4096
struct ieee80211_rateset {
#undef OFDM_SYMBOL_TIME
#ifdef MAGPIE_MERLIN
-a_uint32_t
+a_uint32_t
ath_hal_get_curmode(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
{
if (!chan)
return HAL_MODE_11NG;
if (IS_CHAN_NA(chan))
- return HAL_MODE_11NA;
+ return HAL_MODE_11NA;
if (IS_CHAN_A(chan))
return HAL_MODE_11A;
a_uint32_t ah_magic;
HAL_SOFTC ah_sc;
adf_os_device_t ah_dev;
-
+
a_uint32_t ah_macVersion;
a_uint16_t ah_macRev;
a_uint16_t ah_phyRev;
void __ahdecl(*ah_detach)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
HAL_BOOL incTrigLevel);
-
+
/* Misc Functions */
- void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t);
+ void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t);
void __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t);
-
-
+
+
/* Target Transmit Functions */
HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp);
- a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q);
+ a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q);
HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t);
HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, a_uint32_t);
-
+
HAL_BOOL __ahdecl(*ah_abortTxDma)(struct ath_hal *);
-
+
void __ahdecl(*ah_set11nTxDesc)(struct ath_tx_desc *ds,
a_uint32_t pktLen, HAL_PKT_TYPE type,
a_uint32_t txPower, a_uint32_t keyIx,
void __ahdecl(*ah_set11nBurstDuration)(struct ath_tx_desc *ds,
a_uint32_t burstDuration);
void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_tx_desc *ds, a_uint32_t vmf);
-
+
HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_tx_desc *,
a_uint32_t pktLen, a_uint32_t hdrLen,
HAL_PKT_TYPE type, a_uint32_t txPower,
a_uint32_t filter0, a_uint32_t filter1);
u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
-
+
/* Target receive Functions */
void __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp);
HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_rx_desc *,
a_uint32_t size, a_uint32_t flags);
HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf);
- HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah,
+ HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah,
struct ath_rx_desc *ds, a_uint32_t pa,
- struct ath_desc *nds,
+ struct ath_desc *nds,
struct ath_rx_status *rx_stats);
HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
void __ahdecl(*ah_enableReceive)(struct ath_hal*);
-
+
/* Interrupt functions */
HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
#define AR5416_PWR_TABLE_OFFSET -5
#define AR5416_LEGACY_CHAINMASK 1
#define AR5416_1_CHAINMASK 1
-#define AR5416_2LOHI_CHAINMASK 5
-#define AR5416_2LOMID_CHAINMASK 3
+#define AR5416_2LOHI_CHAINMASK 5
+#define AR5416_2LOMID_CHAINMASK 3
#define AR5416_3_CHAINMASK 7
#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
struct ath_hal_private ah_priv; /* base class */
a_uint16_t ah_antennaSwitchSwap; /* Controls mapping of OID request */
a_uint32_t ah_maskReg; /* copy of AR_IMR */
-
+
a_uint32_t ah_slottime; /* user-specified slot time */
a_int16_t ah_txPowerIndexOffset;
-
+
a_uint32_t ah_intrTxqs;
void *ah_cal_mem;
a_uint16_t ah_ratesArray[Ar5416RateSize];
/* TRUE_ALL_11N - valid for 20/40/Legacy, TRUE - Legacy only, TRUE_20 - HT 20 only, TRUE_40 - HT 40 only */
/* 4ms frame limit not used for NG mode. The values filled for HT are the 64K max aggregate limit */
-#ifndef MAGPIE_MERLIN // K2
+#ifndef MAGPIE_MERLIN // K2
RATE_TABLE_11N ar5416_11ngRateTable = {
- 54, /* number of rates - should match the no. of rows below */
- 100, /* probe interval */
- 50, /* rssi reduce interval */
+ 54, /* number of rates - should match the no. of rows below */
+ 100, /* probe interval */
+ 50, /* rssi reduce interval */
WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
{/* Multiple Single */
/* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/
/* 121.5Mb [41] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 8, 23, 3, 20, 41, 42, 42, 1, 1, 60156, FALSE},
/* 135 Mb [42] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,135000,111900,0x86, 0x00, 6, 8, 23, 3, 20, 41, 42, 42, 1, 1, 66840, FALSE},
/* 135 Mb [43] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 8, 25, 3, 22, 43, 44, 44, 1, 1, 66840, TRUE},
- /* 150 Mb [44] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 22, 43, 44, 44, 1, 1, 74200, TRUE},
+ /* 150 Mb [44] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 22, 43, 44, 44, 1, 1, 74200, TRUE},
/* 108 Mb [45] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,108000,92500, 0x8b, 0x00, 11, 8, 10, 3, 24, 45, 45, 45, 3, 7, 53440, FALSE},
/* 162 Mb [46] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,162000,130300,0x8c, 0x00, 12, 8, 14, 3, 25, 46, 47, 47, 3, 7, 80160, TRUE},
/* 180 Mb [47] */ { FALSE, FALSE, WLAN_PHY_HT_40_DS_HGI,180000,156900,0x8c, 0x00, 12, 8, 14, 3, 25, 46, 47, 47, 3, 7, 89090, TRUE},
/* 300 Mb [53] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 8, 25, 3, 31, 52, 53, 53, 3, 5, 148400, TRUE},
/* Multiple Single */
/* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/
- /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */
+ /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */
},
};
RATE_TABLE_11N ar5416_11ngRateTable = {
- 46, /* number of rates - should match the no. of rows below */
- 50, /* probe interval */
- 50, /* rssi reduce interval */
+ 46, /* number of rates - should match the no. of rows below */
+ 50, /* probe interval */
+ 50, /* rssi reduce interval */
WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
{/* Multiple Single Single */
/* stream stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/
/* 108 Mb [33] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 8, 20, 3, 17, 33, 33, 33, 1, 1, 53476, FALSE},
/* 121.5Mb [34] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 8, 23, 3, 18, 34, 34, 34, 1, 1, 60156, FALSE},
/* 135 Mb [35] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 8, 25, 3, 19, 35, 36, 36, 1, 1, 66840, TRUE},
- /* 150 Mb [36] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 19, 35, 36, 36, 1, 1, 74200, TRUE},
+ /* 150 Mb [36] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 19, 35, 36, 36, 1, 1, 74200, TRUE},
/* 27 Mb [37] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,27000, 25800, 0x88, 0x00, 8, 8, 2, 3, 20, 37, 37, 37, 3, 7, 13360, TRUE},
/* 54 Mb [38] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,54000, 49800, 0x89, 0x00, 9, 8, 4, 3, 21, 38, 38, 38, 3, 7, 26720, FALSE},
/* 81 Mb [39] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,81000, 71900, 0x8a, 0x00, 10, 8, 6, 3, 22, 39, 39, 39, 3, 7, 40080, TRUE},
/* 300 Mb [45] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 8, 25, 3, 27, 44, 45, 45, 3, 5, 148400, TRUE},
/* Multiple Single */
/* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/
- /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */
+ /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */
},
};
//static RATE_TABLE_11N ar5416_11naRateTable = {
RATE_TABLE_11N ar5416_11naRateTable = {
- 42, /* number of rates */
- 50, /* probe interval */
- 50, /* rssi reduce interval */
+ 42, /* number of rates */
+ 50, /* probe interval */
+ 50, /* rssi reduce interval */
WLAN_RC_HT_FLAG, /* Phy rates allowed initially */
{/* Multiple Single Single*/
/* stream stream stream rate short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for */
/* 108 Mb [29] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 4, 20, 3, 13, 29, 29, 29, 1, 1, 53476, FALSE},
/* 121.5Mb [30] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 4, 23, 3, 14, 30, 30, 30, 1, 1, 60156, FALSE},
/* 135 Mb [31] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 4, 25, 3, 15, 31, 32, 32, 1, 1, 66840, TRUE},
- /* 150 Mb [32] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 15, 31, 32, 32, 1, 1, 65535, TRUE},
+ /* 150 Mb [32] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 15, 31, 32, 32, 1, 1, 65535, TRUE},
/* 27 Mb [33] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,27000, 25800, 0x88, 0x00, 8, 0, 2, 3, 16, 33, 33, 33, 3, 7, 13360, TRUE},
/* 54 Mb [34] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,54000, 49800, 0x89, 0x00, 9, 2, 4, 3, 17, 34, 34, 34, 3, 7, 26720, FALSE},
/* 81 Mb [35] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,81000, 71900, 0x8a, 0x00, 10, 2, 6, 3, 18, 35, 35, 35, 3, 7, 40080, TRUE},
/* 270 Mb [40] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,270000,192100,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 41, 41, 3, 5, 133600, TRUE},
/* 300 Mb [41] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 41, 41, 3, 5, 148400, TRUE},
/* stream stream rate short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for */
- /* valid valid Kbps uKbps Code Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */
+ /* valid valid Kbps uKbps Code Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */
},
};
#endif //ATH_SUPPORT_A_MODE
-#endif //#ifdef MAGPIE_MERLIN // MAGPIE_MERLIN
+#endif //#ifdef MAGPIE_MERLIN // MAGPIE_MERLIN
void
ar5416AttachRateTables(struct atheros_softc *sc)
/* Transmit functions */
.ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
.ah_setTxDP = ar5416SetTxDP,
- .ah_numTxPending = ar5416NumTxPending,
+ .ah_numTxPending = ar5416NumTxPending,
.ah_startTxDma = ar5416StartTxDma,
.ah_stopTxDma = ar5416StopTxDma,
void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
{
a_uint32_t phybits;
-
+
iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
phybits = 0;
if (bits & HAL_RX_FILTER_PHYRADAR)
return HAL_EINPROGRESS;
/*
- * Now we need to get the stats from the descriptor. Since desc are
+ * Now we need to get the stats from the descriptor. Since desc are
* uncached, lets make a copy of the stats first. Note that, since we
* touch most of the rx stats, a memcpy would always be more efficient
*
rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
/* XXX what about KeyCacheMiss? */
- rx_stats->rs_rssi_combined =
+ rx_stats->rs_rssi_combined =
MS(ads.ds_rxstatus4, AR_RxRSSICombined);
rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
{
a_uint32_t i;
-
+
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
- ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
+ ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
- | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
+ | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
| SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
if (keyIx != HAL_TXKEYIX_INVALID) {
{
struct ar5416_desc *ads = AR5416DESC(gds);
struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
-
+
if ((ads->ds_txstatus9 & AR_TxDone) == 0)
return HAL_EINPROGRESS;
* ``alternate'' if it wasn't the series 0 rate.
*/
ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
- ds->ds_txstat.ts_rssi_combined =
+ ds->ds_txstat.ts_rssi_combined =
MS(ads->ds_txstatus5, AR_TxRSSICombined);
ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
/*
- * We use a stack variable to manipulate ctl6 to reduce uncached
+ * We use a stack variable to manipulate ctl6 to reduce uncached
* read modify, modfiy, write.
*/
ctl6 = ads->ds_ctl6;
a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags);
extern void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds,
- a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, HAL_11N_RATE_SERIES series[],
+ a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, HAL_11N_RATE_SERIES series[],
a_uint32_t nseries, a_uint32_t flags);
extern void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds,
a_uint32_t aggrLen, a_uint32_t numDelims);
a_uint32_t vmf);
extern HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *,
a_uint32_t size, a_uint32_t flags);
-extern HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah,
+extern HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah,
struct ath_rx_desc *, a_uint32_t,
struct ath_desc *,
struct ath_rx_status *);
#define AR_SREV_VERSION_HOWL 0x014
#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah))
-#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah))
+#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah))
#ifdef AR5416_EMULATION
/* XXX - AR5416 Emulation only
((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN) && \
(AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_MERLIN_20)))
-#define AR_SREV_SOWL(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SOWL))
+#define AR_SREV_SOWL(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SOWL))
#define AR_SREV_SOWL_11(_ah) (AR_SREV_SOWL(_ah) && (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_SOWL_11))
#define AR_RADIO_SREV_MAJOR 0xf0
/* is 802.11 address multicast/broadcast? */
#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01)
-#ifdef __CARRIER_PLATFORM__
+#ifdef __CARRIER_PLATFORM__
#include <ath_carr_pltfrm.h>
#endif
a_uint16_t i_crc;
} adf_os_packed;
-#define IEEE80211_PLCP_SFD 0xF3A0
+#define IEEE80211_PLCP_SFD 0xF3A0
#define IEEE80211_PLCP_SERVICE 0x00
/*
CTRY_CANADA2 = 5001 /* Canada */
};
-/*
+/*
* Country information element.
*/
#define IEEE80211_COUNTRY_MAX_TRIPLETS (83)
} adf_os_packed;
/*
- * Management Action Frames
+ * Management Action Frames
*/
/* generic frame format */
/* HT - recommended transmission channel width */
struct ieee80211_action_ht_txchwidth {
struct ieee80211_action at_header;
- a_uint8_t at_chwidth;
+ a_uint8_t at_chwidth;
} adf_os_packed;
#define IEEE80211_A_HT_TXCHWIDTH_20 0
struct ieee80211_action_ba_addbarequest {
struct ieee80211_action rq_header;
a_uint8_t rq_dialogtoken;
- struct ieee80211_ba_parameterset rq_baparamset;
+ struct ieee80211_ba_parameterset rq_baparamset;
a_uint16_t rq_batimeout; /* in TUs */
struct ieee80211_ba_seqctrl rq_basequencectrl;
} adf_os_packed;
struct ieee80211_action rs_header;
a_uint8_t rs_dialogtoken;
a_uint16_t rs_statuscode;
- struct ieee80211_ba_parameterset rs_baparamset;
+ struct ieee80211_ba_parameterset rs_baparamset;
a_uint16_t rs_batimeout; /* in TUs */
} adf_os_packed;
/* HT capability flags */
#define IEEE80211_HTCAP_C_ADVCODING 0x0001
-#define IEEE80211_HTCAP_C_CHWIDTH40 0x0002
+#define IEEE80211_HTCAP_C_CHWIDTH40 0x0002
#define IEEE80211_HTCAP_C_SMPOWERSAVE_STATIC 0x0000 /* Capable of SM Power Save (Static) */
#define IEEE80211_HTCAP_C_SMPOWERSAVE_DYNAMIC 0x0004 /* Capable of SM Power Save (Dynamic) */
#define IEEE80211_HTCAP_C_SM_RESERVED 0x0008 /* Reserved */
#define IEEE80211_HTCAP_C_RXSTBC 0x0100 /* 2 bits */
#define IEEE80211_HTCAP_C_DELAYEDBLKACK 0x0400
#define IEEE80211_HTCAP_C_MAXAMSDUSIZE 0x0800 /* 1 = 8K, 0 = 3839B */
-#define IEEE80211_HTCAP_C_DSSSCCK40 0x1000
-#define IEEE80211_HTCAP_C_PSMP 0x2000
-#define IEEE80211_HTCAP_C_INTOLERANT40 0x4000
-#define IEEE80211_HTCAP_C_LSIGTXOPPROT 0x8000
+#define IEEE80211_HTCAP_C_DSSSCCK40 0x1000
+#define IEEE80211_HTCAP_C_PSMP 0x2000
+#define IEEE80211_HTCAP_C_INTOLERANT40 0x4000
+#define IEEE80211_HTCAP_C_LSIGTXOPPROT 0x8000
#define IEEE80211_HTCAP_C_SM_MASK 0x000c /* Spatial Multiplexing (SM) capabitlity bitmask */
/* HT extended capability flags */
#define IEEE80211_HTCAP_EXTC_PCO 0x0001
-#define IEEE80211_HTCAP_EXTC_TRANS_TIME_RSVD 0x0000
+#define IEEE80211_HTCAP_EXTC_TRANS_TIME_RSVD 0x0000
#define IEEE80211_HTCAP_EXTC_TRANS_TIME_400 0x0002 /* 20-40 switch time */
#define IEEE80211_HTCAP_EXTC_TRANS_TIME_1500 0x0004 /* in us */
-#define IEEE80211_HTCAP_EXTC_TRANS_TIME_5000 0x0006
+#define IEEE80211_HTCAP_EXTC_TRANS_TIME_5000 0x0006
#define IEEE80211_HTCAP_EXTC_RSVD_1 0x00f8
#define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_NONE 0x0000
#define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_RSVD 0x0100
/* extension channel offset (2 bit signed number) */
enum {
- IEEE80211_HTINFO_EXTOFFSET_NA = 0, /* 0 no extension channel is present */
- IEEE80211_HTINFO_EXTOFFSET_ABOVE = 1, /* +1 extension channel above control channel */
- IEEE80211_HTINFO_EXTOFFSET_UNDEF = 2, /* -2 undefined */
+ IEEE80211_HTINFO_EXTOFFSET_NA = 0, /* 0 no extension channel is present */
+ IEEE80211_HTINFO_EXTOFFSET_ABOVE = 1, /* +1 extension channel above control channel */
+ IEEE80211_HTINFO_EXTOFFSET_UNDEF = 2, /* -2 undefined */
IEEE80211_HTINFO_EXTOFFSET_BELOW = 3 /* -1 extension channel below control channel*/
};
/* recommended transmission width set */
enum {
- IEEE80211_HTINFO_TXWIDTH_20,
- IEEE80211_HTINFO_TXWIDTH_2040
+ IEEE80211_HTINFO_TXWIDTH_20,
+ IEEE80211_HTINFO_TXWIDTH_2040
};
/* operating flags */
#define IEEE80211_HTINFO_OPMODE_PURE 0x00 /* no protection */
-#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_OPT 0x01 /* prot optional (legacy device maybe present) */
-#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_40 0x02 /* prot required (20 MHz) */
-#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_ALL 0x03 /* prot required (legacy devices present) */
+#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_OPT 0x01 /* prot optional (legacy device maybe present) */
+#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_40 0x02 /* prot required (20 MHz) */
+#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_ALL 0x03 /* prot required (legacy devices present) */
#define IEEE80211_HTINFO_OPMODE_MASK 0x03 /* For protection 0x00-0x03 */
/* Non-greenfield STAs present */
#define IEEE80211_WEP_EXTIV 0x20
#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */
#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */
-#define IEEE80211_WEP_ICVLEN 4
+#define IEEE80211_WEP_ICVLEN 4
#define IEEE80211_WAPI_MICLEN 16 /* trailing MIC */
#define IEEE80211_WAPI_IVLEN 16
#define IEEE80211_AID(b) ((b) &~ 0xc000)
-/*
+/*
* RTS frame length parameters. The default is specified in
* the 802.11 spec. The max may be wrong for jumbo frames.
*/
#define IEEE80211_RTS_MIN 1
#define IEEE80211_RTS_MAX 2346
-/*
+/*
* Regulatory extention identifier for country IE.
*/
#define IEEE80211_REG_EXT_ID 201
};
#define IEEE80211_KEYBUF_SIZE 16
-#define IEEE80211_TID_SIZE 17
+#define IEEE80211_TID_SIZE 17
#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx+rx keys */
struct ieee80211_key_target {
#undef CRYPTO_KEY_TYPE_WAPI
#undef IEEE80211_WLAN_HDR_LEN
}
-#undef IEEE80211_ADDR_LEN
+#undef IEEE80211_ADDR_LEN
/*
* Built-in implementation for local skb free. Only interesting for platforms
* that pass skbs between OS instances.
- */
+ */
#define ieee80211_tgt_free_local_nbuf( _nbuf) ieee80211_tgt_free_nbuf( _nbuf)
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-
+
#ifndef _DEV_ATH_PCI_H_
#define _DEV_ATH_PCI_H_
#define ATH_RC_RTSCTS_FLAG 0x10
#define ATH_RC_TX_STBC_FLAG 0x20 /* TX STBC */
#define ATH_RC_RX_STBC_FLAG 0xC0 /* RX STBC ,2 bits */
-#define ATH_RC_RX_STBC_FLAG_S 6
+#define ATH_RC_RX_STBC_FLAG_S 6
#define ATH_RC_WEP_TKIP_FLAG 0x100 /* WEP/TKIP encryption */
enum ath_rc_cwmode{
ATH_RC_CW20_MODE,
- ATH_RC_CW40_MODE,
+ ATH_RC_CW40_MODE,
};
#define ATH_RC_PROBE_ALLOWED 0x00000001
#define ATH_RC_MINRATE_LASTRATE 0x00000002
struct ath_rc_series {
- a_uint8_t rix;
- a_uint8_t tries;
+ a_uint8_t rix;
+ a_uint8_t tries;
u_int8_t tx_chainmask;
a_uint8_t flags;
a_uint32_t max4msframelen;
a_int32_t nframes, a_int32_t nbad);
-void ath_rate_stateupdate(struct ath_softc_tgt *sc, struct ath_node_target *an,
+void ath_rate_stateupdate(struct ath_softc_tgt *sc, struct ath_node_target *an,
enum ath_rc_cwmode cwmode);
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
(((a_uint16_t)(((a_uint8_t *)(p))[(highbyte)])) << 8 | (a_uint16_t)(((a_uint8_t *)(p))[(lowbyte)]))
-
-/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
+
+/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
* structure using only the type and field name.
* Use these macros if there is the potential for unaligned buffer accesses. */
#define A_GET_UINT16_FIELD(p,type,field) \
((a_uint8_t *)(p))[A_OFFSETOF(type,field)] = (a_uint8_t)((value) >> 8); \
((a_uint8_t *)(p))[A_OFFSETOF(type,field) + 1] = (a_uint8_t)(value); \
}
-
+
#define A_GET_UINT8_FIELD(p,type,field) \
((a_uint8_t *)(p))[A_OFFSETOF(type,field)]
-
+
#define A_SET_UINT8_FIELD(p,type,field,value) \
((a_uint8_t *)(p))[A_OFFSETOF(type,field)] = (value)
/****** DANGER DANGER ***************
- *
+ *
* The frame header length and message formats defined herein were
* selected to accommodate optimal alignment for target processing. This reduces code
* size and improves performance.
- *
+ *
* Any changes to the header length may alter the alignment and cause exceptions
* on the target. When adding to the message structures insure that fields are
* properly aligned.
- *
+ *
*/
/* endpoint defines */
{
ENDPOINT_UNUSED = -1,
ENDPOINT0 = 0, /* this is reserved for the control endpoint */
- ENDPOINT1 = 1,
- ENDPOINT2 = 2,
+ ENDPOINT1 = 1,
+ ENDPOINT2 = 2,
ENDPOINT3 = 3,
ENDPOINT4,
ENDPOINT5,
a_uint8_t EndpointID;
a_uint8_t Flags;
a_uint16_t PayloadLen; /* length of data (including trailer) that follows the header */
-
+
/***** end of 4-byte lookahead ****/
-
+
a_uint8_t ControlBytes[4];
-
+
/* message payload starts after the header */
-
+
} POSTPACK HTC_FRAME_HDR;
/* frame header flags */
typedef enum {
HTC_MSG_READY_ID = 1,
HTC_MSG_CONNECT_SERVICE_ID = 2,
- HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3,
+ HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3,
HTC_MSG_SETUP_COMPLETE_ID = 4,
HTC_MSG_CONFIG_PIPE_ID = 5,
HTC_MSG_CONFIG_PIPE_RESPONSE_ID = 6,
} HTC_MSG_IDS;
-
+
#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
-
+
/* base message ID header */
typedef PREPACK struct {
- a_uint16_t MessageID;
+ a_uint16_t MessageID;
} POSTPACK HTC_UNKNOWN_MSG;
-
+
/* HTC ready message
* direction : target-to-host */
typedef PREPACK struct {
a_uint16_t MessageID; /* ID */
- a_uint16_t CreditCount; /* number of credits the target can offer */
+ a_uint16_t CreditCount; /* number of credits the target can offer */
a_uint16_t CreditSize; /* size of each credit */
a_uint8_t MaxEndpoints; /* maximum number of endpoints the target has resources for */
a_uint8_t _Pad1;
* direction : host-to-target */
typedef PREPACK struct {
a_uint16_t MessageID;
- a_uint16_t ServiceID; /* service ID of the service to connect to */
+ a_uint16_t ServiceID; /* service ID of the service to connect to */
a_uint16_t ConnectionFlags; /* connection flags */
a_uint8_t DownLinkPipeID;
a_uint8_t UpLinkPipeID;
-#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
- the host needs credits */
-#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
+#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
+ the host needs credits */
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
-
+
a_uint8_t ServiceMetaLength; /* length of meta data that follows */
a_uint8_t _Pad1;
-
+
/* service-specific meta data starts after the header */
-
+
} POSTPACK HTC_CONNECT_SERVICE_MSG;
/* connect response
typedef PREPACK struct {
a_uint16_t MessageID;
a_uint16_t ServiceID; /* service ID that the connection request was made */
- a_uint8_t Status; /* service connection status */
+ a_uint8_t Status; /* service connection status */
a_uint8_t EndpointID; /* assigned endpoint ID */
a_uint16_t MaxMsgSize; /* maximum expected message size on this endpoint */
a_uint8_t ServiceMetaLength; /* length of meta data that follows */
- a_uint8_t _Pad1;
-
+ a_uint8_t _Pad1;
+
/* service-specific meta data starts after the header */
-
+
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
typedef PREPACK struct {
* direction : host-to-target */
typedef PREPACK struct {
a_uint16_t MessageID;
- a_uint8_t PipeID; /* Pipe ID of the service to connect to */
- a_uint8_t CreditCount; /* CreditCount */
- //a_uint8_t _Pad1;
+ a_uint8_t PipeID; /* Pipe ID of the service to connect to */
+ a_uint8_t CreditCount; /* CreditCount */
+ //a_uint8_t _Pad1;
} POSTPACK HTC_CONFIG_PIPE_MSG;
/* config pipe
* direction : host-to-target */
typedef PREPACK struct {
a_uint16_t MessageID;
- a_uint8_t PipeID; /* Pipe ID of the service to connect to */
- a_uint8_t Status; /* status */
- //a_uint8_t _Pad1;
+ a_uint8_t PipeID; /* Pipe ID of the service to connect to */
+ a_uint8_t Status; /* status */
+ //a_uint8_t _Pad1;
} POSTPACK HTC_CONFIG_PIPE_RESPONSE_MSG;
/* connect response status codes */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
-#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
-#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
+#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
+#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
/* shihhung: config pipe response status code */
typedef enum {
HTC_RECORD_NULL = 0,
HTC_RECORD_CREDITS = 1,
- HTC_RECORD_LOOKAHEAD = 2,
+ HTC_RECORD_LOOKAHEAD = 2,
} HTC_RPT_IDS;
typedef PREPACK struct {
a_uint8_t Credits; /* credits to report since last report */
} POSTPACK HTC_CREDIT_REPORT;
-typedef PREPACK struct {
+typedef PREPACK struct {
a_uint8_t PreValid; /* pre valid guard */
a_uint8_t LookAhead[4]; /* 4 byte lookahead */
a_uint8_t PostValid; /* post valid guard */
-
+
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
-
+
} POSTPACK HTC_LOOKAHEAD_REPORT;
#ifndef ATH_TARGET
typedef enum {
RSVD_SERVICE_GROUP = 0,
- WMI_SERVICE_GROUP = 1,
-
+ WMI_SERVICE_GROUP = 1,
+
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
} HTC_SERVICE_GROUP_IDS;
#define HTC_LOOPBACK_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,2)
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
-#define WMI_BEACON_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
-#define WMI_CAB_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
+#define WMI_BEACON_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
+#define WMI_CAB_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_UAPSD_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_MGMT_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
#define ATH_VERSION_MAJOR 1
#define ATH_VERSION_MINOR 4
-
+
/************************** HAL configurations **************************/
#define HAL_DESC_OPTIMIZATION
#define ATH_NO_VIRTUAL_MEMORY
//#define ATH_SUPPORT_XB_ONLY
-#define ATH_SUPPORT_A_MODE
+#define ATH_SUPPORT_A_MODE
#define ATH_VERSION_MAJOR 1
#define ATH_VERSION_MINOR 4
} POSTPACK ath_mgt_hdr_t;
typedef struct _beacon_header {
- a_uint8_t vap_index;
- a_uint8_t len_changed;
+ a_uint8_t vap_index;
+ a_uint8_t len_changed;
a_uint16_t reserved;
} ath_beacon_hdr_t;
a_uint8_t ni_index;
a_uint8_t vap_index;
a_uint8_t tidno;
- a_uint32_t flags;
+ a_uint32_t flags;
a_int8_t keytype;
a_int8_t keyix;
a_uint8_t cookie;
#define VAP_TARGET_SIZE 12
-struct ieee80211vap_target
+struct ieee80211vap_target
{
a_uint8_t iv_vapindex;
a_uint8_t iv_opmode; /* enum ieee80211_opmode */
a_uint32_t ast_tx_altrate; /* tx frames with alternate rate */
a_uint32_t ast_tx_protect; /* tx frames with protection */
- a_uint32_t tx_tgt; /* tx data pkts recieved on target */
+ a_uint32_t tx_tgt; /* tx data pkts recieved on target */
a_uint32_t tx_qnull; /* txq empty occurences */
a_uint32_t txaggr_nframes; /* no. of frames aggregated */
- a_uint32_t tx_compunaggr; /* tx unaggregated frame completions */
+ a_uint32_t tx_compunaggr; /* tx unaggregated frame completions */
a_uint32_t tx_compaggr; /* tx aggregated completions */
a_uint32_t txaggr_retries; /* tx retries of sub frames */
a_uint32_t txaggr_single; /* tx frames not aggregated */
a_uint8_t tidno;
a_uint8_t aggr_enable;
a_uint8_t padding;
-};
+};
struct wmi_data_delba {
a_uint8_t ni_nodeindex;
a_uint16_t minor;
};
-#endif
+#endif
typedef PREPACK struct {
- a_int8_t rssi;
+ a_int8_t rssi;
a_uint8_t info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */
/* UP in next 3 bits - b4b3b2 */
#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03
#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
#define WMI_DATA_HDR_UP_MASK 0x07
-#define WMI_DATA_HDR_UP_SHIFT 2
+#define WMI_DATA_HDR_UP_SHIFT 2
#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
} POSTPACK WMI_DATA_HDR;
WMI_FRAME_PROBE_RESP,
WMI_FRAME_ASSOC_REQ,
WMI_FRAME_ASSOC_RESP,
- WMI_NUM_MGMT_FRAME
+ WMI_NUM_MGMT_FRAME
} WMI_MGMT_FRAME_TYPE;
/*
} DOT11_AUTH_MODE;
typedef enum {
- NONE_AUTH = 0x01,
+ NONE_AUTH = 0x01,
WPA_AUTH = 0x02,
WPA_PSK_AUTH = 0x03,
WPA2_AUTH = 0x04,
#define RX_FLIP_THRESHOLD 3 /* XXX */
-#ifdef MAGPIE_MERLIN
+#ifdef MAGPIE_MERLIN
#define MAX_TX_RATE_TBL 46
#else
#define MAX_TX_RATE_TBL 54//46
typedef struct phy_rate_ctrl {
/* 11n state */
A_UINT8 validPhyRateCount[WLAN_RC_PHY_MAX]; /* valid rate count */
- A_UINT8 validPhyRateIndex[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL]; /* index */
+ A_UINT8 validPhyRateIndex[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL]; /* index */
}PHY_STATE_CTRL;
/* per-node state */
/*
* Determines and returns the new Tx rate index.
- */
+ */
A_UINT16 rcRateFind(struct ath_softc_tgt *, struct atheros_node *,
A_UINT32 frameLen,const RATE_TABLE *pRateTable);
* used only in 20 mode. If both 20/40 bits are enabled
* then that rate can be used for both 20 and 40 mode */
-#define TRUE_20 0x2
-#define TRUE_40 0x4
+#define TRUE_20 0x2
+#define TRUE_40 0x4
#define TRUE_2040 (TRUE_20|TRUE_40)
#define TRUE_ALL_11N (TRUE_2040|TRUE)
#define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \
|| (_phy == WLAN_RC_PHY_HT_40_DS) \
|| (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \
- || (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
+ || (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
#define WLAN_RC_PHY_40(_phy) ((_phy == WLAN_RC_PHY_HT_40_SS) \
|| (_phy == WLAN_RC_PHY_HT_40_DS) \
|| (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \
- || (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
+ || (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
#define WLAN_RC_PHY_20(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS) \
|| (_phy == WLAN_RC_PHY_HT_20_DS) \
|| (_phy == WLAN_RC_PHY_HT_20_SS_HGI) \
- || (_phy == WLAN_RC_PHY_HT_20_DS_HGI))
+ || (_phy == WLAN_RC_PHY_HT_20_DS_HGI))
#define WLAN_RC_PHY_SGI(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS_HGI) \
|| (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \
|| (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \
- || (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
+ || (_phy == WLAN_RC_PHY_HT_40_DS_HGI))
#define WLAN_RC_PHY_HT(_phy) (_phy >= WLAN_RC_PHY_HT_20_SS)
#define WLAN_RC_WEP_TKIP_FLAG (0x100)
/* Index into the rate table */
-#define INIT_RATE_MAX_20 23
+#define INIT_RATE_MAX_20 23
#define INIT_RATE_MAX_40 40
/*
A_BOOL validSingleStream;/* Valid for use in rate control for single stream operation */
#ifdef MAGPIE_MERLIN
A_BOOL validSTBC; /* Valid for use in rate control for single stream operation */
-#endif
+#endif
WLAN_PHY phy; /* CCK/OFDM/TURBO/XR */
A_UINT32 rateKbps; /* Rate in Kbits per second */
A_UINT32 userRateKbps; /* User rate in KBits per second */
/*
* Determines and returns the new Tx rate index.
- */
+ */
void rcRateFind_11n(struct ath_softc_tgt *sc,
struct ath_node_target *an,
int numTries,
#include "ratectrl.h"
#include "ratectrl11n.h"
-static void ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew,
+static void ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew,
unsigned int capflag, struct ieee80211_rate *rs);
-static void ath_rate_tx_complete_11n(struct ath_softc_tgt *sc, struct ath_node_target *an,
+static void ath_rate_tx_complete_11n(struct ath_softc_tgt *sc, struct ath_node_target *an,
struct ath_tx_desc *ds,
- struct ath_rc_series rcs[], int nframes,
+ struct ath_rc_series rcs[], int nframes,
int nbad);
static void ath_rate_findrate_11n(struct ath_softc_tgt *sc,
for (i=pRc->maxValidRate-1; i > 0; i--) {
for (j=0; j <= i-1; j++) {
-#ifdef MAGPIE_MERLIN
+#ifdef MAGPIE_MERLIN
if (pRateTable->info[pRc->validRateIndex[j]].rateKbps >
pRateTable->info[pRc->validRateIndex[j+1]].rateKbps)
#else
/* Iterators for validTxRateMask */
static INLINE A_BOOL
-rcGetNextValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc,
+rcGetNextValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc,
A_UINT8 curValidTxRate, A_UINT8 *pNextIndex)
{
A_UINT8 i;
/* No more valid rates */
*pNextIndex = 0;
-
+
return FALSE;
}
static INLINE A_BOOL
-rcGetNextLowerValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc,
+rcGetNextLowerValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc,
A_UINT8 curValidTxRate, A_UINT8 *pNextIndex)
{
A_INT8 i;
return FALSE;
}
}
-
+
return TRUE;
}
-/*
- * Initialize the Valid Rate Index from valid entries in Rate Table
+/*
+ * Initialize the Valid Rate Index from valid entries in Rate Table
*/
static A_UINT8 rcSibInitValidRates(const RATE_TABLE_11N *pRateTable,
TX_RATE_CTRL *pRc,
A_UINT8 i, hi = 0;
A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1;
A_UINT8 valid;
-
+
for (i = 0; i < pRateTable->rateCount; i++) {
if (singleStream) {
valid = pRateTable->info[i].validSingleStream;
} else {
valid = pRateTable->info[i].valid;
}
-
+
if (valid == TRUE) {
A_UINT32 phy = pRateTable->info[i].phy;
- if (!rcIsValidPhyRate(phy, capflag, FALSE))
+ if (!rcIsValidPhyRate(phy, capflag, FALSE))
continue;
pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = i;
hi = A_MAX(hi, i);
}
- }
-
+ }
+
return hi;
}
-/*
- * Initialize the Valid Rate Index from Rate Set
+/*
+ * Initialize the Valid Rate Index from Rate Set
*/
static A_UINT8
rcSibSetValidRates(const RATE_TABLE_11N *pRateTable,
- TX_RATE_CTRL *pRc,
+ TX_RATE_CTRL *pRc,
struct ieee80211_rateset *pRateSet,
A_UINT32 capflag,
struct ath_node_target *an,
A_UINT8 i, j, hi = 0;
A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1;
A_UINT32 valid;
-
+
/* Use intersection of working rates and valid rates */
for (i = 0; i < pRateSet->rs_nrates; i++) {
for (j = 0; j < pRateTable->rateCount; j++) {
} else if (singleStream) {
#else
if (singleStream) {
-#endif
+#endif
valid = pRateTable->info[j].validSingleStream;
} else {
valid = pRateTable->info[j].valid;
}
-
+
/*
* We allow a rate only if its valid and the capflag matches one of
* the validity (TRUE/TRUE_20/TRUE_40) flags
*/
- if (((pRateSet->rs_rates[i] & 0x7F) ==
+ if (((pRateSet->rs_rates[i] & 0x7F) ==
(pRateTable->info[j].dot11Rate & 0x7F))
- && ((valid & WLAN_RC_CAP_MODE(capflag)) ==
+ && ((valid & WLAN_RC_CAP_MODE(capflag)) ==
WLAN_RC_CAP_MODE(capflag)) && !WLAN_RC_PHY_HT(phy)) {
- if (!rcIsValidPhyRate(phy, capflag, FALSE))
+ if (!rcIsValidPhyRate(phy, capflag, FALSE))
continue;
pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = j;
}
}
}
-
+
return hi;
}
static A_UINT8
rcSibSetValidHtRates(const RATE_TABLE_11N *pRateTable,
- TX_RATE_CTRL *pRc,
+ TX_RATE_CTRL *pRc,
A_UINT8 *pMcsSet,
A_UINT32 capflag,
struct ath_node_target *an,
A_UINT8 i, j, hi = 0;
A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1;
A_UINT8 valid;
-
+
/* Use intersection of working rates and valid rates */
for (i = 0; i < ((struct ieee80211_rateset *)pMcsSet)->rs_nrates; i++) {
for (j = 0; j < pRateTable->rateCount; j++) {
} else {
valid = pRateTable->info[j].valid;
}
-
- if (((((struct ieee80211_rateset *)pMcsSet)->rs_rates[i] & 0x7F)
- != (pRateTable->info[j].dot11Rate & 0x7F))
- || !WLAN_RC_PHY_HT(phy)
+
+ if (((((struct ieee80211_rateset *)pMcsSet)->rs_rates[i] & 0x7F)
+ != (pRateTable->info[j].dot11Rate & 0x7F))
+ || !WLAN_RC_PHY_HT(phy)
|| !WLAN_RC_PHY_HT_VALID(valid, capflag)
- || ((pRateTable->info[j].dot11Rate == 15) &&
- (valid & TRUE_20) &&
+ || ((pRateTable->info[j].dot11Rate == 15) &&
+ (valid & TRUE_20) &&
(capflag & WLAN_RC_WEP_TKIP_FLAG)) )
{
continue;
}
-
- if (!rcIsValidPhyRate(phy, capflag, FALSE))
+
+ if (!rcIsValidPhyRate(phy, capflag, FALSE))
continue;
-
+
pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = j;
pPhyStateCtrl->validPhyRateCount[phy] += 1;
struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc;
A_UINT8 *phtMcs = (A_UINT8*)&pRateSet->htrates;
TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib);
- PHY_STATE_CTRL mPhyCtrlState;
+ PHY_STATE_CTRL mPhyCtrlState;
A_UINT8 i, j, k, hi = 0, htHi = 0;
for (i = 0; i < WLAN_RC_PHY_MAX; i++) {
for (j = 0; j < MAX_TX_RATE_TBL; j++) {
mPhyCtrlState.validPhyRateIndex[i][j] = 0;
- }
+ }
mPhyCtrlState.validPhyRateCount[i] = 0;
}
pRc->rateTableSize = hi + 1;
pRc->rateMaxPhy = 0;
-
+
ASSERT(pRc->rateTableSize <= MAX_TX_RATE_TBL);
for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) {
for (j = 0; j < mPhyCtrlState.validPhyRateCount[i]; j++) {
pRc->validRateIndex[k++] = mPhyCtrlState.validPhyRateIndex[i][j];
- }
+ }
if (!rcIsValidPhyRate(i, pRateTable->initialRateMax, TRUE) ||
- !mPhyCtrlState.validPhyRateCount[i])
+ !mPhyCtrlState.validPhyRateCount[i])
continue;
- pRc->rateMaxPhy = mPhyCtrlState.validPhyRateIndex[i][j-1];
+ pRc->rateMaxPhy = mPhyCtrlState.validPhyRateIndex[i][j-1];
}
-
+
ASSERT(pRc->rateTableSize <= MAX_TX_RATE_TBL);
ASSERT(k <= MAX_TX_RATE_TBL);
minIndex = 0;
bestRate = minIndex;
-
+
/*
* Try the higher rate first. It will reduce memory moving time
* if we have very good channel characteristics.
*/
for (index = maxIndex; index >= minIndex ; index--) {
A_UINT8 perThres;
-
+
rate = pRc->validRateIndex[index];
if (rate > pRc->rateMaxPhy) {
continue;
}
/* if the best throughput is already larger than the userRateKbps..
- * then we could skip of rest of calculation..
+ * then we could skip of rest of calculation..
*/
if( bestThruput >= pRateTable->info[rate].userRateKbps)
break;
/* Probe the next allowed phy state */
/* FIXME: Check to make sure ratMax is checked properly */
- if (rcGetNextValidTxRate( pRateTable, pRc, rate, &nextRate) &&
+ if (rcGetNextValidTxRate( pRateTable, pRc, rate, &nextRate) &&
(nowMsec - pRc->probeTime > pRateTable->probeInterval) &&
(pRc->hwMaxRetryPktCnt >= 1))
{
A_BOOL rtsctsenable, A_UINT32 chainmask,int stbc)
{
series->tries = tries;
- series->flags = (rtsctsenable? ATH_RC_RTSCTS_FLAG : 0) |
- (WLAN_RC_PHY_DS(pRateTable->info[rix].phy) ? ATH_RC_DS_FLAG : 0) |
- (WLAN_RC_PHY_40(pRateTable->info[rix].phy) ? ATH_RC_CW40_FLAG : 0) |
+ series->flags = (rtsctsenable? ATH_RC_RTSCTS_FLAG : 0) |
+ (WLAN_RC_PHY_DS(pRateTable->info[rix].phy) ? ATH_RC_DS_FLAG : 0) |
+ (WLAN_RC_PHY_40(pRateTable->info[rix].phy) ? ATH_RC_CW40_FLAG : 0) |
(WLAN_RC_PHY_SGI(pRateTable->info[rix].phy) ? ATH_RC_HT40_SGI_FLAG : 0);
#ifdef MAGPIE_MERLIN
if (stbc) {
/* For now, only single stream STBC is supported */
- if (pRateTable->info[rix].rateCode >= 0x80 &&
+ if (pRateTable->info[rix].rateCode >= 0x80 &&
pRateTable->info[rix].rateCode <= 0x87)
{
series->flags |= ATH_RC_TX_STBC_FLAG;
series->max4msframelen = pRateTable->info[rix].max4msframelen;
series->txrateKbps = pRateTable->info[rix].rateKbps;
- /* If the hardware is capable of multiple transmit chains (chainmask is 3, 5 or 7),
+ /* If the hardware is capable of multiple transmit chains (chainmask is 3, 5 or 7),
* then choose the number of transmit chains dynamically based on entries in the rate table.
*/
#ifndef ATH_ENABLE_WLAN_FOR_K2
if(chainmask == 7)
series->tx_chainmask = pRateTable->info[rix].txChainMask_3ch;
- else if(chainmask == 1)
+ else if(chainmask == 1)
series->tx_chainmask = 1;
- else
+ else
series->tx_chainmask = pRateTable->info[rix].txChainMask_2ch; /*Chainmask is 3 or 5*/
#else
series->tx_chainmask = 1;
#endif
}
-static A_UINT8
-rcRateGetIndex(struct ath_softc_tgt *sc, struct ath_node_target *an,
- const RATE_TABLE_11N *pRateTable ,
+static A_UINT8
+rcRateGetIndex(struct ath_softc_tgt *sc, struct ath_node_target *an,
+ const RATE_TABLE_11N *pRateTable ,
A_UINT8 rix, A_UINT16 stepDown, A_UINT16 minRate)
{
A_UINT32 j;
A_UINT8 nextIndex;
struct atheros_node *pSib = ATH_NODE_ATHEROS(an);
TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib);
-
+
if (minRate) {
for (j = RATE_TABLE_11N_SIZE; j > 0; j-- ) {
if (rcGetNextLowerValidTxRate(pRateTable, pRc, rix, &nextIndex)) {
return rix;
}
-void rcRateFind_11n(struct ath_softc_tgt *sc, struct ath_node_target *an,
+void rcRateFind_11n(struct ath_softc_tgt *sc, struct ath_node_target *an,
int numTries, int numRates, int stepDnInc,
unsigned int rcflag, struct ath_rc_series series[], int *isProbe)
{
- A_UINT8 i = 0;
+ A_UINT8 i = 0;
A_UINT8 tryPerRate = 0;
struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc;
RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode];
A_UINT8 dot11Rate;
WLAN_PHY phy;
- rix = rcRateFind_ht(sc, asn, pRateTable, (rcflag & ATH_RC_PROBE_ALLOWED) ? 1 : 0,
+ rix = rcRateFind_ht(sc, asn, pRateTable, (rcflag & ATH_RC_PROBE_ALLOWED) ? 1 : 0,
isProbe);
nrix = rix;
/* set one try for probe rates. For the probes don't enable rts */
rcRateSetseries(pRateTable, &series[i++], 1, nrix,
FALSE, asc->tx_chainmask, asn->stbc);
-
+
/*
* Get the next tried/allowed rate. No RTS for the next series
* after the probe rate
/*
* BUG 26545:
- * Change rate series to enable aggregation when operating at lower MCS rates.
+ * Change rate series to enable aggregation when operating at lower MCS rates.
* When first rate in series is MCS2 in HT40 @ 2.4GHz, series should look like:
* {MCS2, MCS1, MCS0, MCS0}.
* When first rate in series is MCS3 in HT20 @ 2.4GHz, series should look like:
dot11Rate = pRateTable->info[rix].dot11Rate;
phy = pRateTable->info[rix].phy;
if (i == 4 &&
- ((dot11Rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) ||
- (dot11Rate == 3 && phy == WLAN_RC_PHY_HT_20_SS)))
+ ((dot11Rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) ||
+ (dot11Rate == 3 && phy == WLAN_RC_PHY_HT_20_SS)))
{
series[3].rix = series[2].rix;
series[3].flags = series[2].flags;
if (sc->sc_curmode == IEEE80211_MODE_11NG) {
dot11Rate = pRateTable->info[rix].dot11Rate;
if (dot11Rate <= 3 ) {
- series[0].flags |= ATH_RC_RTSCTS_FLAG;
+ series[0].flags |= ATH_RC_RTSCTS_FLAG;
}
}
}
static void
-rcUpdate_ht(struct ath_softc_tgt *sc, struct ath_node_target *an, int txRate,
- A_BOOL Xretries, int retries, A_UINT8 curTxAnt,
+rcUpdate_ht(struct ath_softc_tgt *sc, struct ath_node_target *an, int txRate,
+ A_BOOL Xretries, int retries, A_UINT8 curTxAnt,
A_UINT16 nFrames, A_UINT16 nBad)
{
TX_RATE_CTRL *pRc;
ASSERT(retries >= 0 && retries < MAX_TX_RETRIES);
ASSERT(txRate >= 0);
-
+
if (txRate < 0) {
return;
}
}
/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
- pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per -
+ pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per -
(pRc->state[txRate].per / 8) + ((100) / 8));
}
* of the sum of these two terms.
*/
if (nFrames > 0)
- pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per -
- (pRc->state[txRate].per / 8) +
+ pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per -
+ (pRc->state[txRate].per / 8) +
((100*(retries*nFrames + nBad)/(nFrames*(retries+1))) / 8));
} else {
/* new_PER = 7/8*old_PER + 1/8*(currentPER) */
- pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per -
+ pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per -
(pRc->state[txRate].per / 8) + (nRetry2PerLookup[retries] / 8));
}
/* For all cases */
- ASSERT((pRc->rateMaxPhy >= 0 && pRc->rateMaxPhy <= pRc->rateTableSize &&
+ ASSERT((pRc->rateMaxPhy >= 0 && pRc->rateMaxPhy <= pRc->rateTableSize &&
pRc->rateMaxPhy != INVALID_RATE_MAX));
-
+
/*
* If this rate looks bad (high PER) then stop using it for
* a while (except if we are probing).
*/
if (pRc->state[txRate].per >= 55 && txRate > 0 &&
- pRateTable->info[txRate].rateKbps <=
+ pRateTable->info[txRate].rateKbps <=
pRateTable->info[pRc->rateMaxPhy].rateKbps)
{
- rcGetNextLowerValidTxRate(pRateTable, pRc, (A_UINT8) txRate,
+ rcGetNextLowerValidTxRate(pRateTable, pRc, (A_UINT8) txRate,
&pRc->rateMaxPhy);
/* Don't probe for a little while. */
* the status of previous frames.
*/
void rcUpdate_11n(struct ath_softc_tgt *sc, struct ath_node_target *an,
- A_UINT8 curTxAnt,
+ A_UINT8 curTxAnt,
int finalTSIdx, int Xretries,
- struct ath_rc_series rcs[], int nFrames,
+ struct ath_rc_series rcs[], int nFrames,
int nBad, int long_retry)
{
A_UINT32 series = 0;
if (rcs[series].tries != 0) {
flags = rcs[series].flags;
/* If HT40 and we have switched mode from 40 to 20 => don't update */
- if ((flags & ATH_RC_CW40_FLAG) &&
+ if ((flags & ATH_RC_CW40_FLAG) &&
(pRc->rcPhyMode != (flags & ATH_RC_CW40_FLAG))) {
return;
}
}
/* FIXME:XXXX, too many args! */
- rcUpdate_ht(sc, an, rix, Xretries? 1 : 2, rcs[series].tries,
+ rcUpdate_ht(sc, an, rix, Xretries? 1 : 2, rcs[series].tries,
curTxAnt, nFrames, nFrames);
}
}
flags = rcs[series].flags;
/* If HT40 and we have switched mode from 40 to 20 => don't update */
- if ((flags & ATH_RC_CW40_FLAG) &&
+ if ((flags & ATH_RC_CW40_FLAG) &&
(pRc->rcPhyMode != (flags & ATH_RC_CW40_FLAG))) {
return;
}
}
/* FIXME:XXXX, too many args! */
- rcUpdate_ht(sc, an, rix, Xretries, long_retry, curTxAnt,
+ rcUpdate_ht(sc, an, rix, Xretries, long_retry, curTxAnt,
nFrames, nBad);
}
ar5416AttachRateTables(asc);
asc->tx_chainmask = 1;
-
+
return &asc->arc;
}
ath_rate_tx_complete(struct ath_softc_tgt *sc,
struct ath_node_target *an,
struct ath_tx_desc *ds,
- struct ath_rc_series rcs[],
+ struct ath_rc_series rcs[],
int nframes, int nbad)
{
ath_rate_tx_complete_11n(sc, an, ds, rcs, nframes, nbad);
}
void
-ath_rate_newassoc(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew,
+ath_rate_newassoc(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew,
unsigned int capflag, struct ieee80211_rate *rs)
{
ath_rate_newassoc_11n(sc, an, isnew, capflag, rs);
{
struct ieee80211_node_target *ni = &an->ni;
- ath_rate_newassoc(sc, ATH_NODE_TARGET(ni), isnew, capflag, rs);
+ ath_rate_newassoc(sc, ATH_NODE_TARGET(ni), isnew, capflag, rs);
}
static int init_ath_rate_atheros(void);
ath_rate_tx_complete_11n(struct ath_softc_tgt *sc,
struct ath_node_target *an,
struct ath_tx_desc *ds,
- struct ath_rc_series rcs[],
+ struct ath_rc_series rcs[],
int nframes, int nbad)
{
int finalTSIdx = ds->ds_txstat.ts_rate;
int tx_status = 0;
if ((ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) ||
- (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) ||
+ (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) ||
(ds->ds_txstat.ts_flags & HAL_TX_DATA_UNDERRUN) ||
(ds->ds_txstat.ts_flags & HAL_TX_DELIM_UNDERRUN)) {
tx_status = 1;
}
static void
-ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew,
+ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew,
unsigned int capflag, struct ieee80211_rate *rs)
{
if (isnew) {
projects / open-ath9k-htc-firmware.git / commitdiff