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3c5a450)
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
/* Synthesizer off + RX off */
bank3 = 0x00400018;
/* Synthesizer off + RX off */
bank3 = 0x00400018;
- clock_set(true, AHB_20_22MHZ);
+ clock_set(AHB_20_22MHZ, false);
} else {
/* advance to the next PSM step */
fw.phy.psm.state--;
} else {
/* advance to the next PSM step */
fw.phy.psm.state--;
bank3 = 0x01420098;
if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
bank3 = 0x01420098;
if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
- clock_set(true, AHB_80_88MHZ);
+ clock_set(AHB_80_88MHZ, true);
- clock_set(true, AHB_40_44MHZ);
+ clock_set(AHB_40_44MHZ, true);
AR9170_PWR_RESET_WLAN_MASK);
set(AR9170_PWR_REG_RESET, 0x0);
AR9170_PWR_RESET_WLAN_MASK);
set(AR9170_PWR_REG_RESET, 0x0);
- set(AR9170_PWR_REG_CLOCK_SEL, AHB_40MHZ_OSC);
+ clock_set(AHB_20_22MHZ, false);
set(AR9170_PWR_REG_PLL_ADDAC, 0x5163); /* 0x502b; */
set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO);
set(AR9170_PWR_REG_PLL_ADDAC, 0x5163); /* 0x502b; */
set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO);