void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
-/*************/
-/* Utilities */
-/*************/
-
-#undef adf_os_cpu_to_le16
-
-static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
-{
- return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
-}
-
/*
* Extend a 32 bit TSF to 64 bit, taking wrapping into account.
*/
ds->ds_link = 0;
adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
- ath_hal_setuprxdesc(ah, ds,
- adf_nbuf_tailroom(ds->ds_nbuf),
- 0);
+ ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
if (sc->sc_rxlink == NULL) {
ah->ah_setRxDP(ah, ds->ds_daddr);
continue;
}
- retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr,
+ retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
if (HAL_EINPROGRESS == retval) {
break;
} while(1);
sc->sc_imask |= HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
}
/*******************/
rt = sc->sc_currates;
rate = rt->info[rix].rateCode;
- ath_hal_setuptxdesc(ah, ds
+ ah->ah_setupTxDesc(ds
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, sizeof(struct ieee80211_frame)
, HAL_PKT_TYPE_BEACON
, MAX_RATE_POWER
, rate, 1
, HAL_TXKEYIX_INVALID
- , 0
, flags
, 0
- , 0
- , 0
- , 0
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , 0);
- ath_hal_filltxdesc(ah, ds
+ ah->ah_fillTxDesc(ds
, asf_roundup(adf_nbuf_len(skb), 4)
, AH_TRUE
, AH_TRUE
series[0].Rate = rate;
series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
series[0].RateFlags = 0;
- ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0);
+ ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
}
static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
status &= sc->sc_imask;
if (status & HAL_INT_FATAL) {
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
} else {
if (status & HAL_INT_SWBA) {
ath_uapsd_processtriggers(sc);
sc->sc_imask &= ~HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
}
sc->sc_imask |= HAL_INT_BMISS;
}
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
sc->sc_imask |= HAL_INT_GTT;
- if (ath_hal_htsupported(ah))
+ if (ath_hal_getcapability(ah, HAL_CAP_HT))
sc->sc_imask |= HAL_INT_CST;
adf_os_setup_intr(sc->sc_dev, ath_intr);
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
t = (struct registerWrite *)(data+i);
if( t->reg > 0xffff ) {
- a_uint32_t *pReg = (a_uint32_t *)t->reg;
-
- *pReg = t->val;
-
+ HAL_WORD_REG_WRITE(t->reg, t->val);
#if defined(PROJECT_K2)
if( t->reg == 0x50040 ) {
static uint8_t flg=0;
#if defined(PROJECT_K2)
if( t->reg == 0x7014 ) {
static uint8_t resetPLL = 0;
- a_uint32_t *pReg;
if( resetPLL == 0 ) {
- t->reg = 0x50044;
- pReg = (a_uint32_t *)t->reg;
- *pReg = 0;
+ /* here we write to core register */
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ /* and here to mac register */
ath_hal_reg_write_target(ah, 0x786c,
ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
ath_hal_reg_write_target(ah, 0x786c,
ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
- *pReg = 0x20;
+
+ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
resetPLL = 1;
}
- t->reg = 0x7014;
}
#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
if( t->reg == 0x7014 ){
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
ath_tgt_txq_setup(sc);
sc->sc_imask =0;
- ath_hal_intrset(ah,0);
+ ah->ah_setInterrupts(ah, 0);
return 0;
bad: