+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Qualcomm Atheros nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
/*
* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2005 Atheros Communications, Inc.
halChanHalfRate : 1,
halChanQuarterRate : 1,
halHTSupport : 1,
- halRxStbcSupport : 1,
- halTxStbcSupport : 1,
halGTTSupport : 1,
halFastCCSupport : 1,
halExtChanDfsSupport : 1,
#define SM(_v, _f) (((_v) << _f##_S) & _f)
#define MS(_v, _f) (((_v) & _f) >> _f##_S)
#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
- OS_REG_WRITE(_a, _r, \
- (OS_REG_READ(_a, _r) &~ _f) | (((_v) << _f##_S) & _f))
+ iowrite32_mac(_r, \
+ (ioread32_mac(_r) & ~_f) \
+ | (((_v) << _f##_S) & _f))
#define OS_REG_RMW(_a, _r, _set, _clr) \
- OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
+ iowrite32_mac(_r, \
+ (ioread32_mac(_r) & ~(_clr)) | (_set))
#define OS_REG_SET_BIT(_a, _r, _f) \
- OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | _f)
+ iowrite32_mac(_r, ioread32_mac(_r) | _f)
#define OS_REG_CLR_BIT(_a, _r, _f) \
- OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ _f)
+ iowrite32_mac(_r, ioread32_mac(_r) & ~_f)
/* wait for the register contents to have the specified value */
extern HAL_BOOL ath_hal_wait(struct ath_hal *, a_uint32_t reg,
a_uint32_t mask, a_uint32_t val);
-extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list);
-
/* allocate and free memory */
extern void *ath_hal_malloc(size_t);
extern void ath_hal_free(void *);
* this routine to support chip-specific capabilities.
*/
extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
- HAL_CAPABILITY_TYPE type, a_uint32_t capability,
- a_uint32_t *result);
+ HAL_CAPABILITY_TYPE type);
extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
HAL_CAPABILITY_TYPE type, a_uint32_t capability,
a_uint32_t setting, HAL_STATUS *status);