Merge pull request #57 from olerem/io_clean-2014.05.23

[open-ath9k-htc-firmware.git] / target_firmware / magpie_fw_dev / target / cmnos / cmnos_sflash.c

diff --git a/target_firmware/magpie_fw_dev/target/cmnos/cmnos_sflash.c b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_sflash.c
index 8fc81fe23b984544fd9e6bf25e2b30329b0b5149..1d02293a4df83caf2697e71eab87d5f02bdb2cea 100755 (executable)
--- a/target_firmware/magpie_fw_dev/target/cmnos/cmnos_sflash.c
+++ b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_sflash.c
@@ -1,8 +1,44 @@
+/*
+ * Copyright (c) 2013 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of Qualcomm Atheros nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 #include "sys_cfg.h"
 #include "athos_api.h"
 
 #if SYSTEM_MODULE_SFLASH
 
+#include "adf_os_io.h"
+
 #include "reg_defs.h"
 #include "sflash_api.h"
 
@@ -362,7 +398,7 @@ _cmnos_sflash_WaitTillTransactionOver(void)
 
     do
     {
-        poldata = HAL_WORD_REG_READ(SPI_CS_ADDRESS);
+        poldata = ioread32(SPI_CS_ADDRESS);
 
         flg = SPI_CS_BUSY_GET(poldata);
     } while (flg != 0x0);
@@ -372,20 +408,18 @@ _cmnos_sflash_WaitTillTransactionOver(void)
 LOCAL void
 _cmnos_sflash_WaitTillNotWriteInProcess(void)
 {
-    A_UINT32        poldata;
     A_UINT32        flg;
 
     do
     {
         _cmnos_sflash_WaitTillTransactionOver();
 
-        HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) );
-        HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) );
+        iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR));
+        iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1));
 
         _cmnos_sflash_WaitTillTransactionOver();
 
-        poldata = HAL_WORD_REG_READ(SPI_D_ADDRESS);
-        flg = poldata & ZM_SFLASH_STATUS_REG_WIP;
+        flg = ioread32(SPI_D_ADDRESS) & ZM_SFLASH_STATUS_REG_WIP;
 
     } while (flg != 0x0);
 }
@@ -398,8 +432,8 @@ _cmnos_sflash_WriteEnable()
 {
     _cmnos_sflash_WaitTillNotWriteInProcess();
 
-    HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN) );
-    HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
+    iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN));
+    iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
 
     _cmnos_sflash_WaitTillTransactionOver();
 }
@@ -411,7 +445,7 @@ LOCAL void
 cmnos_sflash_init(void)
 {
     /* Switch the function of I/O pin 19~22 to act as SPI pins */
-    HAL_WORD_REG_WRITE( MAGPIE_REG_CLOCK_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_CLOCK_CTRL_ADDR)|BIT8 );
+       io32_set(MAGPIE_REG_CLOCK_CTRL_ADDR, BIT8);
 
     /* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail :
      *    The designers reached an conclusion that the spi master (the apb_spi interface control) will be
@@ -421,7 +455,7 @@ cmnos_sflash_init(void)
      */
 
     /* Force SPI address size to 24 bits */
-    HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2) );
+    iowrite32(SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2));
 }
 
 /************************************************************************/
@@ -452,8 +486,8 @@ cmnos_sflash_erase(A_UINT32 erase_type, A_UINT32 addr)
     _cmnos_sflash_WriteEnable();
     _cmnos_sflash_WaitTillNotWriteInProcess();
 
-    HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr) );
-    HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
+    iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr));
+    iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
 
 #if 0
     /* Do not wait(let it be completed in background) */
@@ -507,9 +541,9 @@ cmnos_sflash_program(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf)
         _cmnos_sflash_WriteEnable();
         _cmnos_sflash_WaitTillNotWriteInProcess();
 
-        HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr) );
-        HAL_WORD_REG_WRITE( SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data) );
-        HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) );
+        iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr));
+        iowrite32(SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data));
+        iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1));
 
         _cmnos_sflash_WaitTillTransactionOver();
 
@@ -552,8 +586,8 @@ cmnos_sflash_read(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf)
 
         _cmnos_sflash_WaitTillNotWriteInProcess();
 
-        HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4) );
-        HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1) );
+        iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4));
+        iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1));
 
         _cmnos_sflash_WaitTillTransactionOver();
 
@@ -571,12 +605,12 @@ cmnos_sflash_rdsr(void)
 
     _cmnos_sflash_WaitTillTransactionOver();
 
-    HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) );
-    HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) );
+    iowrite32(SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR));
+    iowrite32(SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1));
 
     _cmnos_sflash_WaitTillTransactionOver();
 
-    word_data = HAL_WORD_REG_READ(SPI_D_ADDRESS) & 0x000000FF;
+    word_data = ioread32(SPI_D_ADDRESS) & 0x000000FF;
 
     return word_data;
 }