carl9170 firmware: remove usb transport watchdog
[carl9170fw.git] / include / shared / hw.h
index fa40ebdfc55366a26121bd961ab1b691f5d6295a..30b19a7ef312968fb95525dbd0938113d9a55b3a 100644 (file)
 
 #define        AR9170_MAC_REG_DMA_TXQX_ADDR_CURR       (AR9170_MAC_REG_BASE + 0xdc0)
 
-#define        AR9170_PWR_REG_BASE                     0x1d4000
-
-#define AR9170_PWR_REG_POWER_STATE             (AR9170_PWR_REG_BASE + 0x000)
-
-#define        AR9170_PWR_REG_ADDA_BB                  (AR9170_PWR_REG_BASE + 0x004)
-#define                AR9170_PWR_ADDA_BB_USB_FIFO_RESET       0x00000005
-#define                AR9170_PWR_ADDA_BB_COLD_RESET           0x00000800
-#define                AR9170_PWR_ADDA_BB_WARM_RESET           0x00000400
-
-#define        AR9170_PWR_REG_CLOCK_SEL                (AR9170_PWR_REG_BASE + 0x008)
-#define                AR9170_PWR_CLK_AHB_40MHZ                0
-#define                AR9170_PWR_CLK_AHB_20_22MHZ             1
-#define                AR9170_PWR_CLK_AHB_40_44MHZ             2
-#define                AR9170_PWR_CLK_AHB_80_88MHZ             3
-#define                AR9170_PWR_CLK_DAC_160_INV_DLY          0x70
-
-#define        AR9170_PWR_REG_CHIP_REVISION            (AR9170_PWR_REG_BASE + 0x010)
-#define AR9170_PWR_REG_PLL_ADDAC               (AR9170_PWR_REG_BASE + 0x014)
-#define        AR9170_PWR_REG_WATCH_DOG_MAGIC          (AR9170_PWR_REG_BASE + 0x020)
-
 /* Random number generator */
 #define        AR9170_RAND_REG_BASE                    0x1d0000
 
 #define        AR9170_INT_REG_FIQ_ENCODE               (AR9170_INT_REG_BASE + 0x020)
 #define        AR9170_INT_INT_IRQ_ENCODE               (AR9170_INT_REG_BASE + 0x024)
 
+/* Power Management */
+#define        AR9170_PWR_REG_BASE                     0x1d4000
+
+#define AR9170_PWR_REG_POWER_STATE             (AR9170_PWR_REG_BASE + 0x000)
+
+#define        AR9170_PWR_REG_RESET                    (AR9170_PWR_REG_BASE + 0x004)
+#define                AR9170_PWR_RESET_COMMIT_RESET_MASK      BIT(0)
+#define                AR9170_PWR_RESET_WLAN_MASK              BIT(1)
+#define                AR9170_PWR_RESET_DMA_MASK               BIT(2)
+#define                AR9170_PWR_RESET_BRIDGE_MASK            BIT(3)
+#define                AR9170_PWR_RESET_AHB_MASK               BIT(9)
+#define                AR9170_PWR_RESET_BB_WARM_RESET          BIT(10)
+#define                AR9170_PWR_RESET_BB_COLD_RESET          BIT(11)
+#define                AR9170_PWR_RESET_ADDA_CLK_COLD_RESET    BIT(12)
+#define                AR9170_PWR_RESET_PLL                    BIT(13)
+#define                AR9170_PWR_RESET_USB_PLL                BIT(14)
+
+#define        AR9170_PWR_REG_CLOCK_SEL                (AR9170_PWR_REG_BASE + 0x008)
+#define                AR9170_PWR_CLK_AHB_40MHZ                0
+#define                AR9170_PWR_CLK_AHB_20_22MHZ             1
+#define                AR9170_PWR_CLK_AHB_40_44MHZ             2
+#define                AR9170_PWR_CLK_AHB_80_88MHZ             3
+#define                AR9170_PWR_CLK_DAC_160_INV_DLY          0x70
+
+#define        AR9170_PWR_REG_CHIP_REVISION            (AR9170_PWR_REG_BASE + 0x010)
+#define AR9170_PWR_REG_PLL_ADDAC               (AR9170_PWR_REG_BASE + 0x014)
+#define        AR9170_PWR_REG_WATCH_DOG_MAGIC          (AR9170_PWR_REG_BASE + 0x020)
+
 /* Faraday USB Controller */
 #define        AR9170_USB_REG_BASE                     0x1e1000