uint32_t wrdata;
uint32_t ret;
-#define AGC_CAL_NF (AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF);
+#define AGC_CAL_NF (AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF)
wrdata = get_async(AR9170_PHY_REG_AGC_CONTROL) | AGC_CAL_NF;
set(AR9170_PHY_REG_AGC_CONTROL, wrdata);
ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
/* sitesurvey : 100 ms / current connected 200 ms */
- while (loop && ret != 0x0) {
- ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
-
- if (ret == 0)
- break;
-
+ while ((ret != 0) && loop--) {
udelay(100);
- loop--;
+
+ ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
}
/* return the AGC/Noise calibration state to the driver */
set(AR9170_PHY_REG_ANALOG_SWAP, AR9170_PHY_ANALOG_SWAP_AB |
AR9170_PHY_ANALOG_SWAP_ALT_CHAIN);
- /* configure mask */
- set(AR9170_PHY_REG_RX_CHAINMASK, 0x5); /* chain 0 + chain 2 */
- set(AR9170_PHY_REG_CAL_CHAINMASK, 0x5); /* chain 0 + chain 2 */
-
/* Activate BB */
set(AR9170_PHY_REG_ACTIVE, AR9170_PHY_ACTIVE_EN);
delay(10);
fw.phy.frequency = cmd->rf_init.freq;
if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
- clock_set(true, AHB_80_88MHZ);
+ clock_set(AHB_80_88MHZ, true);
else
- clock_set(true, AHB_40_44MHZ);
+ clock_set(AHB_40_44MHZ, true);
ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),
resp->hdr.len = sizeof(struct carl9170_rf_init_result);
resp->rf_init_res.ret = cpu_to_le32(ret);
-
- resp->rf_init_res.regs[0] = get(AR9170_PHY_REG_CCA);
- resp->rf_init_res.regs[3] = get(AR9170_PHY_REG_EXT_CCA);
-
- resp->rf_init_res.regs[1] = get(AR9170_PHY_REG_CH1_CCA);
- resp->rf_init_res.regs[4] = get(AR9170_PHY_REG_CH1_EXT_CCA);
-
- resp->rf_init_res.regs[2] = get(AR9170_PHY_REG_CH2_CCA);
- resp->rf_init_res.regs[5] = get(AR9170_PHY_REG_CH2_EXT_CCA);
}
#ifdef CONFIG_CARL9170FW_PSM