#endif /* CONFIG_CARL9170FW_DELAYED_TX */
#ifdef CONFIG_CARL9170FW_CAB_QUEUE
-#define AR9170_TERMINATOR_NUMBER_CAB 1
+#define AR9170_TERMINATOR_NUMBER_CAB CARL9170_INTF_NUM
#else
#define AR9170_TERMINATOR_NUMBER_CAB 0
#endif /* CONFIG_CARL9170FW_CAB_QUEUE */
* 0x18000
*/
-#define AR9170_SRAM_SIZE 0x18000
#define CARL9170_SRAM_RESERVED (sizeof(struct carl9170_sram_reserved))
#define AR9170_FRAME_MEMORY_SIZE (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
extern struct ar9170_dma_memory dma_mem;
-#define AR9170_DOWN_BLOCK_RATIO 2
-#define AR9170_RX_BLOCK_RATIO 1
+#define AR9170_DOWN_BLOCK_RATIO 2
+#define AR9170_RX_BLOCK_RATIO 1
/* Tx 16*2 = 32 packets => 32*(5*320) */
-#define AR9170_TX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
- (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
-#define AR9170_RX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
+#define AR9170_TX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
+ (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
+#define AR9170_RX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
/* Error code */
-#define AR9170_ERR_FS_BIT 1
-#define AR9170_ERR_LS_BIT 2
-#define AR9170_ERR_OWN_BITS 3
-#define AR9170_ERR_DATA_SIZE 4
-#define AR9170_ERR_TOTAL_LEN 5
-#define AR9170_ERR_DATA 6
-#define AR9170_ERR_SEQ 7
-#define AR9170_ERR_LEN 8
+#define AR9170_ERR_FS_BIT 1
+#define AR9170_ERR_LS_BIT 2
+#define AR9170_ERR_OWN_BITS 3
+#define AR9170_ERR_DATA_SIZE 4
+#define AR9170_ERR_TOTAL_LEN 5
+#define AR9170_ERR_DATA 6
+#define AR9170_ERR_SEQ 7
+#define AR9170_ERR_LEN 8
/* Status bits definitions */
/* Own bits definitions */
-#define AR9170_OWN_BITS_MASK 0x3
-#define AR9170_OWN_BITS_SW 0x0
-#define AR9170_OWN_BITS_HW 0x1
-#define AR9170_OWN_BITS_SE 0x2
+#define AR9170_OWN_BITS 0x3
+#define AR9170_OWN_BITS_S 0
+#define AR9170_OWN_BITS_SW 0x0
+#define AR9170_OWN_BITS_HW 0x1
+#define AR9170_OWN_BITS_SE 0x2
/* Control bits definitions */
#define AR9170_CTRL_TXFAIL 1
#define AR9170_CTRL_BAFAIL 2
-#define AR9170_CTRL_FAIL_MASK (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
+#define AR9170_CTRL_FAIL (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
/* First segament bit */
-#define AR9170_CTRL_LS_BIT 0x100
+#define AR9170_CTRL_LS_BIT 0x100
/* Last segament bit */
-#define AR9170_CTRL_FS_BIT 0x200
+#define AR9170_CTRL_FS_BIT 0x200
struct dma_queue {
struct dma_desc *head;
void queue_dump(void);
void wlan_txq_hangfix(const unsigned int queue);
+static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
+{
+ return q->terminator == desc;
+}
+
static inline __inline bool queue_empty(struct dma_queue *q)
{
return q->head == q->terminator;
{
struct dma_desc *desc = NULL;
- if ((q->head->status & AR9170_OWN_BITS_MASK) == bits)
+ if ((q->head->status & AR9170_OWN_BITS) == bits)
desc = dma_unlink_head(q);
return desc;
struct dma_desc *desc = NULL;
/* AR9170_OWN_BITS_HW will be filtered out here too. */
- if ((q->head->status & AR9170_OWN_BITS_MASK) != bits)
+ if ((q->head->status & AR9170_OWN_BITS) != bits)
desc = dma_unlink_head(q);
return desc;
#define __for_each_desc_bits(desc, queue, bits) \
for (desc = (queue)->head; \
(desc != (queue)->terminator && \
- (desc->status & AR9170_OWN_BITS_MASK) == bits); \
+ (desc->status & AR9170_OWN_BITS) == bits); \
desc = desc->lastAddr->nextAddr)
#define __while_desc_bits(desc, queue, bits) \
for (desc = (queue)->head; \
(!queue_empty(queue) && \
- (desc->status & AR9170_OWN_BITS_MASK) == bits); \
+ (desc->status & AR9170_OWN_BITS) == bits); \
desc = (queue)->head)
#define __for_each_desc(desc, queue) \
static inline __inline void dma_rearm(struct dma_desc *desc)
{
/* Set OWN bit to HW */
- desc->status = ((desc->status & (~AR9170_OWN_BITS_MASK)) |
+ desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
AR9170_OWN_BITS_HW);
}