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carl9170 firmware: 5/10 MHz Channel Support for carl9170
[carl9170fw.git]
/
carlfw
/
src
/
rf.c
diff --git
a/carlfw/src/rf.c
b/carlfw/src/rf.c
index e031dd8ee4d1f84e7fa3570dbd8c1e6f6c8b56fb..152aac59f5be225600e6b5cd081c1fb9cb9e31e6 100644
(file)
--- a/
carlfw/src/rf.c
+++ b/
carlfw/src/rf.c
@@
-197,18
+197,19
@@
static uint32_t rf_init(const uint32_t delta_slope_coeff_exp,
void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
{
void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
{
- uint32_t ret;
+ uint32_t ret
, div
;
- fw.phy.
ht_settings = cmd->rf_init.ht_
settings;
+ fw.phy.
settings = cmd->rf_init.
settings;
fw.phy.frequency = cmd->rf_init.freq;
fw.phy.frequency = cmd->rf_init.freq;
+ div = GET_VAL(CARL9170FW_PHY_RF_DIV, fw.phy.settings);
/*
* Is the clock controlled by the PHY?
*/
/*
* Is the clock controlled by the PHY?
*/
- if ((fw.phy.
ht_
settings & EIGHTY_FLAG) == EIGHTY_FLAG)
- clock_set(AHB_80_88MHZ, true);
+ if ((fw.phy.settings & EIGHTY_FLAG) == EIGHTY_FLAG)
+ clock_set(AHB_80_88MHZ, true
, div
);
else
else
- clock_set(AHB_40_44MHZ, true);
+ clock_set(AHB_40_44MHZ, true
, div
);
ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),
ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),