#define AR9170_PWR_CLK_AHB_20_22MHZ 1
#define AR9170_PWR_CLK_AHB_40_44MHZ 2
#define AR9170_PWR_CLK_AHB_80_88MHZ 3
+#define AR9170_PWR_CLK_ADDAC_CLK160 (BIT(2) | (BIT(3))
+#define AR9170_PWR_CLK_ADDAC_CLK160_S 2
#define AR9170_PWR_CLK_DAC_160_INV_DLY 0x70
#define AR9170_PWR_REG_CHIP_REVISION (AR9170_PWR_REG_BASE + 0x010)