2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
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22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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35 #ifndef __XLP_HAL_UART_H__
36 #define __XLP_HAL_UART_H__
38 /* UART Specific registers */
39 #define UART_RX_DATA 0x00
40 #define UART_TX_DATA 0x00
42 #define UART_INT_EN 0x01
43 #define UART_INT_ID 0x02
44 #define UART_FIFO_CTL 0x02
45 #define UART_LINE_CTL 0x03
46 #define UART_MODEM_CTL 0x04
47 #define UART_LINE_STS 0x05
48 #define UART_MODEM_STS 0x06
50 #define UART_DIVISOR0 0x00
51 #define UART_DIVISOR1 0x01
53 #define BASE_BAUD (XLP_IO_CLK/16)
54 #define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
57 #define LCR_5BITS 0x00
58 #define LCR_6BITS 0x01
59 #define LCR_7BITS 0x02
60 #define LCR_8BITS 0x03
61 #define LCR_STOPB 0x04
62 #define LCR_PENAB 0x08
64 #define LCR_PEVEN 0x10
66 #define LCR_PZERO 0x30
67 #define LCR_SBREAK 0x40
68 #define LCR_EFR_ENABLE 0xbf
76 #define MCR_LOOPBACK 0x10
79 #define FCR_RCV_RST 0x02
80 #define FCR_XMT_RST 0x04
81 #define FCR_RX_LOW 0x00
82 #define FCR_RX_MEDL 0x40
83 #define FCR_RX_MEDH 0x80
84 #define FCR_RX_HIGH 0xc0
87 #define IER_ERXRDY 0x1
88 #define IER_ETXRDY 0x2
92 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
94 #define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95 #define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96 #define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \
98 XLP_IO_UART_OFFSET(node, inst))
99 #define nlm_get_uart_regbase(node, inst) \
100 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
103 nlm_uart_set_baudrate(uint64_t base, int baud)
107 lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
109 /* enable divisor register, and write baud values */
110 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
111 nlm_write_uart_reg(base, UART_DIVISOR0,
112 (BAUD_DIVISOR(baud) & 0xff));
113 nlm_write_uart_reg(base, UART_DIVISOR1,
114 ((BAUD_DIVISOR(baud) >> 8) & 0xff));
116 /* restore default lcr */
117 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
121 nlm_uart_outbyte(uint64_t base, char c)
126 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
131 nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
135 nlm_uart_inbyte(uint64_t base)
140 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
141 if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
145 if (lsr & 0x01) { /* Rx data */
146 data = nlm_read_uart_reg(base, UART_RX_DATA);
155 nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
156 int parity, int int_en, int loopback)
163 else if (databits == 7)
165 else if (databits == 6)
175 /* setup default lcr */
176 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
178 /* Reset the FIFOs */
179 nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
181 nlm_uart_set_baudrate(base, baud);
184 nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
187 nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
191 #endif /* !LOCORE && !__ASSEMBLY__ */
192 #endif /* __XLP_HAL_UART_H__ */