xilinx/xdma-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.
   4  * Copyright (C) 2022, Advanced Micro Devices, Inc.
   5  */
   6
   7 #ifndef __DMA_XDMA_REGS_H
   8 #define __DMA_XDMA_REGS_H
   9
  10 /* The length of register space exposed to host */
  11 #define XDMA_REG_SPACE_LEN      65536
  12
  13 /*
  14  * maximum number of DMA channels for each direction:
  15  * Host to Card (H2C) or Card to Host (C2H)
  16  */
  17 #define XDMA_MAX_CHANNELS       4
  18
  19 /*
  20  * macros to define the number of descriptor blocks can be used in one
  21  * DMA transfer request.
  22  * the DMA engine uses a linked list of descriptor blocks that specify the
  23  * source, destination, and length of the DMA transfers.
  24  */
  25 #define XDMA_DESC_BLOCK_NUM             BIT(7)
  26 #define XDMA_DESC_BLOCK_MASK            (XDMA_DESC_BLOCK_NUM - 1)
  27
  28 /* descriptor definitions */
  29 #define XDMA_DESC_ADJACENT              32
  30 #define XDMA_DESC_ADJACENT_MASK         (XDMA_DESC_ADJACENT - 1)
  31 #define XDMA_DESC_ADJACENT_BITS         GENMASK(13, 8)
  32 #define XDMA_DESC_MAGIC                 0xad4bUL
  33 #define XDMA_DESC_MAGIC_BITS            GENMASK(31, 16)
  34 #define XDMA_DESC_FLAGS_BITS            GENMASK(7, 0)
  35 #define XDMA_DESC_STOPPED               BIT(0)
  36 #define XDMA_DESC_COMPLETED             BIT(1)
  37 #define XDMA_DESC_BLEN_BITS             28
  38 #define XDMA_DESC_BLEN_MAX              (BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE)
  39
  40 /* macros to construct the descriptor control word */
  41 #define XDMA_DESC_CONTROL(adjacent, flag)                               \
  42         (FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) |            \
  43          FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) |          \
  44          FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag)))
  45 #define XDMA_DESC_CONTROL_LAST                                          \
  46         XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED)
  47 #define XDMA_DESC_CONTROL_CYCLIC                                        \
  48         XDMA_DESC_CONTROL(1, XDMA_DESC_COMPLETED)
  49
  50 /*
  51  * Descriptor for a single contiguous memory block transfer.
  52  *
  53  * Multiple descriptors are linked by means of the next pointer. An additional
  54  * extra adjacent number gives the amount of extra contiguous descriptors.
  55  *
  56  * The descriptors are in root complex memory, and the bytes in the 32-bit
  57  * words must be in little-endian byte ordering.
  58  */
  59 struct xdma_hw_desc {
  60         __le32          control;
  61         __le32          bytes;
  62         __le64          src_addr;
  63         __le64          dst_addr;
  64         __le64          next_desc;
  65 };
  66
  67 #define XDMA_DESC_SIZE          sizeof(struct xdma_hw_desc)
  68 #define XDMA_DESC_BLOCK_SIZE    (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
  69 #define XDMA_DESC_BLOCK_ALIGN   4096
  70
  71 /*
  72  * Channel registers
  73  */
  74 #define XDMA_CHAN_IDENTIFIER            0x0
  75 #define XDMA_CHAN_CONTROL               0x4
  76 #define XDMA_CHAN_CONTROL_W1S           0x8
  77 #define XDMA_CHAN_CONTROL_W1C           0xc
  78 #define XDMA_CHAN_STATUS                0x40
  79 #define XDMA_CHAN_COMPLETED_DESC        0x48
  80 #define XDMA_CHAN_ALIGNMENTS            0x4c
  81 #define XDMA_CHAN_INTR_ENABLE           0x90
  82 #define XDMA_CHAN_INTR_ENABLE_W1S       0x94
  83 #define XDMA_CHAN_INTR_ENABLE_W1C       0x9c
  84
  85 #define XDMA_CHAN_STRIDE        0x100
  86 #define XDMA_CHAN_H2C_OFFSET    0x0
  87 #define XDMA_CHAN_C2H_OFFSET    0x1000
  88 #define XDMA_CHAN_H2C_TARGET    0x0
  89 #define XDMA_CHAN_C2H_TARGET    0x1
  90
  91 /* macro to check if channel is available */
  92 #define XDMA_CHAN_MAGIC         0x1fc0
  93 #define XDMA_CHAN_CHECK_TARGET(id, target)              \
  94         (((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target))
  95
  96 /* bits of the channel control register */
  97 #define CHAN_CTRL_RUN_STOP                      BIT(0)
  98 #define CHAN_CTRL_IE_DESC_STOPPED               BIT(1)
  99 #define CHAN_CTRL_IE_DESC_COMPLETED             BIT(2)
 100 #define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH        BIT(3)
 101 #define CHAN_CTRL_IE_MAGIC_STOPPED              BIT(4)
 102 #define CHAN_CTRL_IE_IDLE_STOPPED               BIT(6)
 103 #define CHAN_CTRL_IE_READ_ERROR                 GENMASK(13, 9)
 104 #define CHAN_CTRL_IE_DESC_ERROR                 GENMASK(23, 19)
 105 #define CHAN_CTRL_NON_INCR_ADDR                 BIT(25)
 106 #define CHAN_CTRL_POLL_MODE_WB                  BIT(26)
 107
 108 #define CHAN_CTRL_START (CHAN_CTRL_RUN_STOP |                           \
 109                          CHAN_CTRL_IE_DESC_STOPPED |                    \
 110                          CHAN_CTRL_IE_DESC_COMPLETED |                  \
 111                          CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |             \
 112                          CHAN_CTRL_IE_MAGIC_STOPPED |                   \
 113                          CHAN_CTRL_IE_READ_ERROR |                      \
 114                          CHAN_CTRL_IE_DESC_ERROR)
 115
 116 /* bits of the channel interrupt enable mask */
 117 #define CHAN_IM_DESC_ERROR                      BIT(19)
 118 #define CHAN_IM_READ_ERROR                      BIT(9)
 119 #define CHAN_IM_IDLE_STOPPED                    BIT(6)
 120 #define CHAN_IM_MAGIC_STOPPED                   BIT(4)
 121 #define CHAN_IM_DESC_COMPLETED                  BIT(2)
 122 #define CHAN_IM_DESC_STOPPED                    BIT(1)
 123
 124 #define CHAN_IM_ALL     (CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR |      \
 125                          CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \
 126                          CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED)
 127
 128 /*
 129  * Channel SGDMA registers
 130  */
 131 #define XDMA_SGDMA_IDENTIFIER   0x4000
 132 #define XDMA_SGDMA_DESC_LO      0x4080
 133 #define XDMA_SGDMA_DESC_HI      0x4084
 134 #define XDMA_SGDMA_DESC_ADJ     0x4088
 135 #define XDMA_SGDMA_DESC_CREDIT  0x408c
 136
 137 /* bits of the SG DMA control register */
 138 #define XDMA_CTRL_RUN_STOP                      BIT(0)
 139 #define XDMA_CTRL_IE_DESC_STOPPED               BIT(1)
 140 #define XDMA_CTRL_IE_DESC_COMPLETED             BIT(2)
 141 #define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH        BIT(3)
 142 #define XDMA_CTRL_IE_MAGIC_STOPPED              BIT(4)
 143 #define XDMA_CTRL_IE_IDLE_STOPPED               BIT(6)
 144 #define XDMA_CTRL_IE_READ_ERROR                 GENMASK(13, 9)
 145 #define XDMA_CTRL_IE_DESC_ERROR                 GENMASK(23, 19)
 146 #define XDMA_CTRL_NON_INCR_ADDR                 BIT(25)
 147 #define XDMA_CTRL_POLL_MODE_WB                  BIT(26)
 148
 149 /*
 150  * interrupt registers
 151  */
 152 #define XDMA_IRQ_IDENTIFIER             0x2000
 153 #define XDMA_IRQ_USER_INT_EN            0x2004
 154 #define XDMA_IRQ_USER_INT_EN_W1S        0x2008
 155 #define XDMA_IRQ_USER_INT_EN_W1C        0x200c
 156 #define XDMA_IRQ_CHAN_INT_EN            0x2010
 157 #define XDMA_IRQ_CHAN_INT_EN_W1S        0x2014
 158 #define XDMA_IRQ_CHAN_INT_EN_W1C        0x2018
 159 #define XDMA_IRQ_USER_INT_REQ           0x2040
 160 #define XDMA_IRQ_CHAN_INT_REQ           0x2044
 161 #define XDMA_IRQ_USER_INT_PEND          0x2048
 162 #define XDMA_IRQ_CHAN_INT_PEND          0x204c
 163 #define XDMA_IRQ_USER_VEC_NUM           0x2080
 164 #define XDMA_IRQ_CHAN_VEC_NUM           0x20a0
 165
 166 #define XDMA_IRQ_VEC_SHIFT              8
 167
 168 #endif /* __DMA_XDMA_REGS_H */