1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ICS backend for OPAL managed interrupts.
5 * Copyright 2011 IBM Corp.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/irq.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
15 #include <linux/init.h>
16 #include <linux/cpu.h>
18 #include <linux/of_address.h>
19 #include <linux/spinlock.h>
20 #include <linux/msi.h>
21 #include <linux/list.h>
24 #include <asm/machdep.h>
26 #include <asm/errno.h>
29 #include <asm/firmware.h>
33 struct device_node *node;
38 #define to_ics_native(_ics) container_of(_ics, struct ics_native, ics)
40 static void __iomem *ics_native_xive(struct ics_native *in, unsigned int vec)
42 return in->base + 0x800 + ((vec - in->ibase) << 2);
45 static void ics_native_unmask_irq(struct irq_data *d)
47 unsigned int vec = (unsigned int)irqd_to_hwirq(d);
48 struct ics *ics = irq_data_get_irq_chip_data(d);
49 struct ics_native *in = to_ics_native(ics);
52 pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec);
54 if (vec < in->ibase || vec >= (in->ibase + in->icount))
57 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
58 out_be32(ics_native_xive(in, vec), (server << 8) | DEFAULT_PRIORITY);
61 static unsigned int ics_native_startup(struct irq_data *d)
65 * The generic MSI code returns with the interrupt disabled on the
66 * card, using the MSI mask bits. Firmware doesn't appear to unmask
67 * at that level, so we do it here by hand.
69 if (irq_data_get_msi_desc(d))
70 pci_msi_unmask_irq(d);
74 ics_native_unmask_irq(d);
78 static void ics_native_do_mask(struct ics_native *in, unsigned int vec)
80 out_be32(ics_native_xive(in, vec), 0xff);
83 static void ics_native_mask_irq(struct irq_data *d)
85 unsigned int vec = (unsigned int)irqd_to_hwirq(d);
86 struct ics *ics = irq_data_get_irq_chip_data(d);
87 struct ics_native *in = to_ics_native(ics);
89 pr_devel("ics-native: mask virq %d [hw 0x%x]\n", d->irq, vec);
91 if (vec < in->ibase || vec >= (in->ibase + in->icount))
93 ics_native_do_mask(in, vec);
96 static int ics_native_set_affinity(struct irq_data *d,
97 const struct cpumask *cpumask,
100 unsigned int vec = (unsigned int)irqd_to_hwirq(d);
101 struct ics *ics = irq_data_get_irq_chip_data(d);
102 struct ics_native *in = to_ics_native(ics);
106 if (vec < in->ibase || vec >= (in->ibase + in->icount))
109 server = xics_get_irq_server(d->irq, cpumask, 1);
111 pr_warn("%s: No online cpus in the mask %*pb for irq %d\n",
112 __func__, cpumask_pr_args(cpumask), d->irq);
116 xive = in_be32(ics_native_xive(in, vec));
117 xive = (xive & 0xff) | (server << 8);
118 out_be32(ics_native_xive(in, vec), xive);
120 return IRQ_SET_MASK_OK;
123 static struct irq_chip ics_native_irq_chip = {
125 .irq_startup = ics_native_startup,
126 .irq_mask = ics_native_mask_irq,
127 .irq_unmask = ics_native_unmask_irq,
128 .irq_eoi = NULL, /* Patched at init time */
129 .irq_set_affinity = ics_native_set_affinity,
130 .irq_set_type = xics_set_irq_type,
131 .irq_retrigger = xics_retrigger,
134 static int ics_native_check(struct ics *ics, unsigned int hw_irq)
136 struct ics_native *in = to_ics_native(ics);
138 pr_devel("%s: hw_irq=0x%x\n", __func__, hw_irq);
140 if (hw_irq < in->ibase || hw_irq >= (in->ibase + in->icount))
146 static void ics_native_mask_unknown(struct ics *ics, unsigned long vec)
148 struct ics_native *in = to_ics_native(ics);
150 if (vec < in->ibase || vec >= (in->ibase + in->icount))
153 ics_native_do_mask(in, vec);
156 static long ics_native_get_server(struct ics *ics, unsigned long vec)
158 struct ics_native *in = to_ics_native(ics);
161 if (vec < in->ibase || vec >= (in->ibase + in->icount))
164 xive = in_be32(ics_native_xive(in, vec));
165 return (xive >> 8) & 0xfff;
168 static int ics_native_host_match(struct ics *ics, struct device_node *node)
170 struct ics_native *in = to_ics_native(ics);
172 return in->node == node;
175 static struct ics ics_native_template = {
176 .check = ics_native_check,
177 .mask_unknown = ics_native_mask_unknown,
178 .get_server = ics_native_get_server,
179 .host_match = ics_native_host_match,
180 .chip = &ics_native_irq_chip,
183 static int __init ics_native_add_one(struct device_node *np)
185 struct ics_native *ics;
189 ics = kzalloc(sizeof(struct ics_native), GFP_KERNEL);
192 ics->node = of_node_get(np);
193 memcpy(&ics->ics, &ics_native_template, sizeof(struct ics));
195 ics->base = of_iomap(np, 0);
197 pr_err("Failed to map %pOFP\n", np);
202 count = of_property_count_u32_elems(np, "interrupt-ranges");
203 if (count < 2 || count & 1) {
204 pr_err("Failed to read interrupt-ranges of %pOFP\n", np);
209 pr_warn("ICS %pOFP has %d ranges, only one supported\n",
212 rc = of_property_read_u32_array(np, "interrupt-ranges",
215 pr_err("Failed to read interrupt-ranges of %pOFP\n", np);
218 ics->ibase = ranges[0];
219 ics->icount = ranges[1];
221 pr_info("ICS native initialized for sources %d..%d\n",
222 ics->ibase, ics->ibase + ics->icount - 1);
224 /* Register ourselves */
225 xics_register_ics(&ics->ics);
229 of_node_put(ics->node);
234 int __init ics_native_init(void)
236 struct device_node *ics;
237 bool found_one = false;
239 /* We need to patch our irq chip's EOI to point to the
242 ics_native_irq_chip.irq_eoi = icp_ops->eoi;
244 /* Find native ICS in the device-tree */
245 for_each_compatible_node(ics, NULL, "openpower,xics-sources") {
246 if (ics_native_add_one(ics) == 0)
251 pr_info("ICS native backend registered\n");
253 return found_one ? 0 : -ENODEV;