2 * Intel Atom SOC Power Management Controller Driver
3 * Copyright (c) 2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 #include <linux/debugfs.h>
19 #include <linux/device.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
23 #include <linux/platform_data/x86/clk-pmc-atom.h>
24 #include <linux/platform_data/x86/pmc_atom.h>
25 #include <linux/platform_device.h>
26 #include <linux/pci.h>
27 #include <linux/seq_file.h>
35 const struct pmc_bit_map *d3_sts_0;
36 const struct pmc_bit_map *d3_sts_1;
37 const struct pmc_bit_map *func_dis;
38 const struct pmc_bit_map *func_dis_2;
39 const struct pmc_bit_map *pss;
43 const struct pmc_reg_map *map;
44 const struct pmc_clk *clks;
50 const struct pmc_reg_map *map;
51 #ifdef CONFIG_DEBUG_FS
52 struct dentry *dbgfs_dir;
53 #endif /* CONFIG_DEBUG_FS */
57 static struct pmc_dev pmc_device;
58 static u32 acpi_base_addr;
60 static const struct pmc_clk byt_clks[] = {
69 .parent_name = "xtal",
74 static const struct pmc_clk cht_clks[] = {
83 static const struct pmc_bit_map d3_sts_0_map[] = {
84 {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
85 {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
86 {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
87 {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
88 {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
89 {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
90 {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
91 {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
92 {"SCC_EMMC", BIT_SCC_EMMC},
93 {"SCC_SDIO", BIT_SCC_SDIO},
94 {"SCC_SDCARD", BIT_SCC_SDCARD},
95 {"SCC_MIPI", BIT_SCC_MIPI},
102 {"USB_EHCI", BIT_USB_EHCI},
104 {"PCIE_PORT0", BIT_PCIE_PORT0},
105 {"PCIE_PORT1", BIT_PCIE_PORT1},
106 {"PCIE_PORT2", BIT_PCIE_PORT2},
107 {"PCIE_PORT3", BIT_PCIE_PORT3},
108 {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
109 {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
110 {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
111 {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
112 {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
113 {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
114 {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
115 {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
119 static struct pmc_bit_map byt_d3_sts_1_map[] = {
121 {"OTG_SS_PHY", BIT_OTG_SS_PHY},
122 {"USH_SS_PHY", BIT_USH_SS_PHY},
127 static struct pmc_bit_map cht_d3_sts_1_map[] = {
129 {"GMM", BIT_STS_GMM},
130 {"ISH", BIT_STS_ISH},
134 static struct pmc_bit_map cht_func_dis_2_map[] = {
141 static const struct pmc_bit_map byt_pss_map[] = {
142 {"GBE", PMC_PSS_BIT_GBE},
143 {"SATA", PMC_PSS_BIT_SATA},
144 {"HDA", PMC_PSS_BIT_HDA},
145 {"SEC", PMC_PSS_BIT_SEC},
146 {"PCIE", PMC_PSS_BIT_PCIE},
147 {"LPSS", PMC_PSS_BIT_LPSS},
148 {"LPE", PMC_PSS_BIT_LPE},
149 {"DFX", PMC_PSS_BIT_DFX},
150 {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
151 {"USH_SUS", PMC_PSS_BIT_USH_SUS},
152 {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
153 {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
154 {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
155 {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
156 {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
157 {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
158 {"USB", PMC_PSS_BIT_USB},
159 {"USB_SUS", PMC_PSS_BIT_USB_SUS},
163 static const struct pmc_bit_map cht_pss_map[] = {
164 {"SATA", PMC_PSS_BIT_SATA},
165 {"HDA", PMC_PSS_BIT_HDA},
166 {"SEC", PMC_PSS_BIT_SEC},
167 {"PCIE", PMC_PSS_BIT_PCIE},
168 {"LPSS", PMC_PSS_BIT_LPSS},
169 {"LPE", PMC_PSS_BIT_LPE},
170 {"UFS", PMC_PSS_BIT_CHT_UFS},
171 {"UXD", PMC_PSS_BIT_CHT_UXD},
172 {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
173 {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
174 {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
175 {"GMM", PMC_PSS_BIT_CHT_GMM},
176 {"ISH", PMC_PSS_BIT_CHT_ISH},
177 {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
178 {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
179 {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
180 {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
181 {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
182 {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
186 static const struct pmc_reg_map byt_reg_map = {
187 .d3_sts_0 = d3_sts_0_map,
188 .d3_sts_1 = byt_d3_sts_1_map,
189 .func_dis = d3_sts_0_map,
190 .func_dis_2 = byt_d3_sts_1_map,
194 static const struct pmc_reg_map cht_reg_map = {
195 .d3_sts_0 = d3_sts_0_map,
196 .d3_sts_1 = cht_d3_sts_1_map,
197 .func_dis = d3_sts_0_map,
198 .func_dis_2 = cht_func_dis_2_map,
202 static const struct pmc_data byt_data = {
207 static const struct pmc_data cht_data = {
212 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
214 return readl(pmc->regmap + reg_offset);
217 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
219 writel(val, pmc->regmap + reg_offset);
222 int pmc_atom_read(int offset, u32 *value)
224 struct pmc_dev *pmc = &pmc_device;
229 *value = pmc_reg_read(pmc, offset);
232 EXPORT_SYMBOL_GPL(pmc_atom_read);
234 int pmc_atom_write(int offset, u32 value)
236 struct pmc_dev *pmc = &pmc_device;
241 pmc_reg_write(pmc, offset, value);
244 EXPORT_SYMBOL_GPL(pmc_atom_write);
246 static void pmc_power_off(void)
251 pr_info("Preparing to enter system sleep state S5\n");
253 pm1_cnt_port = acpi_base_addr + PM1_CNT;
255 pm1_cnt_value = inl(pm1_cnt_port);
256 pm1_cnt_value &= SLEEP_TYPE_MASK;
257 pm1_cnt_value |= SLEEP_TYPE_S5;
258 pm1_cnt_value |= SLEEP_ENABLE;
260 outl(pm1_cnt_value, pm1_cnt_port);
263 static void pmc_hw_reg_setup(struct pmc_dev *pmc)
266 * Disable PMC S0IX_WAKE_EN events coming from:
268 * - GPIO_SUS ored dedicated IRQs
269 * - GPIO_SCORE ored dedicated IRQs
270 * - GPIO_SUS shared IRQ
271 * - GPIO_SCORE shared IRQ
273 pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
276 #ifdef CONFIG_DEBUG_FS
277 static void pmc_dev_state_print(struct seq_file *s, int reg_index,
278 u32 sts, const struct pmc_bit_map *sts_map,
279 u32 fd, const struct pmc_bit_map *fd_map)
281 int offset = PMC_REG_BIT_WIDTH * reg_index;
284 for (index = 0; sts_map[index].name; index++) {
285 seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
286 offset + index, sts_map[index].name,
287 fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
288 sts_map[index].bit_mask & sts ? "D3" : "D0");
292 static int pmc_dev_state_show(struct seq_file *s, void *unused)
294 struct pmc_dev *pmc = s->private;
295 const struct pmc_reg_map *m = pmc->map;
296 u32 func_dis, func_dis_2;
297 u32 d3_sts_0, d3_sts_1;
299 func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
300 func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
301 d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
302 d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
305 pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
308 pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
313 static int pmc_dev_state_open(struct inode *inode, struct file *file)
315 return single_open(file, pmc_dev_state_show, inode->i_private);
318 static const struct file_operations pmc_dev_state_ops = {
319 .open = pmc_dev_state_open,
322 .release = single_release,
325 static int pmc_pss_state_show(struct seq_file *s, void *unused)
327 struct pmc_dev *pmc = s->private;
328 const struct pmc_bit_map *map = pmc->map->pss;
329 u32 pss = pmc_reg_read(pmc, PMC_PSS);
332 for (index = 0; map[index].name; index++) {
333 seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
334 index, map[index].name,
335 map[index].bit_mask & pss ? "Off" : "On");
340 static int pmc_pss_state_open(struct inode *inode, struct file *file)
342 return single_open(file, pmc_pss_state_show, inode->i_private);
345 static const struct file_operations pmc_pss_state_ops = {
346 .open = pmc_pss_state_open,
349 .release = single_release,
352 static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
354 struct pmc_dev *pmc = s->private;
355 u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
357 s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
358 s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
359 s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
360 s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
361 s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
363 seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
364 seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
365 seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
366 seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
367 seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
371 static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
373 return single_open(file, pmc_sleep_tmr_show, inode->i_private);
376 static const struct file_operations pmc_sleep_tmr_ops = {
377 .open = pmc_sleep_tmr_open,
380 .release = single_release,
383 static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
385 debugfs_remove_recursive(pmc->dbgfs_dir);
388 static int pmc_dbgfs_register(struct pmc_dev *pmc)
390 struct dentry *dir, *f;
392 dir = debugfs_create_dir("pmc_atom", NULL);
396 pmc->dbgfs_dir = dir;
398 f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
399 dir, pmc, &pmc_dev_state_ops);
403 f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
404 dir, pmc, &pmc_pss_state_ops);
408 f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
409 dir, pmc, &pmc_sleep_tmr_ops);
415 pmc_dbgfs_unregister(pmc);
419 static int pmc_dbgfs_register(struct pmc_dev *pmc)
423 #endif /* CONFIG_DEBUG_FS */
426 * Some systems need one or more of their pmc_plt_clks to be
427 * marked as critical.
429 static const struct dmi_system_id critclk_systems[] = {
431 /* pmc_plt_clk0 is used for an external HSIC USB HUB */
432 .ident = "MPL CEC1x",
434 DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
435 DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
439 /* pmc_plt_clk0 - 3 are used for the 4 ethernet controllers */
440 .ident = "Lex 3I380D",
442 DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
443 DMI_MATCH(DMI_PRODUCT_NAME, "3I380D"),
447 /* pmc_plt_clk* - are used for ethernet controllers */
448 .ident = "Lex 2I385SW",
450 DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
451 DMI_MATCH(DMI_PRODUCT_NAME, "2I385SW"),
455 /* pmc_plt_clk* - are used for ethernet controllers */
456 .ident = "Beckhoff Baytrail",
458 DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
459 DMI_MATCH(DMI_PRODUCT_FAMILY, "CBxx63"),
463 .ident = "SIMATIC IPC227E",
465 DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
466 DMI_MATCH(DMI_PRODUCT_VERSION, "6ES7647-8B"),
470 .ident = "CONNECT X300",
472 DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
473 DMI_MATCH(DMI_PRODUCT_VERSION, "A5E45074588"),
480 static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
481 const struct pmc_data *pmc_data)
483 struct platform_device *clkdev;
484 struct pmc_clk_data *clk_data;
485 const struct dmi_system_id *d = dmi_first_match(critclk_systems);
487 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
491 clk_data->base = pmc_regmap; /* offset is added by client */
492 clk_data->clks = pmc_data->clks;
494 clk_data->critical = true;
495 pr_info("%s critclks quirk enabled\n", d->ident);
498 clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
500 clk_data, sizeof(*clk_data));
501 if (IS_ERR(clkdev)) {
503 return PTR_ERR(clkdev);
511 static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
513 struct pmc_dev *pmc = &pmc_device;
514 const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
515 const struct pmc_reg_map *map = data->map;
518 /* Obtain ACPI base address */
519 pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
520 acpi_base_addr &= ACPI_BASE_ADDR_MASK;
522 /* Install power off function */
523 if (acpi_base_addr != 0 && pm_power_off == NULL)
524 pm_power_off = pmc_power_off;
526 pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
527 pmc->base_addr &= PMC_BASE_ADDR_MASK;
529 pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
531 dev_err(&pdev->dev, "error: ioremap failed\n");
537 /* PMC hardware registers setup */
538 pmc_hw_reg_setup(pmc);
540 ret = pmc_dbgfs_register(pmc);
542 dev_warn(&pdev->dev, "debugfs register failed\n");
544 /* Register platform clocks - PMC_PLT_CLK [0..5] */
545 ret = pmc_setup_clks(pdev, pmc->regmap, data);
547 dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
555 * Data for PCI driver interface
557 * used by pci_match_id() call below.
559 static const struct pci_device_id pmc_pci_ids[] = {
560 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
561 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
565 static int __init pmc_atom_init(void)
567 struct pci_dev *pdev = NULL;
568 const struct pci_device_id *ent;
570 /* We look for our device - PCU PMC
571 * we assume that there is max. one device.
573 * We can't use plain pci_driver mechanism,
574 * as the device is really a multiple function device,
575 * main driver that binds to the pci_device is lpc_ich
576 * and have to find & bind to the device this way.
578 for_each_pci_dev(pdev) {
579 ent = pci_match_id(pmc_pci_ids, pdev);
581 return pmc_setup_dev(pdev, ent);
583 /* Device not found. */
587 device_initcall(pmc_atom_init);
590 MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
591 MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
592 MODULE_LICENSE("GPL v2");