1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
8 #include <linux/netdevice.h>
9 #include <linux/filter.h>
10 #include <linux/if_vlan.h>
11 #include <linux/bpf.h>
12 #include <linux/memory.h>
13 #include <linux/sort.h>
14 #include <asm/extable.h>
15 #include <asm/set_memory.h>
16 #include <asm/nospec-branch.h>
17 #include <asm/text-patching.h>
19 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
32 #define EMIT(bytes, len) \
33 do { prog = emit_code(prog, bytes, len); } while (0)
35 #define EMIT1(b1) EMIT(b1, 1)
36 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
37 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
38 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
40 #define EMIT1_off32(b1, off) \
41 do { EMIT1(b1); EMIT(off, 4); } while (0)
42 #define EMIT2_off32(b1, b2, off) \
43 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
44 #define EMIT3_off32(b1, b2, b3, off) \
45 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
46 #define EMIT4_off32(b1, b2, b3, b4, off) \
47 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
49 #ifdef CONFIG_X86_KERNEL_IBT
50 #define EMIT_ENDBR() EMIT(gen_endbr(), 4)
55 static bool is_imm8(int value)
57 return value <= 127 && value >= -128;
60 static bool is_simm32(s64 value)
62 return value == (s64)(s32)value;
65 static bool is_uimm32(u64 value)
67 return value == (u64)(u32)value;
71 #define EMIT_mov(DST, SRC) \
74 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
77 static int bpf_size_to_x86_bytes(int bpf_size)
79 if (bpf_size == BPF_W)
81 else if (bpf_size == BPF_H)
83 else if (bpf_size == BPF_B)
85 else if (bpf_size == BPF_DW)
92 * List of x86 cond jumps opcodes (. + s8)
93 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
106 /* Pick a register outside of BPF range for JIT internal work */
107 #define AUX_REG (MAX_BPF_JIT_REG + 1)
108 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
111 * The following table maps BPF registers to x86-64 registers.
113 * x86-64 register R12 is unused, since if used as base address
114 * register in load/store instructions, it always needs an
115 * extra byte of encoding and is callee saved.
117 * x86-64 register R9 is not used by BPF programs, but can be used by BPF
118 * trampoline. x86-64 register R10 is used for blinding (if enabled).
120 static const int reg2hex[] = {
121 [BPF_REG_0] = 0, /* RAX */
122 [BPF_REG_1] = 7, /* RDI */
123 [BPF_REG_2] = 6, /* RSI */
124 [BPF_REG_3] = 2, /* RDX */
125 [BPF_REG_4] = 1, /* RCX */
126 [BPF_REG_5] = 0, /* R8 */
127 [BPF_REG_6] = 3, /* RBX callee saved */
128 [BPF_REG_7] = 5, /* R13 callee saved */
129 [BPF_REG_8] = 6, /* R14 callee saved */
130 [BPF_REG_9] = 7, /* R15 callee saved */
131 [BPF_REG_FP] = 5, /* RBP readonly */
132 [BPF_REG_AX] = 2, /* R10 temp register */
133 [AUX_REG] = 3, /* R11 temp register */
134 [X86_REG_R9] = 1, /* R9 register, 6th function argument */
137 static const int reg2pt_regs[] = {
138 [BPF_REG_0] = offsetof(struct pt_regs, ax),
139 [BPF_REG_1] = offsetof(struct pt_regs, di),
140 [BPF_REG_2] = offsetof(struct pt_regs, si),
141 [BPF_REG_3] = offsetof(struct pt_regs, dx),
142 [BPF_REG_4] = offsetof(struct pt_regs, cx),
143 [BPF_REG_5] = offsetof(struct pt_regs, r8),
144 [BPF_REG_6] = offsetof(struct pt_regs, bx),
145 [BPF_REG_7] = offsetof(struct pt_regs, r13),
146 [BPF_REG_8] = offsetof(struct pt_regs, r14),
147 [BPF_REG_9] = offsetof(struct pt_regs, r15),
151 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
152 * which need extra byte of encoding.
153 * rax,rcx,...,rbp have simpler encoding
155 static bool is_ereg(u32 reg)
157 return (1 << reg) & (BIT(BPF_REG_5) |
167 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
168 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
169 * of encoding. al,cl,dl,bl have simpler encoding.
171 static bool is_ereg_8l(u32 reg)
173 return is_ereg(reg) ||
174 (1 << reg) & (BIT(BPF_REG_1) |
179 static bool is_axreg(u32 reg)
181 return reg == BPF_REG_0;
184 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
185 static u8 add_1mod(u8 byte, u32 reg)
192 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
201 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
202 static u8 add_1reg(u8 byte, u32 dst_reg)
204 return byte + reg2hex[dst_reg];
207 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
208 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
210 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
213 /* Some 1-byte opcodes for binary ALU operations */
214 static u8 simple_alu_opcodes[] = {
225 static void jit_fill_hole(void *area, unsigned int size)
227 /* Fill whole space with INT3 instructions */
228 memset(area, 0xcc, size);
231 int bpf_arch_text_invalidate(void *dst, size_t len)
233 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len));
237 int cleanup_addr; /* Epilogue code offset */
240 * Program specific offsets of labels in the code; these rely on the
241 * JIT doing at least 2 passes, recording the position on the first
242 * pass, only to generate the correct offset on the second pass.
244 int tail_call_direct_label;
245 int tail_call_indirect_label;
248 /* Maximum number of bytes emitted while JITing one eBPF insn */
249 #define BPF_MAX_INSN_SIZE 128
250 #define BPF_INSN_SAFETY 64
252 /* Number of bytes emit_patch() needs to generate instructions */
253 #define X86_PATCH_SIZE 5
254 /* Number of bytes that will be skipped on tailcall */
255 #define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE)
257 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
261 if (callee_regs_used[0])
262 EMIT1(0x53); /* push rbx */
263 if (callee_regs_used[1])
264 EMIT2(0x41, 0x55); /* push r13 */
265 if (callee_regs_used[2])
266 EMIT2(0x41, 0x56); /* push r14 */
267 if (callee_regs_used[3])
268 EMIT2(0x41, 0x57); /* push r15 */
272 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
276 if (callee_regs_used[3])
277 EMIT2(0x41, 0x5F); /* pop r15 */
278 if (callee_regs_used[2])
279 EMIT2(0x41, 0x5E); /* pop r14 */
280 if (callee_regs_used[1])
281 EMIT2(0x41, 0x5D); /* pop r13 */
282 if (callee_regs_used[0])
283 EMIT1(0x5B); /* pop rbx */
288 * Emit x86-64 prologue code for BPF program.
289 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
290 * while jumping to another program
292 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
293 bool tail_call_reachable, bool is_subprog)
297 /* BPF trampoline can be made to work without these nops,
298 * but let's waste 5 bytes for now and optimize later
301 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
302 prog += X86_PATCH_SIZE;
303 if (!ebpf_from_cbpf) {
304 if (tail_call_reachable && !is_subprog)
305 EMIT2(0x31, 0xC0); /* xor eax, eax */
307 EMIT2(0x66, 0x90); /* nop2 */
309 EMIT1(0x55); /* push rbp */
310 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
312 /* X86_TAIL_CALL_OFFSET is here */
315 /* sub rsp, rounded_stack_depth */
317 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
318 if (tail_call_reachable)
319 EMIT1(0x50); /* push rax */
323 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
328 offset = func - (ip + X86_PATCH_SIZE);
329 if (!is_simm32(offset)) {
330 pr_err("Target call %p is out of range\n", func);
333 EMIT1_off32(opcode, offset);
338 static int emit_call(u8 **pprog, void *func, void *ip)
340 return emit_patch(pprog, func, ip, 0xE8);
343 static int emit_jump(u8 **pprog, void *func, void *ip)
345 return emit_patch(pprog, func, ip, 0xE9);
348 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
349 void *old_addr, void *new_addr)
351 const u8 *nop_insn = x86_nops[5];
352 u8 old_insn[X86_PATCH_SIZE];
353 u8 new_insn[X86_PATCH_SIZE];
357 memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
360 ret = t == BPF_MOD_CALL ?
361 emit_call(&prog, old_addr, ip) :
362 emit_jump(&prog, old_addr, ip);
367 memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
370 ret = t == BPF_MOD_CALL ?
371 emit_call(&prog, new_addr, ip) :
372 emit_jump(&prog, new_addr, ip);
378 mutex_lock(&text_mutex);
379 if (memcmp(ip, old_insn, X86_PATCH_SIZE))
382 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
383 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
387 mutex_unlock(&text_mutex);
391 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
392 void *old_addr, void *new_addr)
394 if (!is_kernel_text((long)ip) &&
395 !is_bpf_text_address((long)ip))
396 /* BPF poking in modules is not supported */
400 * See emit_prologue(), for IBT builds the trampoline hook is preceded
401 * with an ENDBR instruction.
403 if (is_endbr(*(u32 *)ip))
404 ip += ENDBR_INSN_SIZE;
406 return __bpf_arch_text_poke(ip, t, old_addr, new_addr);
409 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8)
411 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
415 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
417 EMIT2(0xFF, 0xE0 + reg);
418 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
419 OPTIMIZER_HIDE_VAR(reg);
420 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
422 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */
423 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS))
424 EMIT1(0xCC); /* int3 */
430 static void emit_return(u8 **pprog, u8 *ip)
434 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
435 emit_jump(&prog, x86_return_thunk, ip);
437 EMIT1(0xC3); /* ret */
438 if (IS_ENABLED(CONFIG_SLS))
439 EMIT1(0xCC); /* int3 */
446 * Generate the following code:
448 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
449 * if (index >= array->map.max_entries)
451 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
453 * prog = array->ptrs[index];
456 * goto *(prog->bpf_func + prologue_size);
459 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
460 u32 stack_depth, u8 *ip,
461 struct jit_context *ctx)
463 int tcc_off = -4 - round_up(stack_depth, 8);
464 u8 *prog = *pprog, *start = *pprog;
468 * rdi - pointer to ctx
469 * rsi - pointer to bpf_array
470 * rdx - index in bpf_array
474 * if (index >= array->map.max_entries)
477 EMIT2(0x89, 0xD2); /* mov edx, edx */
478 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */
479 offsetof(struct bpf_array, map.max_entries));
481 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
482 EMIT2(X86_JBE, offset); /* jbe out */
485 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
488 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
489 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
491 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
492 EMIT2(X86_JAE, offset); /* jae out */
493 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
494 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
496 /* prog = array->ptrs[index]; */
497 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
498 offsetof(struct bpf_array, ptrs));
504 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */
506 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
507 EMIT2(X86_JE, offset); /* je out */
509 pop_callee_regs(&prog, callee_regs_used);
511 EMIT1(0x58); /* pop rax */
513 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */
514 round_up(stack_depth, 8));
516 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
517 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */
518 offsetof(struct bpf_prog, bpf_func));
519 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */
520 X86_TAIL_CALL_OFFSET);
522 * Now we're ready to jump into next BPF program
523 * rdi == ctx (1st arg)
524 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
526 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
529 ctx->tail_call_indirect_label = prog - start;
533 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
535 bool *callee_regs_used, u32 stack_depth,
536 struct jit_context *ctx)
538 int tcc_off = -4 - round_up(stack_depth, 8);
539 u8 *prog = *pprog, *start = *pprog;
543 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
546 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
547 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
549 offset = ctx->tail_call_direct_label - (prog + 2 - start);
550 EMIT2(X86_JAE, offset); /* jae out */
551 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
552 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
554 poke->tailcall_bypass = ip + (prog - start);
555 poke->adj_off = X86_TAIL_CALL_OFFSET;
556 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
557 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
559 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
560 poke->tailcall_bypass);
562 pop_callee_regs(&prog, callee_regs_used);
563 EMIT1(0x58); /* pop rax */
565 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
567 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
568 prog += X86_PATCH_SIZE;
571 ctx->tail_call_direct_label = prog - start;
576 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
578 struct bpf_jit_poke_descriptor *poke;
579 struct bpf_array *array;
580 struct bpf_prog *target;
583 for (i = 0; i < prog->aux->size_poke_tab; i++) {
584 poke = &prog->aux->poke_tab[i];
585 if (poke->aux && poke->aux != prog->aux)
588 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
590 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
593 array = container_of(poke->tail_call.map, struct bpf_array, map);
594 mutex_lock(&array->aux->poke_mutex);
595 target = array->ptrs[poke->tail_call.key];
597 ret = __bpf_arch_text_poke(poke->tailcall_target,
599 (u8 *)target->bpf_func +
602 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
604 (u8 *)poke->tailcall_target +
605 X86_PATCH_SIZE, NULL);
608 WRITE_ONCE(poke->tailcall_target_stable, true);
609 mutex_unlock(&array->aux->poke_mutex);
613 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
614 u32 dst_reg, const u32 imm32)
620 * Optimization: if imm32 is positive, use 'mov %eax, imm32'
621 * (which zero-extends imm32) to save 2 bytes.
623 if (sign_propagate && (s32)imm32 < 0) {
624 /* 'mov %rax, imm32' sign extends imm32 */
625 b1 = add_1mod(0x48, dst_reg);
628 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
633 * Optimization: if imm32 is zero, use 'xor %eax, %eax'
637 if (is_ereg(dst_reg))
638 EMIT1(add_2mod(0x40, dst_reg, dst_reg));
641 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
645 /* mov %eax, imm32 */
646 if (is_ereg(dst_reg))
647 EMIT1(add_1mod(0x40, dst_reg));
648 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
653 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
654 const u32 imm32_hi, const u32 imm32_lo)
658 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
660 * For emitting plain u32, where sign bit must not be
661 * propagated LLVM tends to load imm64 over mov32
662 * directly, so save couple of bytes by just doing
663 * 'mov %eax, imm32' instead.
665 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
667 /* movabsq rax, imm64 */
668 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
676 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
682 EMIT_mov(dst_reg, src_reg);
685 if (is_ereg(dst_reg) || is_ereg(src_reg))
686 EMIT1(add_2mod(0x40, dst_reg, src_reg));
687 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
693 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
694 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
699 /* 1-byte signed displacement.
701 * If off == 0 we could skip this and save one extra byte, but
702 * special case of x86 R13 which always needs an offset is not
705 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
707 /* 4-byte signed displacement */
708 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
714 * Emit a REX byte if it will be necessary to address these registers
716 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
721 EMIT1(add_2mod(0x48, dst_reg, src_reg));
722 else if (is_ereg(dst_reg) || is_ereg(src_reg))
723 EMIT1(add_2mod(0x40, dst_reg, src_reg));
728 * Similar version of maybe_emit_mod() for a single register
730 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
735 EMIT1(add_1mod(0x48, reg));
736 else if (is_ereg(reg))
737 EMIT1(add_1mod(0x40, reg));
741 /* LDX: dst_reg = *(u8*)(src_reg + off) */
742 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
748 /* Emit 'movzx rax, byte ptr [rax + off]' */
749 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
752 /* Emit 'movzx rax, word ptr [rax + off]' */
753 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
756 /* Emit 'mov eax, dword ptr [rax+0x14]' */
757 if (is_ereg(dst_reg) || is_ereg(src_reg))
758 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
763 /* Emit 'mov rax, qword ptr [rax+0x14]' */
764 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
767 emit_insn_suffix(&prog, src_reg, dst_reg, off);
771 /* STX: *(u8*)(dst_reg + off) = src_reg */
772 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
778 /* Emit 'mov byte ptr [rax + off], al' */
779 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
780 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
781 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
786 if (is_ereg(dst_reg) || is_ereg(src_reg))
787 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
792 if (is_ereg(dst_reg) || is_ereg(src_reg))
793 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
798 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
801 emit_insn_suffix(&prog, dst_reg, src_reg, off);
805 static int emit_atomic(u8 **pprog, u8 atomic_op,
806 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
810 EMIT1(0xF0); /* lock prefix */
812 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
820 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
821 EMIT1(simple_alu_opcodes[atomic_op]);
823 case BPF_ADD | BPF_FETCH:
824 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
828 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
832 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
836 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
840 emit_insn_suffix(&prog, dst_reg, src_reg, off);
846 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
848 u32 reg = x->fixup >> 8;
850 /* jump over faulting load and clear dest register */
851 *(unsigned long *)((void *)regs + reg) = 0;
852 regs->ip += x->fixup & 0xff;
856 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
857 bool *regs_used, bool *tail_call_seen)
861 for (i = 1; i <= insn_cnt; i++, insn++) {
862 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
863 *tail_call_seen = true;
864 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
866 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
868 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
870 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
875 static void emit_nops(u8 **pprog, int len)
883 if (noplen > ASM_NOP_MAX)
884 noplen = ASM_NOP_MAX;
886 for (i = 0; i < noplen; i++)
887 EMIT1(x86_nops[noplen][i]);
894 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
896 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
897 #define RESTORE_TAIL_CALL_CNT(stack) \
898 EMIT3_off32(0x48, 0x8B, 0x85, -round_up(stack, 8) - 8)
900 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image,
901 int oldproglen, struct jit_context *ctx, bool jmp_padding)
903 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
904 struct bpf_insn *insn = bpf_prog->insnsi;
905 bool callee_regs_used[4] = {};
906 int insn_cnt = bpf_prog->len;
907 bool tail_call_seen = false;
908 bool seen_exit = false;
909 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
911 int ilen, proglen = 0;
915 detect_reg_usage(insn, insn_cnt, callee_regs_used,
918 /* tail call's presence in current prog implies it is reachable */
919 tail_call_reachable |= tail_call_seen;
921 emit_prologue(&prog, bpf_prog->aux->stack_depth,
922 bpf_prog_was_classic(bpf_prog), tail_call_reachable,
923 bpf_prog->aux->func_idx != 0);
924 push_callee_regs(&prog, callee_regs_used);
928 memcpy(rw_image + proglen, temp, ilen);
933 for (i = 1; i <= insn_cnt; i++, insn++) {
934 const s32 imm32 = insn->imm;
935 u32 dst_reg = insn->dst_reg;
936 u32 src_reg = insn->src_reg;
944 switch (insn->code) {
946 case BPF_ALU | BPF_ADD | BPF_X:
947 case BPF_ALU | BPF_SUB | BPF_X:
948 case BPF_ALU | BPF_AND | BPF_X:
949 case BPF_ALU | BPF_OR | BPF_X:
950 case BPF_ALU | BPF_XOR | BPF_X:
951 case BPF_ALU64 | BPF_ADD | BPF_X:
952 case BPF_ALU64 | BPF_SUB | BPF_X:
953 case BPF_ALU64 | BPF_AND | BPF_X:
954 case BPF_ALU64 | BPF_OR | BPF_X:
955 case BPF_ALU64 | BPF_XOR | BPF_X:
956 maybe_emit_mod(&prog, dst_reg, src_reg,
957 BPF_CLASS(insn->code) == BPF_ALU64);
958 b2 = simple_alu_opcodes[BPF_OP(insn->code)];
959 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
962 case BPF_ALU64 | BPF_MOV | BPF_X:
963 case BPF_ALU | BPF_MOV | BPF_X:
965 BPF_CLASS(insn->code) == BPF_ALU64,
970 case BPF_ALU | BPF_NEG:
971 case BPF_ALU64 | BPF_NEG:
972 maybe_emit_1mod(&prog, dst_reg,
973 BPF_CLASS(insn->code) == BPF_ALU64);
974 EMIT2(0xF7, add_1reg(0xD8, dst_reg));
977 case BPF_ALU | BPF_ADD | BPF_K:
978 case BPF_ALU | BPF_SUB | BPF_K:
979 case BPF_ALU | BPF_AND | BPF_K:
980 case BPF_ALU | BPF_OR | BPF_K:
981 case BPF_ALU | BPF_XOR | BPF_K:
982 case BPF_ALU64 | BPF_ADD | BPF_K:
983 case BPF_ALU64 | BPF_SUB | BPF_K:
984 case BPF_ALU64 | BPF_AND | BPF_K:
985 case BPF_ALU64 | BPF_OR | BPF_K:
986 case BPF_ALU64 | BPF_XOR | BPF_K:
987 maybe_emit_1mod(&prog, dst_reg,
988 BPF_CLASS(insn->code) == BPF_ALU64);
991 * b3 holds 'normal' opcode, b2 short form only valid
992 * in case dst is eax/rax.
994 switch (BPF_OP(insn->code)) {
1018 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1019 else if (is_axreg(dst_reg))
1020 EMIT1_off32(b2, imm32);
1022 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1025 case BPF_ALU64 | BPF_MOV | BPF_K:
1026 case BPF_ALU | BPF_MOV | BPF_K:
1027 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1031 case BPF_LD | BPF_IMM | BPF_DW:
1032 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1037 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1038 case BPF_ALU | BPF_MOD | BPF_X:
1039 case BPF_ALU | BPF_DIV | BPF_X:
1040 case BPF_ALU | BPF_MOD | BPF_K:
1041 case BPF_ALU | BPF_DIV | BPF_K:
1042 case BPF_ALU64 | BPF_MOD | BPF_X:
1043 case BPF_ALU64 | BPF_DIV | BPF_X:
1044 case BPF_ALU64 | BPF_MOD | BPF_K:
1045 case BPF_ALU64 | BPF_DIV | BPF_K: {
1046 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1048 if (dst_reg != BPF_REG_0)
1049 EMIT1(0x50); /* push rax */
1050 if (dst_reg != BPF_REG_3)
1051 EMIT1(0x52); /* push rdx */
1053 if (BPF_SRC(insn->code) == BPF_X) {
1054 if (src_reg == BPF_REG_0 ||
1055 src_reg == BPF_REG_3) {
1056 /* mov r11, src_reg */
1057 EMIT_mov(AUX_REG, src_reg);
1061 /* mov r11, imm32 */
1062 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1066 if (dst_reg != BPF_REG_0)
1067 /* mov rax, dst_reg */
1068 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg);
1072 * equivalent to 'xor rdx, rdx', but one byte less
1077 maybe_emit_1mod(&prog, src_reg, is64);
1078 EMIT2(0xF7, add_1reg(0xF0, src_reg));
1080 if (BPF_OP(insn->code) == BPF_MOD &&
1081 dst_reg != BPF_REG_3)
1082 /* mov dst_reg, rdx */
1083 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3);
1084 else if (BPF_OP(insn->code) == BPF_DIV &&
1085 dst_reg != BPF_REG_0)
1086 /* mov dst_reg, rax */
1087 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0);
1089 if (dst_reg != BPF_REG_3)
1090 EMIT1(0x5A); /* pop rdx */
1091 if (dst_reg != BPF_REG_0)
1092 EMIT1(0x58); /* pop rax */
1096 case BPF_ALU | BPF_MUL | BPF_K:
1097 case BPF_ALU64 | BPF_MUL | BPF_K:
1098 maybe_emit_mod(&prog, dst_reg, dst_reg,
1099 BPF_CLASS(insn->code) == BPF_ALU64);
1102 /* imul dst_reg, dst_reg, imm8 */
1103 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg),
1106 /* imul dst_reg, dst_reg, imm32 */
1108 add_2reg(0xC0, dst_reg, dst_reg),
1112 case BPF_ALU | BPF_MUL | BPF_X:
1113 case BPF_ALU64 | BPF_MUL | BPF_X:
1114 maybe_emit_mod(&prog, src_reg, dst_reg,
1115 BPF_CLASS(insn->code) == BPF_ALU64);
1117 /* imul dst_reg, src_reg */
1118 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg));
1122 case BPF_ALU | BPF_LSH | BPF_K:
1123 case BPF_ALU | BPF_RSH | BPF_K:
1124 case BPF_ALU | BPF_ARSH | BPF_K:
1125 case BPF_ALU64 | BPF_LSH | BPF_K:
1126 case BPF_ALU64 | BPF_RSH | BPF_K:
1127 case BPF_ALU64 | BPF_ARSH | BPF_K:
1128 maybe_emit_1mod(&prog, dst_reg,
1129 BPF_CLASS(insn->code) == BPF_ALU64);
1131 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1133 EMIT2(0xD1, add_1reg(b3, dst_reg));
1135 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1138 case BPF_ALU | BPF_LSH | BPF_X:
1139 case BPF_ALU | BPF_RSH | BPF_X:
1140 case BPF_ALU | BPF_ARSH | BPF_X:
1141 case BPF_ALU64 | BPF_LSH | BPF_X:
1142 case BPF_ALU64 | BPF_RSH | BPF_X:
1143 case BPF_ALU64 | BPF_ARSH | BPF_X:
1145 /* Check for bad case when dst_reg == rcx */
1146 if (dst_reg == BPF_REG_4) {
1147 /* mov r11, dst_reg */
1148 EMIT_mov(AUX_REG, dst_reg);
1152 if (src_reg != BPF_REG_4) { /* common case */
1153 EMIT1(0x51); /* push rcx */
1155 /* mov rcx, src_reg */
1156 EMIT_mov(BPF_REG_4, src_reg);
1159 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1160 maybe_emit_1mod(&prog, dst_reg,
1161 BPF_CLASS(insn->code) == BPF_ALU64);
1163 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1164 EMIT2(0xD3, add_1reg(b3, dst_reg));
1166 if (src_reg != BPF_REG_4)
1167 EMIT1(0x59); /* pop rcx */
1169 if (insn->dst_reg == BPF_REG_4)
1170 /* mov dst_reg, r11 */
1171 EMIT_mov(insn->dst_reg, AUX_REG);
1174 case BPF_ALU | BPF_END | BPF_FROM_BE:
1177 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1179 if (is_ereg(dst_reg))
1181 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1183 /* Emit 'movzwl eax, ax' */
1184 if (is_ereg(dst_reg))
1185 EMIT3(0x45, 0x0F, 0xB7);
1188 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1191 /* Emit 'bswap eax' to swap lower 4 bytes */
1192 if (is_ereg(dst_reg))
1196 EMIT1(add_1reg(0xC8, dst_reg));
1199 /* Emit 'bswap rax' to swap 8 bytes */
1200 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1201 add_1reg(0xC8, dst_reg));
1206 case BPF_ALU | BPF_END | BPF_FROM_LE:
1210 * Emit 'movzwl eax, ax' to zero extend 16-bit
1213 if (is_ereg(dst_reg))
1214 EMIT3(0x45, 0x0F, 0xB7);
1217 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1220 /* Emit 'mov eax, eax' to clear upper 32-bits */
1221 if (is_ereg(dst_reg))
1223 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1231 /* speculation barrier */
1232 case BPF_ST | BPF_NOSPEC:
1233 if (boot_cpu_has(X86_FEATURE_XMM2))
1237 /* ST: *(u8*)(dst_reg + off) = imm */
1238 case BPF_ST | BPF_MEM | BPF_B:
1239 if (is_ereg(dst_reg))
1244 case BPF_ST | BPF_MEM | BPF_H:
1245 if (is_ereg(dst_reg))
1246 EMIT3(0x66, 0x41, 0xC7);
1250 case BPF_ST | BPF_MEM | BPF_W:
1251 if (is_ereg(dst_reg))
1256 case BPF_ST | BPF_MEM | BPF_DW:
1257 EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1259 st: if (is_imm8(insn->off))
1260 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1262 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1264 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1267 /* STX: *(u8*)(dst_reg + off) = src_reg */
1268 case BPF_STX | BPF_MEM | BPF_B:
1269 case BPF_STX | BPF_MEM | BPF_H:
1270 case BPF_STX | BPF_MEM | BPF_W:
1271 case BPF_STX | BPF_MEM | BPF_DW:
1272 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1275 /* LDX: dst_reg = *(u8*)(src_reg + off) */
1276 case BPF_LDX | BPF_MEM | BPF_B:
1277 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1278 case BPF_LDX | BPF_MEM | BPF_H:
1279 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1280 case BPF_LDX | BPF_MEM | BPF_W:
1281 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1282 case BPF_LDX | BPF_MEM | BPF_DW:
1283 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1284 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1285 /* Though the verifier prevents negative insn->off in BPF_PROBE_MEM
1286 * add abs(insn->off) to the limit to make sure that negative
1287 * offset won't be an issue.
1288 * insn->off is s16, so it won't affect valid pointers.
1290 u64 limit = TASK_SIZE_MAX + PAGE_SIZE + abs(insn->off);
1291 u8 *end_of_jmp1, *end_of_jmp2;
1293 /* Conservatively check that src_reg + insn->off is a kernel address:
1294 * 1. src_reg + insn->off >= limit
1295 * 2. src_reg + insn->off doesn't become small positive.
1296 * Cannot do src_reg + insn->off >= limit in one branch,
1297 * since it needs two spare registers, but JIT has only one.
1300 /* movabsq r11, limit */
1301 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG));
1302 EMIT((u32)limit, 4);
1303 EMIT(limit >> 32, 4);
1304 /* cmp src_reg, r11 */
1305 maybe_emit_mod(&prog, src_reg, AUX_REG, true);
1306 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG));
1307 /* if unsigned '<' goto end_of_jmp2 */
1311 /* mov r11, src_reg */
1312 emit_mov_reg(&prog, true, AUX_REG, src_reg);
1313 /* add r11, insn->off */
1314 maybe_emit_1mod(&prog, AUX_REG, true);
1315 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
1316 /* jmp if not carry to start_of_ldx
1317 * Otherwise ERR_PTR(-EINVAL) + 128 will be the user addr
1318 * that has to be rejected.
1320 EMIT2(0x73 /* JNC */, 0);
1323 /* xor dst_reg, dst_reg */
1324 emit_mov_imm32(&prog, false, dst_reg, 0);
1325 /* jmp byte_after_ldx */
1328 /* populate jmp_offset for JB above to jump to xor dst_reg */
1329 end_of_jmp1[-1] = end_of_jmp2 - end_of_jmp1;
1330 /* populate jmp_offset for JNC above to jump to start_of_ldx */
1331 start_of_ldx = prog;
1332 end_of_jmp2[-1] = start_of_ldx - end_of_jmp2;
1334 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1335 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1336 struct exception_table_entry *ex;
1337 u8 *_insn = image + proglen + (start_of_ldx - temp);
1340 /* populate jmp_offset for JMP above */
1341 start_of_ldx[-1] = prog - start_of_ldx;
1343 if (!bpf_prog->aux->extable)
1346 if (excnt >= bpf_prog->aux->num_exentries) {
1347 pr_err("ex gen bug\n");
1350 ex = &bpf_prog->aux->extable[excnt++];
1352 delta = _insn - (u8 *)&ex->insn;
1353 if (!is_simm32(delta)) {
1354 pr_err("extable->insn doesn't fit into 32-bit\n");
1357 /* switch ex to rw buffer for writes */
1358 ex = (void *)rw_image + ((void *)ex - (void *)image);
1362 ex->data = EX_TYPE_BPF;
1364 if (dst_reg > BPF_REG_9) {
1365 pr_err("verifier error\n");
1369 * Compute size of x86 insn and its target dest x86 register.
1370 * ex_handler_bpf() will use lower 8 bits to adjust
1371 * pt_regs->ip to jump over this x86 instruction
1372 * and upper bits to figure out which pt_regs to zero out.
1373 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1374 * of 4 bytes will be ignored and rbx will be zero inited.
1376 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1380 case BPF_STX | BPF_ATOMIC | BPF_W:
1381 case BPF_STX | BPF_ATOMIC | BPF_DW:
1382 if (insn->imm == (BPF_AND | BPF_FETCH) ||
1383 insn->imm == (BPF_OR | BPF_FETCH) ||
1384 insn->imm == (BPF_XOR | BPF_FETCH)) {
1385 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1386 u32 real_src_reg = src_reg;
1387 u32 real_dst_reg = dst_reg;
1391 * Can't be implemented with a single x86 insn.
1392 * Need to do a CMPXCHG loop.
1395 /* Will need RAX as a CMPXCHG operand so save R0 */
1396 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1397 if (src_reg == BPF_REG_0)
1398 real_src_reg = BPF_REG_AX;
1399 if (dst_reg == BPF_REG_0)
1400 real_dst_reg = BPF_REG_AX;
1402 branch_target = prog;
1403 /* Load old value */
1404 emit_ldx(&prog, BPF_SIZE(insn->code),
1405 BPF_REG_0, real_dst_reg, insn->off);
1407 * Perform the (commutative) operation locally,
1408 * put the result in the AUX_REG.
1410 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1411 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1412 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1413 add_2reg(0xC0, AUX_REG, real_src_reg));
1414 /* Attempt to swap in new value */
1415 err = emit_atomic(&prog, BPF_CMPXCHG,
1416 real_dst_reg, AUX_REG,
1418 BPF_SIZE(insn->code));
1422 * ZF tells us whether we won the race. If it's
1423 * cleared we need to try again.
1425 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1426 /* Return the pre-modification value */
1427 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1428 /* Restore R0 after clobbering RAX */
1429 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1433 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1434 insn->off, BPF_SIZE(insn->code));
1440 case BPF_JMP | BPF_CALL:
1441 func = (u8 *) __bpf_call_base + imm32;
1442 if (tail_call_reachable) {
1443 RESTORE_TAIL_CALL_CNT(bpf_prog->aux->stack_depth);
1444 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
1447 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1]))
1452 case BPF_JMP | BPF_TAIL_CALL:
1454 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1455 &prog, image + addrs[i - 1],
1457 bpf_prog->aux->stack_depth,
1460 emit_bpf_tail_call_indirect(&prog,
1462 bpf_prog->aux->stack_depth,
1463 image + addrs[i - 1],
1468 case BPF_JMP | BPF_JEQ | BPF_X:
1469 case BPF_JMP | BPF_JNE | BPF_X:
1470 case BPF_JMP | BPF_JGT | BPF_X:
1471 case BPF_JMP | BPF_JLT | BPF_X:
1472 case BPF_JMP | BPF_JGE | BPF_X:
1473 case BPF_JMP | BPF_JLE | BPF_X:
1474 case BPF_JMP | BPF_JSGT | BPF_X:
1475 case BPF_JMP | BPF_JSLT | BPF_X:
1476 case BPF_JMP | BPF_JSGE | BPF_X:
1477 case BPF_JMP | BPF_JSLE | BPF_X:
1478 case BPF_JMP32 | BPF_JEQ | BPF_X:
1479 case BPF_JMP32 | BPF_JNE | BPF_X:
1480 case BPF_JMP32 | BPF_JGT | BPF_X:
1481 case BPF_JMP32 | BPF_JLT | BPF_X:
1482 case BPF_JMP32 | BPF_JGE | BPF_X:
1483 case BPF_JMP32 | BPF_JLE | BPF_X:
1484 case BPF_JMP32 | BPF_JSGT | BPF_X:
1485 case BPF_JMP32 | BPF_JSLT | BPF_X:
1486 case BPF_JMP32 | BPF_JSGE | BPF_X:
1487 case BPF_JMP32 | BPF_JSLE | BPF_X:
1488 /* cmp dst_reg, src_reg */
1489 maybe_emit_mod(&prog, dst_reg, src_reg,
1490 BPF_CLASS(insn->code) == BPF_JMP);
1491 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1494 case BPF_JMP | BPF_JSET | BPF_X:
1495 case BPF_JMP32 | BPF_JSET | BPF_X:
1496 /* test dst_reg, src_reg */
1497 maybe_emit_mod(&prog, dst_reg, src_reg,
1498 BPF_CLASS(insn->code) == BPF_JMP);
1499 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1502 case BPF_JMP | BPF_JSET | BPF_K:
1503 case BPF_JMP32 | BPF_JSET | BPF_K:
1504 /* test dst_reg, imm32 */
1505 maybe_emit_1mod(&prog, dst_reg,
1506 BPF_CLASS(insn->code) == BPF_JMP);
1507 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1510 case BPF_JMP | BPF_JEQ | BPF_K:
1511 case BPF_JMP | BPF_JNE | BPF_K:
1512 case BPF_JMP | BPF_JGT | BPF_K:
1513 case BPF_JMP | BPF_JLT | BPF_K:
1514 case BPF_JMP | BPF_JGE | BPF_K:
1515 case BPF_JMP | BPF_JLE | BPF_K:
1516 case BPF_JMP | BPF_JSGT | BPF_K:
1517 case BPF_JMP | BPF_JSLT | BPF_K:
1518 case BPF_JMP | BPF_JSGE | BPF_K:
1519 case BPF_JMP | BPF_JSLE | BPF_K:
1520 case BPF_JMP32 | BPF_JEQ | BPF_K:
1521 case BPF_JMP32 | BPF_JNE | BPF_K:
1522 case BPF_JMP32 | BPF_JGT | BPF_K:
1523 case BPF_JMP32 | BPF_JLT | BPF_K:
1524 case BPF_JMP32 | BPF_JGE | BPF_K:
1525 case BPF_JMP32 | BPF_JLE | BPF_K:
1526 case BPF_JMP32 | BPF_JSGT | BPF_K:
1527 case BPF_JMP32 | BPF_JSLT | BPF_K:
1528 case BPF_JMP32 | BPF_JSGE | BPF_K:
1529 case BPF_JMP32 | BPF_JSLE | BPF_K:
1530 /* test dst_reg, dst_reg to save one extra byte */
1532 maybe_emit_mod(&prog, dst_reg, dst_reg,
1533 BPF_CLASS(insn->code) == BPF_JMP);
1534 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1538 /* cmp dst_reg, imm8/32 */
1539 maybe_emit_1mod(&prog, dst_reg,
1540 BPF_CLASS(insn->code) == BPF_JMP);
1543 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1545 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1547 emit_cond_jmp: /* Convert BPF opcode to x86 */
1548 switch (BPF_OP(insn->code)) {
1557 /* GT is unsigned '>', JA in x86 */
1561 /* LT is unsigned '<', JB in x86 */
1565 /* GE is unsigned '>=', JAE in x86 */
1569 /* LE is unsigned '<=', JBE in x86 */
1573 /* Signed '>', GT in x86 */
1577 /* Signed '<', LT in x86 */
1581 /* Signed '>=', GE in x86 */
1585 /* Signed '<=', LE in x86 */
1588 default: /* to silence GCC warning */
1591 jmp_offset = addrs[i + insn->off] - addrs[i];
1592 if (is_imm8(jmp_offset)) {
1594 /* To keep the jmp_offset valid, the extra bytes are
1595 * padded before the jump insn, so we subtract the
1596 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1598 * If the previous pass already emits an imm8
1599 * jmp_cond, then this BPF insn won't shrink, so
1602 * On the other hand, if the previous pass emits an
1603 * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1604 * keep the image from shrinking further.
1606 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1607 * is 2 bytes, so the size difference is 4 bytes.
1609 nops = INSN_SZ_DIFF - 2;
1610 if (nops != 0 && nops != 4) {
1611 pr_err("unexpected jmp_cond padding: %d bytes\n",
1615 emit_nops(&prog, nops);
1617 EMIT2(jmp_cond, jmp_offset);
1618 } else if (is_simm32(jmp_offset)) {
1619 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1621 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1627 case BPF_JMP | BPF_JA:
1628 case BPF_JMP32 | BPF_JA:
1629 if (BPF_CLASS(insn->code) == BPF_JMP) {
1630 if (insn->off == -1)
1631 /* -1 jmp instructions will always jump
1632 * backwards two bytes. Explicitly handling
1633 * this case avoids wasting too many passes
1634 * when there are long sequences of replaced
1639 jmp_offset = addrs[i + insn->off] - addrs[i];
1641 if (insn->imm == -1)
1644 jmp_offset = addrs[i + insn->imm] - addrs[i];
1649 * If jmp_padding is enabled, the extra nops will
1650 * be inserted. Otherwise, optimize out nop jumps.
1653 /* There are 3 possible conditions.
1654 * (1) This BPF_JA is already optimized out in
1655 * the previous run, so there is no need
1656 * to pad any extra byte (0 byte).
1657 * (2) The previous pass emits an imm8 jmp,
1658 * so we pad 2 bytes to match the previous
1660 * (3) Similarly, the previous pass emits an
1661 * imm32 jmp, and 5 bytes is padded.
1663 nops = INSN_SZ_DIFF;
1664 if (nops != 0 && nops != 2 && nops != 5) {
1665 pr_err("unexpected nop jump padding: %d bytes\n",
1669 emit_nops(&prog, nops);
1674 if (is_imm8(jmp_offset)) {
1676 /* To avoid breaking jmp_offset, the extra bytes
1677 * are padded before the actual jmp insn, so
1678 * 2 bytes is subtracted from INSN_SZ_DIFF.
1680 * If the previous pass already emits an imm8
1681 * jmp, there is nothing to pad (0 byte).
1683 * If it emits an imm32 jmp (5 bytes) previously
1684 * and now an imm8 jmp (2 bytes), then we pad
1685 * (5 - 2 = 3) bytes to stop the image from
1686 * shrinking further.
1688 nops = INSN_SZ_DIFF - 2;
1689 if (nops != 0 && nops != 3) {
1690 pr_err("unexpected jump padding: %d bytes\n",
1694 emit_nops(&prog, INSN_SZ_DIFF - 2);
1696 EMIT2(0xEB, jmp_offset);
1697 } else if (is_simm32(jmp_offset)) {
1698 EMIT1_off32(0xE9, jmp_offset);
1700 pr_err("jmp gen bug %llx\n", jmp_offset);
1705 case BPF_JMP | BPF_EXIT:
1707 jmp_offset = ctx->cleanup_addr - addrs[i];
1711 /* Update cleanup_addr */
1712 ctx->cleanup_addr = proglen;
1713 pop_callee_regs(&prog, callee_regs_used);
1714 EMIT1(0xC9); /* leave */
1715 emit_return(&prog, image + addrs[i - 1] + (prog - temp));
1720 * By design x86-64 JIT should support all BPF instructions.
1721 * This error will be seen if new instruction was added
1722 * to the interpreter, but not to the JIT, or if there is
1725 pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1730 if (ilen > BPF_MAX_INSN_SIZE) {
1731 pr_err("bpf_jit: fatal insn size error\n");
1737 * When populating the image, assert that:
1739 * i) We do not write beyond the allocated space, and
1740 * ii) addrs[i] did not change from the prior run, in order
1741 * to validate assumptions made for computing branch
1744 if (unlikely(proglen + ilen > oldproglen ||
1745 proglen + ilen != addrs[i])) {
1746 pr_err("bpf_jit: fatal error\n");
1749 memcpy(rw_image + proglen, temp, ilen);
1756 if (image && excnt != bpf_prog->aux->num_exentries) {
1757 pr_err("extable is not populated\n");
1763 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_regs,
1768 /* Store function arguments to stack.
1769 * For a function that accepts two pointers the sequence will be:
1770 * mov QWORD PTR [rbp-0x10],rdi
1771 * mov QWORD PTR [rbp-0x8],rsi
1773 for (i = 0; i < min(nr_regs, 6); i++)
1774 emit_stx(prog, BPF_DW, BPF_REG_FP,
1775 i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1776 -(stack_size - i * 8));
1779 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_regs,
1784 /* Restore function arguments from stack.
1785 * For a function that accepts two pointers the sequence will be:
1786 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1787 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1789 for (i = 0; i < min(nr_regs, 6); i++)
1790 emit_ldx(prog, BPF_DW,
1791 i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1793 -(stack_size - i * 8));
1796 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1797 struct bpf_tramp_link *l, int stack_size,
1798 int run_ctx_off, bool save_ret)
1802 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
1803 struct bpf_prog *p = l->link.prog;
1804 u64 cookie = l->cookie;
1806 /* mov rdi, cookie */
1807 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie);
1809 /* Prepare struct bpf_tramp_run_ctx.
1811 * bpf_tramp_run_ctx is already preserved by
1812 * arch_prepare_bpf_trampoline().
1814 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi
1816 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
1818 /* arg1: mov rdi, progs[i] */
1819 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1820 /* arg2: lea rsi, [rbp - ctx_cookie_off] */
1821 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off);
1823 if (emit_call(&prog, bpf_trampoline_enter(p), prog))
1825 /* remember prog start time returned by __bpf_prog_enter */
1826 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1828 /* if (__bpf_prog_enter*(prog) == 0)
1829 * goto skip_exec_of_prog;
1831 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */
1832 /* emit 2 nops that will be replaced with JE insn */
1834 emit_nops(&prog, 2);
1836 /* arg1: lea rdi, [rbp - stack_size] */
1837 EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1838 /* arg2: progs[i]->insnsi for interpreter */
1840 emit_mov_imm64(&prog, BPF_REG_2,
1841 (long) p->insnsi >> 32,
1842 (u32) (long) p->insnsi);
1843 /* call JITed bpf program or interpreter */
1844 if (emit_call(&prog, p->bpf_func, prog))
1848 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1849 * of the previous call which is then passed on the stack to
1850 * the next BPF program.
1852 * BPF_TRAMP_FENTRY trampoline may need to return the return
1853 * value of BPF_PROG_TYPE_STRUCT_OPS prog.
1856 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1858 /* replace 2 nops with JE insn, since jmp target is known */
1859 jmp_insn[0] = X86_JE;
1860 jmp_insn[1] = prog - jmp_insn - 2;
1862 /* arg1: mov rdi, progs[i] */
1863 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1864 /* arg2: mov rsi, rbx <- start time in nsec */
1865 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1866 /* arg3: lea rdx, [rbp - run_ctx_off] */
1867 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off);
1868 if (emit_call(&prog, bpf_trampoline_exit(p), prog))
1875 static void emit_align(u8 **pprog, u32 align)
1877 u8 *target, *prog = *pprog;
1879 target = PTR_ALIGN(prog, align);
1881 emit_nops(&prog, target - prog);
1886 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
1891 offset = func - (ip + 2 + 4);
1892 if (!is_simm32(offset)) {
1893 pr_err("Target %p is out of range\n", func);
1896 EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
1901 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
1902 struct bpf_tramp_links *tl, int stack_size,
1903 int run_ctx_off, bool save_ret)
1908 for (i = 0; i < tl->nr_links; i++) {
1909 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size,
1910 run_ctx_off, save_ret))
1917 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
1918 struct bpf_tramp_links *tl, int stack_size,
1919 int run_ctx_off, u8 **branches)
1924 /* The first fmod_ret program will receive a garbage return value.
1925 * Set this to 0 to avoid confusing the program.
1927 emit_mov_imm32(&prog, false, BPF_REG_0, 0);
1928 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1929 for (i = 0; i < tl->nr_links; i++) {
1930 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true))
1933 /* mod_ret prog stored return value into [rbp - 8]. Emit:
1934 * if (*(u64 *)(rbp - 8) != 0)
1937 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
1938 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
1940 /* Save the location of the branch and Generate 6 nops
1941 * (4 bytes for an offset and 2 bytes for the jump) These nops
1942 * are replaced with a conditional jump once do_fexit (i.e. the
1943 * start of the fexit invocation) is finalized.
1946 emit_nops(&prog, 4 + 2);
1954 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
1955 * its 'struct btf_func_model' will be nr_args=2
1956 * The assembly code when eth_type_trans is executing after trampoline:
1960 * sub rsp, 16 // space for skb and dev
1961 * push rbx // temp regs to pass start time
1962 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack
1963 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack
1964 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
1965 * mov rbx, rax // remember start time in bpf stats are enabled
1966 * lea rdi, [rbp - 16] // R1==ctx of bpf prog
1967 * call addr_of_jited_FENTRY_prog
1968 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
1969 * mov rsi, rbx // prog start time
1970 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
1971 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack
1972 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack
1977 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
1978 * replaced with 'call generated_bpf_trampoline'. When it returns
1979 * eth_type_trans will continue executing with original skb and dev pointers.
1981 * The assembly code when eth_type_trans is called from trampoline:
1985 * sub rsp, 24 // space for skb, dev, return value
1986 * push rbx // temp regs to pass start time
1987 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack
1988 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack
1989 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
1990 * mov rbx, rax // remember start time if bpf stats are enabled
1991 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
1992 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev
1993 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
1994 * mov rsi, rbx // prog start time
1995 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
1996 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack
1997 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack
1998 * call eth_type_trans+5 // execute body of eth_type_trans
1999 * mov qword ptr [rbp - 8], rax // save return value
2000 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2001 * mov rbx, rax // remember start time in bpf stats are enabled
2002 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
2003 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value
2004 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2005 * mov rsi, rbx // prog start time
2006 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2007 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value
2010 * add rsp, 8 // skip eth_type_trans's frame
2011 * ret // return to its caller
2013 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
2014 const struct btf_func_model *m, u32 flags,
2015 struct bpf_tramp_links *tlinks,
2018 int i, ret, nr_regs = m->nr_args, stack_size = 0;
2019 int regs_off, nregs_off, ip_off, run_ctx_off;
2020 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2021 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2022 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2023 void *orig_call = func_addr;
2024 u8 **branches = NULL;
2028 /* extra registers for struct arguments */
2029 for (i = 0; i < m->nr_args; i++)
2030 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
2031 nr_regs += (m->arg_size[i] + 7) / 8 - 1;
2033 /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
2037 /* Generated trampoline stack layout:
2039 * RBP + 8 [ return address ]
2042 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or
2043 * BPF_TRAMP_F_RET_FENTRY_RET flags
2045 * [ reg_argN ] always
2047 * RBP - regs_off [ reg_arg1 ] program's ctx pointer
2049 * RBP - nregs_off [ regs count ] always
2051 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag
2053 * RBP - run_ctx_off [ bpf_tramp_run_ctx ]
2054 * RSP [ tail_call_cnt ] BPF_TRAMP_F_TAIL_CALL_CTX
2057 /* room for return value of orig_call or fentry prog */
2058 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2062 stack_size += nr_regs * 8;
2063 regs_off = stack_size;
2067 nregs_off = stack_size;
2069 if (flags & BPF_TRAMP_F_IP_ARG)
2070 stack_size += 8; /* room for IP address argument */
2072 ip_off = stack_size;
2074 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7;
2075 run_ctx_off = stack_size;
2077 if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2078 /* skip patched call instruction and point orig_call to actual
2079 * body of the kernel function.
2081 if (is_endbr(*(u32 *)orig_call))
2082 orig_call += ENDBR_INSN_SIZE;
2083 orig_call += X86_PATCH_SIZE;
2089 EMIT1(0x55); /* push rbp */
2090 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2091 EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
2092 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
2093 EMIT1(0x50); /* push rax */
2094 EMIT1(0x53); /* push rbx */
2096 /* Store number of argument registers of the traced function:
2098 * mov QWORD PTR [rbp - nregs_off], rax
2100 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs);
2101 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off);
2103 if (flags & BPF_TRAMP_F_IP_ARG) {
2104 /* Store IP address of the traced function:
2105 * movabsq rax, func_addr
2106 * mov QWORD PTR [rbp - ip_off], rax
2108 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr);
2109 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off);
2112 save_regs(m, &prog, nr_regs, regs_off);
2114 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2115 /* arg1: mov rdi, im */
2116 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2117 if (emit_call(&prog, __bpf_tramp_enter, prog)) {
2123 if (fentry->nr_links)
2124 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off,
2125 flags & BPF_TRAMP_F_RET_FENTRY_RET))
2128 if (fmod_ret->nr_links) {
2129 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *),
2134 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off,
2135 run_ctx_off, branches)) {
2141 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2142 restore_regs(m, &prog, nr_regs, regs_off);
2144 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
2145 /* Before calling the original function, restore the
2146 * tail_call_cnt from stack to rax.
2148 RESTORE_TAIL_CALL_CNT(stack_size);
2150 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2151 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8);
2152 EMIT2(0xff, 0xd3); /* call *rbx */
2154 /* call original function */
2155 if (emit_call(&prog, orig_call, prog)) {
2160 /* remember return value in a stack for bpf prog to access */
2161 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2162 im->ip_after_call = prog;
2163 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2164 prog += X86_PATCH_SIZE;
2167 if (fmod_ret->nr_links) {
2168 /* From Intel 64 and IA-32 Architectures Optimization
2169 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2170 * Coding Rule 11: All branch targets should be 16-byte
2173 emit_align(&prog, 16);
2174 /* Update the branches saved in invoke_bpf_mod_ret with the
2175 * aligned address of do_fexit.
2177 for (i = 0; i < fmod_ret->nr_links; i++)
2178 emit_cond_near_jump(&branches[i], prog, branches[i],
2182 if (fexit->nr_links)
2183 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) {
2188 if (flags & BPF_TRAMP_F_RESTORE_REGS)
2189 restore_regs(m, &prog, nr_regs, regs_off);
2191 /* This needs to be done regardless. If there were fmod_ret programs,
2192 * the return value is only updated on the stack and still needs to be
2195 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2196 im->ip_epilogue = prog;
2197 /* arg1: mov rdi, im */
2198 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2199 if (emit_call(&prog, __bpf_tramp_exit, prog)) {
2203 } else if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
2204 /* Before running the original function, restore the
2205 * tail_call_cnt from stack to rax.
2207 RESTORE_TAIL_CALL_CNT(stack_size);
2209 /* restore return value of orig_call or fentry prog back into RAX */
2211 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2213 EMIT1(0x5B); /* pop rbx */
2214 EMIT1(0xC9); /* leave */
2215 if (flags & BPF_TRAMP_F_SKIP_FRAME)
2216 /* skip our return address and return to parent */
2217 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2218 emit_return(&prog, prog);
2219 /* Make sure the trampoline generation logic doesn't overflow */
2220 if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2224 ret = prog - (u8 *)image;
2231 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf)
2233 u8 *jg_reloc, *prog = *pprog;
2234 int pivot, err, jg_bytes = 1;
2238 /* Leaf node of recursion, i.e. not a range of indices
2241 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2242 if (!is_simm32(progs[a]))
2244 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2246 err = emit_cond_near_jump(&prog, /* je func */
2247 (void *)progs[a], image + (prog - buf),
2252 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf));
2258 /* Not a leaf node, so we pivot, and recursively descend into
2259 * the lower and upper ranges.
2261 pivot = (b - a) / 2;
2262 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2263 if (!is_simm32(progs[a + pivot]))
2265 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2267 if (pivot > 2) { /* jg upper_part */
2268 /* Require near jump. */
2270 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2276 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */
2281 /* From Intel 64 and IA-32 Architectures Optimization
2282 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2283 * Coding Rule 11: All branch targets should be 16-byte
2286 emit_align(&prog, 16);
2287 jg_offset = prog - jg_reloc;
2288 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2290 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2291 b, progs, image, buf);
2299 static int cmp_ips(const void *a, const void *b)
2311 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs)
2315 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2316 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf);
2319 struct x64_jit_data {
2320 struct bpf_binary_header *rw_header;
2321 struct bpf_binary_header *header;
2325 struct jit_context ctx;
2328 #define MAX_PASSES 20
2329 #define PADDING_PASSES (MAX_PASSES - 5)
2331 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2333 struct bpf_binary_header *rw_header = NULL;
2334 struct bpf_binary_header *header = NULL;
2335 struct bpf_prog *tmp, *orig_prog = prog;
2336 struct x64_jit_data *jit_data;
2337 int proglen, oldproglen = 0;
2338 struct jit_context ctx = {};
2339 bool tmp_blinded = false;
2340 bool extra_pass = false;
2341 bool padding = false;
2342 u8 *rw_image = NULL;
2348 if (!prog->jit_requested)
2351 tmp = bpf_jit_blind_constants(prog);
2353 * If blinding was requested and we failed during blinding,
2354 * we must fall back to the interpreter.
2363 jit_data = prog->aux->jit_data;
2365 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2370 prog->aux->jit_data = jit_data;
2372 addrs = jit_data->addrs;
2374 ctx = jit_data->ctx;
2375 oldproglen = jit_data->proglen;
2376 image = jit_data->image;
2377 header = jit_data->header;
2378 rw_header = jit_data->rw_header;
2379 rw_image = (void *)rw_header + ((void *)image - (void *)header);
2382 goto skip_init_addrs;
2384 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2391 * Before first pass, make a rough estimation of addrs[]
2392 * each BPF instruction is translated to less than 64 bytes
2394 for (proglen = 0, i = 0; i <= prog->len; i++) {
2398 ctx.cleanup_addr = proglen;
2402 * JITed image shrinks with every pass and the loop iterates
2403 * until the image stops shrinking. Very large BPF programs
2404 * may converge on the last pass. In such case do one more
2405 * pass to emit the final image.
2407 for (pass = 0; pass < MAX_PASSES || image; pass++) {
2408 if (!padding && pass >= PADDING_PASSES)
2410 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding);
2415 bpf_arch_text_copy(&header->size, &rw_header->size,
2416 sizeof(rw_header->size));
2417 bpf_jit_binary_pack_free(header, rw_header);
2419 /* Fall back to interpreter mode */
2422 prog->bpf_func = NULL;
2424 prog->jited_len = 0;
2429 if (proglen != oldproglen) {
2430 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2431 proglen, oldproglen);
2436 if (proglen == oldproglen) {
2438 * The number of entries in extable is the number of BPF_LDX
2439 * insns that access kernel memory via "pointer to BTF type".
2440 * The verifier changed their opcode from LDX|MEM|size
2441 * to LDX|PROBE_MEM|size to make JITing easier.
2443 u32 align = __alignof__(struct exception_table_entry);
2444 u32 extable_size = prog->aux->num_exentries *
2445 sizeof(struct exception_table_entry);
2447 /* allocate module memory for x86 insns and extable */
2448 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size,
2449 &image, align, &rw_header, &rw_image,
2455 prog->aux->extable = (void *) image + roundup(proglen, align);
2457 oldproglen = proglen;
2461 if (bpf_jit_enable > 1)
2462 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image);
2465 if (!prog->is_func || extra_pass) {
2467 * bpf_jit_binary_pack_finalize fails in two scenarios:
2468 * 1) header is not pointing to proper module memory;
2469 * 2) the arch doesn't support bpf_arch_text_copy().
2471 * Both cases are serious bugs and justify WARN_ON.
2473 if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) {
2474 /* header has been freed */
2479 bpf_tail_call_direct_fixup(prog);
2481 jit_data->addrs = addrs;
2482 jit_data->ctx = ctx;
2483 jit_data->proglen = proglen;
2484 jit_data->image = image;
2485 jit_data->header = header;
2486 jit_data->rw_header = rw_header;
2488 prog->bpf_func = (void *)image;
2490 prog->jited_len = proglen;
2495 if (!image || !prog->is_func || extra_pass) {
2497 bpf_prog_fill_jited_linfo(prog, addrs + 1);
2501 prog->aux->jit_data = NULL;
2505 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2510 bool bpf_jit_supports_kfunc_call(void)
2515 void *bpf_arch_text_copy(void *dst, void *src, size_t len)
2517 if (text_poke_copy(dst, src, len) == NULL)
2518 return ERR_PTR(-EINVAL);
2522 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
2523 bool bpf_jit_supports_subprog_tailcalls(void)
2528 void bpf_jit_free(struct bpf_prog *prog)
2531 struct x64_jit_data *jit_data = prog->aux->jit_data;
2532 struct bpf_binary_header *hdr;
2535 * If we fail the final pass of JIT (from jit_subprogs),
2536 * the program may not be finalized yet. Call finalize here
2537 * before freeing it.
2540 bpf_jit_binary_pack_finalize(prog, jit_data->header,
2541 jit_data->rw_header);
2542 kvfree(jit_data->addrs);
2545 hdr = bpf_jit_binary_pack_hdr(prog);
2546 bpf_jit_binary_pack_free(hdr, NULL);
2547 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog));
2550 bpf_prog_unlock_free(prog);
2553 void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke,
2554 struct bpf_prog *new, struct bpf_prog *old)
2556 u8 *old_addr, *new_addr, *old_bypass_addr;
2559 old_bypass_addr = old ? NULL : poke->bypass_addr;
2560 old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL;
2561 new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL;
2564 * On program loading or teardown, the program's kallsym entry
2565 * might not be in place, so we use __bpf_arch_text_poke to skip
2566 * the kallsyms check.
2569 ret = __bpf_arch_text_poke(poke->tailcall_target,
2571 old_addr, new_addr);
2574 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
2581 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
2586 /* let other CPUs finish the execution of program
2587 * so that it will not possible to expose them
2588 * to invalid nop, stack unwind, nop state
2592 ret = __bpf_arch_text_poke(poke->tailcall_target,