1 // SPDX-License-Identifier: GPL-2.0-only
3 * Page Attribute Table (PAT) support: handle memory caching attributes in page tables.
5 * Authors: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
6 * Suresh B Siddha <suresh.b.siddha@intel.com>
8 * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen.
12 * PAT is a CPU feature supported by all modern x86 CPUs, to allow the firmware and
13 * the kernel to set one of a handful of 'caching type' attributes for physical
14 * memory ranges: uncached, write-combining, write-through, write-protected,
15 * and the most commonly used and default attribute: write-back caching.
17 * PAT support supercedes and augments MTRR support in a compatible fashion: MTRR is
18 * a hardware interface to enumerate a limited number of physical memory ranges
19 * and set their caching attributes explicitly, programmed into the CPU via MSRs.
20 * Even modern CPUs have MTRRs enabled - but these are typically not touched
21 * by the kernel or by user-space (such as the X server), we rely on PAT for any
22 * additional cache attribute logic.
24 * PAT doesn't work via explicit memory ranges, but uses page table entries to add
25 * cache attribute information to the mapped memory range: there's 3 bits used,
26 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT), with the 8 possible values mapped by the
27 * CPU to actual cache attributes via an MSR loaded into the CPU (MSR_IA32_CR_PAT).
29 * ( There's a metric ton of finer details, such as compatibility with CPU quirks
30 * that only support 4 types of PAT entries, and interaction with MTRRs, see
31 * below for details. )
34 #include <linux/seq_file.h>
35 #include <linux/memblock.h>
36 #include <linux/debugfs.h>
37 #include <linux/ioport.h>
38 #include <linux/kernel.h>
39 #include <linux/pfn_t.h>
40 #include <linux/slab.h>
43 #include <linux/rbtree.h>
45 #include <asm/cacheflush.h>
46 #include <asm/processor.h>
47 #include <asm/tlbflush.h>
48 #include <asm/x86_init.h>
49 #include <asm/fcntl.h>
50 #include <asm/e820/api.h>
54 #include <asm/memtype.h>
58 #include "../mm_internal.h"
61 #define pr_fmt(fmt) "" fmt
63 static bool __read_mostly pat_bp_initialized;
64 static bool __read_mostly pat_disabled = !IS_ENABLED(CONFIG_X86_PAT);
65 static bool __initdata pat_force_disabled = !IS_ENABLED(CONFIG_X86_PAT);
66 static bool __read_mostly pat_bp_enabled;
67 static bool __read_mostly pat_cm_initialized;
70 * PAT support is enabled by default, but can be disabled for
71 * various user-requested or hardware-forced reasons:
73 void pat_disable(const char *msg_reason)
78 if (pat_bp_initialized) {
79 WARN_ONCE(1, "x86/PAT: PAT cannot be disabled after initialization\n");
84 pr_info("x86/PAT: %s\n", msg_reason);
87 static int __init nopat(char *str)
89 pat_disable("PAT support disabled via boot option.");
90 pat_force_disabled = true;
93 early_param("nopat", nopat);
95 bool pat_enabled(void)
97 return pat_bp_enabled;
99 EXPORT_SYMBOL_GPL(pat_enabled);
101 int pat_debug_enable;
103 static int __init pat_debug_setup(char *str)
105 pat_debug_enable = 1;
108 __setup("debugpat", pat_debug_setup);
110 #ifdef CONFIG_X86_PAT
112 * X86 PAT uses page flags arch_1 and uncached together to keep track of
113 * memory type of pages that have backing page struct.
115 * X86 PAT supports 4 different memory types:
116 * - _PAGE_CACHE_MODE_WB
117 * - _PAGE_CACHE_MODE_WC
118 * - _PAGE_CACHE_MODE_UC_MINUS
119 * - _PAGE_CACHE_MODE_WT
121 * _PAGE_CACHE_MODE_WB is the default type.
125 #define _PGMT_WC (1UL << PG_arch_1)
126 #define _PGMT_UC_MINUS (1UL << PG_uncached)
127 #define _PGMT_WT (1UL << PG_uncached | 1UL << PG_arch_1)
128 #define _PGMT_MASK (1UL << PG_uncached | 1UL << PG_arch_1)
129 #define _PGMT_CLEAR_MASK (~_PGMT_MASK)
131 static inline enum page_cache_mode get_page_memtype(struct page *pg)
133 unsigned long pg_flags = pg->flags & _PGMT_MASK;
135 if (pg_flags == _PGMT_WB)
136 return _PAGE_CACHE_MODE_WB;
137 else if (pg_flags == _PGMT_WC)
138 return _PAGE_CACHE_MODE_WC;
139 else if (pg_flags == _PGMT_UC_MINUS)
140 return _PAGE_CACHE_MODE_UC_MINUS;
142 return _PAGE_CACHE_MODE_WT;
145 static inline void set_page_memtype(struct page *pg,
146 enum page_cache_mode memtype)
148 unsigned long memtype_flags;
149 unsigned long old_flags;
150 unsigned long new_flags;
153 case _PAGE_CACHE_MODE_WC:
154 memtype_flags = _PGMT_WC;
156 case _PAGE_CACHE_MODE_UC_MINUS:
157 memtype_flags = _PGMT_UC_MINUS;
159 case _PAGE_CACHE_MODE_WT:
160 memtype_flags = _PGMT_WT;
162 case _PAGE_CACHE_MODE_WB:
164 memtype_flags = _PGMT_WB;
169 old_flags = pg->flags;
170 new_flags = (old_flags & _PGMT_CLEAR_MASK) | memtype_flags;
171 } while (cmpxchg(&pg->flags, old_flags, new_flags) != old_flags);
174 static inline enum page_cache_mode get_page_memtype(struct page *pg)
178 static inline void set_page_memtype(struct page *pg,
179 enum page_cache_mode memtype)
185 PAT_UC = 0, /* uncached */
186 PAT_WC = 1, /* Write combining */
187 PAT_WT = 4, /* Write Through */
188 PAT_WP = 5, /* Write Protected */
189 PAT_WB = 6, /* Write Back (default) */
190 PAT_UC_MINUS = 7, /* UC, but can be overridden by MTRR */
193 #define CM(c) (_PAGE_CACHE_MODE_ ## c)
195 static enum page_cache_mode pat_get_cache_mode(unsigned pat_val, char *msg)
197 enum page_cache_mode cache;
201 case PAT_UC: cache = CM(UC); cache_mode = "UC "; break;
202 case PAT_WC: cache = CM(WC); cache_mode = "WC "; break;
203 case PAT_WT: cache = CM(WT); cache_mode = "WT "; break;
204 case PAT_WP: cache = CM(WP); cache_mode = "WP "; break;
205 case PAT_WB: cache = CM(WB); cache_mode = "WB "; break;
206 case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break;
207 default: cache = CM(WB); cache_mode = "WB "; break;
210 memcpy(msg, cache_mode, 4);
218 * Update the cache mode to pgprot translation tables according to PAT
220 * Using lower indices is preferred, so we start with highest index.
222 static void __init_cache_modes(u64 pat)
224 enum page_cache_mode cache;
228 WARN_ON_ONCE(pat_cm_initialized);
231 for (i = 7; i >= 0; i--) {
232 cache = pat_get_cache_mode((pat >> (i * 8)) & 7,
234 update_cache_mode_entry(i, cache);
236 pr_info("x86/PAT: Configuration [0-7]: %s\n", pat_msg);
238 pat_cm_initialized = true;
241 #define PAT(x, y) ((u64)PAT_ ## y << ((x)*8))
243 static void pat_bp_init(u64 pat)
247 if (!boot_cpu_has(X86_FEATURE_PAT)) {
248 pat_disable("PAT not supported by the CPU.");
252 rdmsrl(MSR_IA32_CR_PAT, tmp_pat);
254 pat_disable("PAT support disabled by the firmware.");
258 wrmsrl(MSR_IA32_CR_PAT, pat);
259 pat_bp_enabled = true;
261 __init_cache_modes(pat);
264 static void pat_ap_init(u64 pat)
266 if (!boot_cpu_has(X86_FEATURE_PAT)) {
268 * If this happens we are on a secondary CPU, but switched to
269 * PAT on the boot CPU. We have no way to undo PAT.
271 panic("x86/PAT: PAT enabled, but not supported by secondary CPU\n");
274 wrmsrl(MSR_IA32_CR_PAT, pat);
277 void __init init_cache_modes(void)
281 if (pat_cm_initialized)
284 if (boot_cpu_has(X86_FEATURE_PAT)) {
286 * CPU supports PAT. Set PAT table to be consistent with
287 * PAT MSR. This case supports "nopat" boot option, and
288 * virtual machine environments which support PAT without
289 * MTRRs. In specific, Xen has unique setup to PAT MSR.
291 * If PAT MSR returns 0, it is considered invalid and emulates
294 rdmsrl(MSR_IA32_CR_PAT, pat);
299 * No PAT. Emulate the PAT table that corresponds to the two
300 * cache bits, PWT (Write Through) and PCD (Cache Disable).
301 * This setup is also the same as the BIOS default setup.
308 * 00 0 WB : _PAGE_CACHE_MODE_WB
309 * 01 1 WT : _PAGE_CACHE_MODE_WT
310 * 10 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
311 * 11 3 UC : _PAGE_CACHE_MODE_UC
313 * NOTE: When WC or WP is used, it is redirected to UC- per
314 * the default setup in __cachemode2pte_tbl[].
316 pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) |
317 PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC);
318 } else if (!pat_force_disabled && cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) {
320 * Clearly PAT is enabled underneath. Allow pat_enabled() to
323 pat_bp_enabled = true;
326 __init_cache_modes(pat);
330 * pat_init - Initialize the PAT MSR and PAT table on the current CPU
332 * This function initializes PAT MSR and PAT table with an OS-defined value
333 * to enable additional cache attributes, WC, WT and WP.
335 * This function must be called on all CPUs using the specific sequence of
336 * operations defined in Intel SDM. mtrr_rendezvous_handler() provides this
342 struct cpuinfo_x86 *c = &boot_cpu_data;
344 #ifndef CONFIG_X86_PAT
345 pr_info_once("x86/PAT: PAT support disabled because CONFIG_X86_PAT is disabled in the kernel.\n");
351 if ((c->x86_vendor == X86_VENDOR_INTEL) &&
352 (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
353 ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
355 * PAT support with the lower four entries. Intel Pentium 2,
356 * 3, M, and 4 are affected by PAT errata, which makes the
357 * upper four entries unusable. To be on the safe side, we don't
365 * 000 0 WB : _PAGE_CACHE_MODE_WB
366 * 001 1 WC : _PAGE_CACHE_MODE_WC
367 * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
368 * 011 3 UC : _PAGE_CACHE_MODE_UC
371 * NOTE: When WT or WP is used, it is redirected to UC- per
372 * the default setup in __cachemode2pte_tbl[].
374 pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
375 PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
378 * Full PAT support. We put WT in slot 7 to improve
379 * robustness in the presence of errata that might cause
380 * the high PAT bit to be ignored. This way, a buggy slot 7
381 * access will hit slot 3, and slot 3 is UC, so at worst
382 * we lose performance without causing a correctness issue.
383 * Pentium 4 erratum N46 is an example for such an erratum,
384 * although we try not to use PAT at all on affected CPUs.
391 * 000 0 WB : _PAGE_CACHE_MODE_WB
392 * 001 1 WC : _PAGE_CACHE_MODE_WC
393 * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
394 * 011 3 UC : _PAGE_CACHE_MODE_UC
395 * 100 4 WB : Reserved
396 * 101 5 WP : _PAGE_CACHE_MODE_WP
397 * 110 6 UC-: Reserved
398 * 111 7 WT : _PAGE_CACHE_MODE_WT
400 * The reserved slots are unused, but mapped to their
401 * corresponding types in the presence of PAT errata.
403 pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
404 PAT(4, WB) | PAT(5, WP) | PAT(6, UC_MINUS) | PAT(7, WT);
407 if (!pat_bp_initialized) {
409 pat_bp_initialized = true;
417 static DEFINE_SPINLOCK(memtype_lock); /* protects memtype accesses */
420 * Does intersection of PAT memory type and MTRR memory type and returns
421 * the resulting memory type as PAT understands it.
422 * (Type in pat and mtrr will not have same value)
423 * The intersection is based on "Effective Memory Type" tables in IA-32
426 static unsigned long pat_x_mtrr_type(u64 start, u64 end,
427 enum page_cache_mode req_type)
430 * Look for MTRR hint to get the effective type in case where PAT
433 if (req_type == _PAGE_CACHE_MODE_WB) {
434 u8 mtrr_type, uniform;
436 mtrr_type = mtrr_type_lookup(start, end, &uniform);
437 if (mtrr_type != MTRR_TYPE_WRBACK)
438 return _PAGE_CACHE_MODE_UC_MINUS;
440 return _PAGE_CACHE_MODE_WB;
446 struct pagerange_state {
447 unsigned long cur_pfn;
453 pagerange_is_ram_callback(unsigned long initial_pfn, unsigned long total_nr_pages, void *arg)
455 struct pagerange_state *state = arg;
457 state->not_ram |= initial_pfn > state->cur_pfn;
458 state->ram |= total_nr_pages > 0;
459 state->cur_pfn = initial_pfn + total_nr_pages;
461 return state->ram && state->not_ram;
464 static int pat_pagerange_is_ram(resource_size_t start, resource_size_t end)
467 unsigned long start_pfn = start >> PAGE_SHIFT;
468 unsigned long end_pfn = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
469 struct pagerange_state state = {start_pfn, 0, 0};
472 * For legacy reasons, physical address range in the legacy ISA
473 * region is tracked as non-RAM. This will allow users of
474 * /dev/mem to map portions of legacy ISA region, even when
475 * some of those portions are listed(or not even listed) with
476 * different e820 types(RAM/reserved/..)
478 if (start_pfn < ISA_END_ADDRESS >> PAGE_SHIFT)
479 start_pfn = ISA_END_ADDRESS >> PAGE_SHIFT;
481 if (start_pfn < end_pfn) {
482 ret = walk_system_ram_range(start_pfn, end_pfn - start_pfn,
483 &state, pagerange_is_ram_callback);
486 return (ret > 0) ? -1 : (state.ram ? 1 : 0);
490 * For RAM pages, we use page flags to mark the pages with appropriate type.
491 * The page flags are limited to four types, WB (default), WC, WT and UC-.
492 * WP request fails with -EINVAL, and UC gets redirected to UC-. Setting
493 * a new memory type is only allowed for a page mapped with the default WB
496 * Here we do two passes:
497 * - Find the memtype of all the pages in the range, look for any conflicts.
498 * - In case of no conflicts, set the new memtype for pages in the range.
500 static int reserve_ram_pages_type(u64 start, u64 end,
501 enum page_cache_mode req_type,
502 enum page_cache_mode *new_type)
507 if (req_type == _PAGE_CACHE_MODE_WP) {
509 *new_type = _PAGE_CACHE_MODE_UC_MINUS;
513 if (req_type == _PAGE_CACHE_MODE_UC) {
514 /* We do not support strong UC */
516 req_type = _PAGE_CACHE_MODE_UC_MINUS;
519 for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
520 enum page_cache_mode type;
522 page = pfn_to_page(pfn);
523 type = get_page_memtype(page);
524 if (type != _PAGE_CACHE_MODE_WB) {
525 pr_info("x86/PAT: reserve_ram_pages_type failed [mem %#010Lx-%#010Lx], track 0x%x, req 0x%x\n",
526 start, end - 1, type, req_type);
535 *new_type = req_type;
537 for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
538 page = pfn_to_page(pfn);
539 set_page_memtype(page, req_type);
544 static int free_ram_pages_type(u64 start, u64 end)
549 for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
550 page = pfn_to_page(pfn);
551 set_page_memtype(page, _PAGE_CACHE_MODE_WB);
556 static u64 sanitize_phys(u64 address)
559 * When changing the memtype for pages containing poison allow
560 * for a "decoy" virtual address (bit 63 clear) passed to
561 * set_memory_X(). __pa() on a "decoy" address results in a
562 * physical address with bit 63 set.
564 * Decoy addresses are not present for 32-bit builds, see
567 if (IS_ENABLED(CONFIG_X86_64))
568 return address & __PHYSICAL_MASK;
573 * req_type typically has one of the:
574 * - _PAGE_CACHE_MODE_WB
575 * - _PAGE_CACHE_MODE_WC
576 * - _PAGE_CACHE_MODE_UC_MINUS
577 * - _PAGE_CACHE_MODE_UC
578 * - _PAGE_CACHE_MODE_WT
580 * If new_type is NULL, function will return an error if it cannot reserve the
581 * region with req_type. If new_type is non-NULL, function will return
582 * available type in new_type in case of no error. In case of any error
583 * it will return a negative return value.
585 int memtype_reserve(u64 start, u64 end, enum page_cache_mode req_type,
586 enum page_cache_mode *new_type)
588 struct memtype *entry_new;
589 enum page_cache_mode actual_type;
593 start = sanitize_phys(start);
596 * The end address passed into this function is exclusive, but
597 * sanitize_phys() expects an inclusive address.
599 end = sanitize_phys(end - 1) + 1;
601 WARN(1, "%s failed: [mem %#010Lx-%#010Lx], req %s\n", __func__,
602 start, end - 1, cattr_name(req_type));
606 if (!pat_enabled()) {
607 /* This is identical to page table setting without PAT */
609 *new_type = req_type;
613 /* Low ISA region is always mapped WB in page table. No need to track */
614 if (x86_platform.is_untracked_pat_range(start, end)) {
616 *new_type = _PAGE_CACHE_MODE_WB;
621 * Call mtrr_lookup to get the type hint. This is an
622 * optimization for /dev/mem mmap'ers into WB memory (BIOS
623 * tools and ACPI tools). Use WB request for WB memory and use
624 * UC_MINUS otherwise.
626 actual_type = pat_x_mtrr_type(start, end, req_type);
629 *new_type = actual_type;
631 is_range_ram = pat_pagerange_is_ram(start, end);
632 if (is_range_ram == 1) {
634 err = reserve_ram_pages_type(start, end, req_type, new_type);
637 } else if (is_range_ram < 0) {
641 entry_new = kzalloc(sizeof(struct memtype), GFP_KERNEL);
645 entry_new->start = start;
646 entry_new->end = end;
647 entry_new->type = actual_type;
649 spin_lock(&memtype_lock);
651 err = memtype_check_insert(entry_new, new_type);
653 pr_info("x86/PAT: memtype_reserve failed [mem %#010Lx-%#010Lx], track %s, req %s\n",
655 cattr_name(entry_new->type), cattr_name(req_type));
657 spin_unlock(&memtype_lock);
662 spin_unlock(&memtype_lock);
664 dprintk("memtype_reserve added [mem %#010Lx-%#010Lx], track %s, req %s, ret %s\n",
665 start, end - 1, cattr_name(entry_new->type), cattr_name(req_type),
666 new_type ? cattr_name(*new_type) : "-");
671 int memtype_free(u64 start, u64 end)
674 struct memtype *entry_old;
679 start = sanitize_phys(start);
680 end = sanitize_phys(end);
682 /* Low ISA region is always mapped WB. No need to track */
683 if (x86_platform.is_untracked_pat_range(start, end))
686 is_range_ram = pat_pagerange_is_ram(start, end);
687 if (is_range_ram == 1)
688 return free_ram_pages_type(start, end);
689 if (is_range_ram < 0)
692 spin_lock(&memtype_lock);
693 entry_old = memtype_erase(start, end);
694 spin_unlock(&memtype_lock);
696 if (IS_ERR(entry_old)) {
697 pr_info("x86/PAT: %s:%d freeing invalid memtype [mem %#010Lx-%#010Lx]\n",
698 current->comm, current->pid, start, end - 1);
704 dprintk("memtype_free request [mem %#010Lx-%#010Lx]\n", start, end - 1);
711 * lookup_memtype - Looks up the memory type for a physical address
712 * @paddr: physical address of which memory type needs to be looked up
714 * Only to be called when PAT is enabled
716 * Returns _PAGE_CACHE_MODE_WB, _PAGE_CACHE_MODE_WC, _PAGE_CACHE_MODE_UC_MINUS
717 * or _PAGE_CACHE_MODE_WT.
719 static enum page_cache_mode lookup_memtype(u64 paddr)
721 enum page_cache_mode rettype = _PAGE_CACHE_MODE_WB;
722 struct memtype *entry;
724 if (x86_platform.is_untracked_pat_range(paddr, paddr + PAGE_SIZE))
727 if (pat_pagerange_is_ram(paddr, paddr + PAGE_SIZE)) {
730 page = pfn_to_page(paddr >> PAGE_SHIFT);
731 return get_page_memtype(page);
734 spin_lock(&memtype_lock);
736 entry = memtype_lookup(paddr);
738 rettype = entry->type;
740 rettype = _PAGE_CACHE_MODE_UC_MINUS;
742 spin_unlock(&memtype_lock);
748 * pat_pfn_immune_to_uc_mtrr - Check whether the PAT memory type
749 * of @pfn cannot be overridden by UC MTRR memory type.
751 * Only to be called when PAT is enabled.
753 * Returns true, if the PAT memory type of @pfn is UC, UC-, or WC.
754 * Returns false in other cases.
756 bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn)
758 enum page_cache_mode cm = lookup_memtype(PFN_PHYS(pfn));
760 return cm == _PAGE_CACHE_MODE_UC ||
761 cm == _PAGE_CACHE_MODE_UC_MINUS ||
762 cm == _PAGE_CACHE_MODE_WC;
764 EXPORT_SYMBOL_GPL(pat_pfn_immune_to_uc_mtrr);
767 * memtype_reserve_io - Request a memory type mapping for a region of memory
768 * @start: start (physical address) of the region
769 * @end: end (physical address) of the region
770 * @type: A pointer to memtype, with requested type. On success, requested
771 * or any other compatible type that was available for the region is returned
773 * On success, returns 0
774 * On failure, returns non-zero
776 int memtype_reserve_io(resource_size_t start, resource_size_t end,
777 enum page_cache_mode *type)
779 resource_size_t size = end - start;
780 enum page_cache_mode req_type = *type;
781 enum page_cache_mode new_type;
784 WARN_ON_ONCE(iomem_map_sanity_check(start, size));
786 ret = memtype_reserve(start, end, req_type, &new_type);
790 if (!is_new_memtype_allowed(start, size, req_type, new_type))
793 if (memtype_kernel_map_sync(start, size, new_type) < 0)
800 memtype_free(start, end);
807 * memtype_free_io - Release a memory type mapping for a region of memory
808 * @start: start (physical address) of the region
809 * @end: end (physical address) of the region
811 void memtype_free_io(resource_size_t start, resource_size_t end)
813 memtype_free(start, end);
816 #ifdef CONFIG_X86_PAT
817 int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size)
819 enum page_cache_mode type = _PAGE_CACHE_MODE_WC;
821 return memtype_reserve_io(start, start + size, &type);
823 EXPORT_SYMBOL(arch_io_reserve_memtype_wc);
825 void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size)
827 memtype_free_io(start, start + size);
829 EXPORT_SYMBOL(arch_io_free_memtype_wc);
832 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
833 unsigned long size, pgprot_t vma_prot)
835 if (!phys_mem_access_encrypted(pfn << PAGE_SHIFT, size))
836 vma_prot = pgprot_decrypted(vma_prot);
841 #ifdef CONFIG_STRICT_DEVMEM
842 /* This check is done in drivers/char/mem.c in case of STRICT_DEVMEM */
843 static inline int range_is_allowed(unsigned long pfn, unsigned long size)
848 /* This check is needed to avoid cache aliasing when PAT is enabled */
849 static inline int range_is_allowed(unsigned long pfn, unsigned long size)
851 u64 from = ((u64)pfn) << PAGE_SHIFT;
852 u64 to = from + size;
858 while (cursor < to) {
859 if (!devmem_is_allowed(pfn))
866 #endif /* CONFIG_STRICT_DEVMEM */
868 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
869 unsigned long size, pgprot_t *vma_prot)
871 enum page_cache_mode pcm = _PAGE_CACHE_MODE_WB;
873 if (!range_is_allowed(pfn, size))
876 if (file->f_flags & O_DSYNC)
877 pcm = _PAGE_CACHE_MODE_UC_MINUS;
879 *vma_prot = __pgprot((pgprot_val(*vma_prot) & ~_PAGE_CACHE_MASK) |
880 cachemode2protval(pcm));
885 * Change the memory type for the physical address range in kernel identity
886 * mapping space if that range is a part of identity map.
888 int memtype_kernel_map_sync(u64 base, unsigned long size,
889 enum page_cache_mode pcm)
893 if (base > __pa(high_memory-1))
897 * Some areas in the middle of the kernel identity range
898 * are not mapped, for example the PCI space.
900 if (!page_is_ram(base >> PAGE_SHIFT))
903 id_sz = (__pa(high_memory-1) <= base + size) ?
904 __pa(high_memory) - base : size;
906 if (ioremap_change_attr((unsigned long)__va(base), id_sz, pcm) < 0) {
907 pr_info("x86/PAT: %s:%d ioremap_change_attr failed %s for [mem %#010Lx-%#010Lx]\n",
908 current->comm, current->pid,
910 base, (unsigned long long)(base + size-1));
917 * Internal interface to reserve a range of physical memory with prot.
918 * Reserved non RAM regions only and after successful memtype_reserve,
919 * this func also keeps identity mapping (if any) in sync with this new prot.
921 static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot,
926 enum page_cache_mode want_pcm = pgprot2cachemode(*vma_prot);
927 enum page_cache_mode pcm = want_pcm;
929 is_ram = pat_pagerange_is_ram(paddr, paddr + size);
932 * reserve_pfn_range() for RAM pages. We do not refcount to keep
933 * track of number of mappings of RAM pages. We can assert that
934 * the type requested matches the type of first page in the range.
940 pcm = lookup_memtype(paddr);
941 if (want_pcm != pcm) {
942 pr_warn("x86/PAT: %s:%d map pfn RAM range req %s for [mem %#010Lx-%#010Lx], got %s\n",
943 current->comm, current->pid,
944 cattr_name(want_pcm),
945 (unsigned long long)paddr,
946 (unsigned long long)(paddr + size - 1),
948 *vma_prot = __pgprot((pgprot_val(*vma_prot) &
949 (~_PAGE_CACHE_MASK)) |
950 cachemode2protval(pcm));
955 ret = memtype_reserve(paddr, paddr + size, want_pcm, &pcm);
959 if (pcm != want_pcm) {
961 !is_new_memtype_allowed(paddr, size, want_pcm, pcm)) {
962 memtype_free(paddr, paddr + size);
963 pr_err("x86/PAT: %s:%d map pfn expected mapping type %s for [mem %#010Lx-%#010Lx], got %s\n",
964 current->comm, current->pid,
965 cattr_name(want_pcm),
966 (unsigned long long)paddr,
967 (unsigned long long)(paddr + size - 1),
972 * We allow returning different type than the one requested in
975 *vma_prot = __pgprot((pgprot_val(*vma_prot) &
976 (~_PAGE_CACHE_MASK)) |
977 cachemode2protval(pcm));
980 if (memtype_kernel_map_sync(paddr, size, pcm) < 0) {
981 memtype_free(paddr, paddr + size);
988 * Internal interface to free a range of physical memory.
989 * Frees non RAM regions only.
991 static void free_pfn_range(u64 paddr, unsigned long size)
995 is_ram = pat_pagerange_is_ram(paddr, paddr + size);
997 memtype_free(paddr, paddr + size);
1000 static int get_pat_info(struct vm_area_struct *vma, resource_size_t *paddr,
1005 VM_WARN_ON_ONCE(!(vma->vm_flags & VM_PAT));
1008 * We need the starting PFN and cachemode used for track_pfn_remap()
1009 * that covered the whole VMA. For most mappings, we can obtain that
1010 * information from the page tables. For COW mappings, we might now
1011 * suddenly have anon folios mapped and follow_phys() will fail.
1013 * Fallback to using vma->vm_pgoff, see remap_pfn_range_notrack(), to
1014 * detect the PFN. If we need the cachemode as well, we're out of luck
1015 * for now and have to fail fork().
1017 if (!follow_phys(vma, vma->vm_start, 0, &prot, paddr)) {
1019 *pgprot = __pgprot(prot);
1022 if (is_cow_mapping(vma->vm_flags)) {
1025 *paddr = (resource_size_t)vma->vm_pgoff << PAGE_SHIFT;
1033 * track_pfn_copy is called when vma that is covering the pfnmap gets
1034 * copied through copy_page_range().
1036 * If the vma has a linear pfn mapping for the entire range, we get the prot
1037 * from pte and reserve the entire vma range with single reserve_pfn_range call.
1039 int track_pfn_copy(struct vm_area_struct *vma)
1041 resource_size_t paddr;
1042 unsigned long vma_size = vma->vm_end - vma->vm_start;
1045 if (vma->vm_flags & VM_PAT) {
1046 if (get_pat_info(vma, &paddr, &pgprot))
1048 /* reserve the whole chunk covered by vma. */
1049 return reserve_pfn_range(paddr, vma_size, &pgprot, 1);
1056 * prot is passed in as a parameter for the new mapping. If the vma has
1057 * a linear pfn mapping for the entire range, or no vma is provided,
1058 * reserve the entire pfn + size range with single reserve_pfn_range
1061 int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
1062 unsigned long pfn, unsigned long addr, unsigned long size)
1064 resource_size_t paddr = (resource_size_t)pfn << PAGE_SHIFT;
1065 enum page_cache_mode pcm;
1067 /* reserve the whole chunk starting from paddr */
1068 if (!vma || (addr == vma->vm_start
1069 && size == (vma->vm_end - vma->vm_start))) {
1072 ret = reserve_pfn_range(paddr, size, prot, 0);
1073 if (ret == 0 && vma)
1074 vma->vm_flags |= VM_PAT;
1082 * For anything smaller than the vma size we set prot based on the
1085 pcm = lookup_memtype(paddr);
1087 /* Check memtype for the remaining pages */
1088 while (size > PAGE_SIZE) {
1091 if (pcm != lookup_memtype(paddr))
1095 *prot = __pgprot((pgprot_val(*prot) & (~_PAGE_CACHE_MASK)) |
1096 cachemode2protval(pcm));
1101 void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, pfn_t pfn)
1103 enum page_cache_mode pcm;
1108 /* Set prot based on lookup */
1109 pcm = lookup_memtype(pfn_t_to_phys(pfn));
1110 *prot = __pgprot((pgprot_val(*prot) & (~_PAGE_CACHE_MASK)) |
1111 cachemode2protval(pcm));
1115 * untrack_pfn is called while unmapping a pfnmap for a region.
1116 * untrack can be called for a specific region indicated by pfn and size or
1117 * can be for the entire vma (in which case pfn, size are zero).
1119 void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
1122 resource_size_t paddr;
1124 if (vma && !(vma->vm_flags & VM_PAT))
1127 /* free the chunk starting from pfn or the whole chunk */
1128 paddr = (resource_size_t)pfn << PAGE_SHIFT;
1129 if (!paddr && !size) {
1130 if (get_pat_info(vma, &paddr, NULL))
1132 size = vma->vm_end - vma->vm_start;
1134 free_pfn_range(paddr, size);
1136 vma->vm_flags &= ~VM_PAT;
1140 * untrack_pfn_moved is called, while mremapping a pfnmap for a new region,
1141 * with the old vma after its pfnmap page table has been removed. The new
1142 * vma has a new pfnmap to the same pfn & cache type with VM_PAT set.
1144 void untrack_pfn_moved(struct vm_area_struct *vma)
1146 vma->vm_flags &= ~VM_PAT;
1149 pgprot_t pgprot_writecombine(pgprot_t prot)
1151 return __pgprot(pgprot_val(prot) |
1152 cachemode2protval(_PAGE_CACHE_MODE_WC));
1154 EXPORT_SYMBOL_GPL(pgprot_writecombine);
1156 pgprot_t pgprot_writethrough(pgprot_t prot)
1158 return __pgprot(pgprot_val(prot) |
1159 cachemode2protval(_PAGE_CACHE_MODE_WT));
1161 EXPORT_SYMBOL_GPL(pgprot_writethrough);
1163 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_X86_PAT)
1166 * We are allocating a temporary printout-entry to be passed
1167 * between seq_start()/next() and seq_show():
1169 static struct memtype *memtype_get_idx(loff_t pos)
1171 struct memtype *entry_print;
1174 entry_print = kzalloc(sizeof(struct memtype), GFP_KERNEL);
1178 spin_lock(&memtype_lock);
1179 ret = memtype_copy_nth_element(entry_print, pos);
1180 spin_unlock(&memtype_lock);
1182 /* Free it on error: */
1191 static void *memtype_seq_start(struct seq_file *seq, loff_t *pos)
1195 seq_puts(seq, "PAT memtype list:\n");
1198 return memtype_get_idx(*pos);
1201 static void *memtype_seq_next(struct seq_file *seq, void *v, loff_t *pos)
1205 return memtype_get_idx(*pos);
1208 static void memtype_seq_stop(struct seq_file *seq, void *v)
1213 static int memtype_seq_show(struct seq_file *seq, void *v)
1215 struct memtype *entry_print = (struct memtype *)v;
1217 seq_printf(seq, "PAT: [mem 0x%016Lx-0x%016Lx] %s\n",
1220 cattr_name(entry_print->type));
1225 static const struct seq_operations memtype_seq_ops = {
1226 .start = memtype_seq_start,
1227 .next = memtype_seq_next,
1228 .stop = memtype_seq_stop,
1229 .show = memtype_seq_show,
1232 static int memtype_seq_open(struct inode *inode, struct file *file)
1234 return seq_open(file, &memtype_seq_ops);
1237 static const struct file_operations memtype_fops = {
1238 .open = memtype_seq_open,
1240 .llseek = seq_lseek,
1241 .release = seq_release,
1244 static int __init pat_memtype_list_init(void)
1246 if (pat_enabled()) {
1247 debugfs_create_file("pat_memtype_list", S_IRUSR,
1248 arch_debugfs_dir, NULL, &memtype_fops);
1252 late_initcall(pat_memtype_list_init);
1254 #endif /* CONFIG_DEBUG_FS && CONFIG_X86_PAT */