1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/kexec.h>
57 #include <linux/numa.h>
58 #include <linux/pgtable.h>
59 #include <linux/overflow.h>
65 #include <asm/realmode.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/api.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
82 #include <asm/spec-ctrl.h>
83 #include <asm/hw_irq.h>
84 #include <asm/stackprotector.h>
87 /* representing HT siblings of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
89 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
91 /* representing HT and core siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
95 /* representing HT, core, and die siblings of each logical CPU */
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
97 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
101 EXPORT_PER_CPU_SYMBOL(cpu_info);
103 struct mwait_cpu_dead {
104 unsigned int control;
108 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF
109 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD
112 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
113 * that it's unlikely to be touched by other CPUs.
115 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
117 /* Logical package management. We might want to allocate that dynamically */
118 unsigned int __max_logical_packages __read_mostly;
119 EXPORT_SYMBOL(__max_logical_packages);
120 static unsigned int logical_packages __read_mostly;
121 static unsigned int logical_die __read_mostly;
123 /* Maximum number of SMT threads on any online core */
124 int __read_mostly __max_smt_threads = 1;
126 /* Flag to indicate if a complete sched domain rebuild is required */
127 bool x86_topology_update;
129 int arch_update_cpu_topology(void)
131 int retval = x86_topology_update;
133 x86_topology_update = false;
137 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
141 spin_lock_irqsave(&rtc_lock, flags);
142 CMOS_WRITE(0xa, 0xf);
143 spin_unlock_irqrestore(&rtc_lock, flags);
144 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
146 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
150 static inline void smpboot_restore_warm_reset_vector(void)
155 * Paranoid: Set warm reset code and vector here back
158 spin_lock_irqsave(&rtc_lock, flags);
160 spin_unlock_irqrestore(&rtc_lock, flags);
162 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
166 * Report back to the Boot Processor during boot time or to the caller processor
169 static void smp_callin(void)
173 /* Mop up eventual mwait_play_dead() wreckage */
174 this_cpu_write(mwait_cpu_dead.status, 0);
175 this_cpu_write(mwait_cpu_dead.control, 0);
178 * If waken up by an INIT in an 82489DX configuration
179 * cpu_callout_mask guarantees we don't get here before
180 * an INIT_deassert IPI reaches our local APIC, so it is
181 * now safe to touch our local APIC.
183 cpuid = smp_processor_id();
186 * the boot CPU has finished the init stage and is spinning
187 * on callin_map until we finish. We are free to set up this
188 * CPU, first the APIC. (this is probably redundant on most
194 * Save our processor parameters. Note: this information
195 * is needed for clock calibration.
197 smp_store_cpu_info(cpuid);
200 * The topology information must be up to date before
201 * calibrate_delay() and notify_cpu_starting().
203 set_cpu_sibling_map(raw_smp_processor_id());
205 ap_init_aperfmperf();
209 * Update loops_per_jiffy in cpu_data. Previous call to
210 * smp_store_cpu_info() stored a value that is close but not as
211 * accurate as the value just calculated.
214 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
215 pr_debug("Stack at about %p\n", &cpuid);
219 notify_cpu_starting(cpuid);
222 * Allow the master to continue.
224 cpumask_set_cpu(cpuid, cpu_callin_mask);
227 static int cpu0_logical_apicid;
228 static int enable_start_cpu0;
230 * Activate a secondary processor.
232 static void notrace start_secondary(void *unused)
235 * Don't put *anything* except direct CPU state initialization
236 * before cpu_init(), SMP booting is too fragile that we want to
237 * limit the things done here to the most necessary things.
242 /* switch away from the initial page table */
243 load_cr3(swapper_pg_dir);
246 cpu_init_secondary();
247 rcu_cpu_starting(raw_smp_processor_id());
248 x86_cpuinit.early_percpu_clock_init();
251 enable_start_cpu0 = 0;
253 /* otherwise gcc will move up smp_processor_id before the cpu_init */
256 * Check TSC synchronization with the boot CPU:
258 check_tsc_sync_target();
260 speculative_store_bypass_ht_init();
263 * Lock vector_lock, set CPU online and bring the vector
264 * allocator online. Online must be set with vector_lock held
265 * to prevent a concurrent irq setup/teardown from seeing a
266 * half valid vector space.
269 set_cpu_online(smp_processor_id(), true);
271 unlock_vector_lock();
272 cpu_set_state_online(smp_processor_id());
273 x86_platform.nmi_init();
275 /* enable local interrupts */
278 x86_cpuinit.setup_percpu_clockev();
281 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
285 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
288 bool topology_is_primary_thread(unsigned int cpu)
290 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
294 * topology_smt_supported - Check whether SMT is supported by the CPUs
296 bool topology_smt_supported(void)
298 return smp_num_siblings > 1;
302 * topology_phys_to_logical_pkg - Map a physical package id to a logical
304 * Returns logical package id or -1 if not found
306 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
310 for_each_possible_cpu(cpu) {
311 struct cpuinfo_x86 *c = &cpu_data(cpu);
313 if (c->initialized && c->phys_proc_id == phys_pkg)
314 return c->logical_proc_id;
318 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
320 * topology_phys_to_logical_die - Map a physical die id to logical
322 * Returns logical die id or -1 if not found
324 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
327 int proc_id = cpu_data(cur_cpu).phys_proc_id;
329 for_each_possible_cpu(cpu) {
330 struct cpuinfo_x86 *c = &cpu_data(cpu);
332 if (c->initialized && c->cpu_die_id == die_id &&
333 c->phys_proc_id == proc_id)
334 return c->logical_die_id;
338 EXPORT_SYMBOL(topology_phys_to_logical_die);
341 * topology_update_package_map - Update the physical to logical package map
342 * @pkg: The physical package id as retrieved via CPUID
343 * @cpu: The cpu for which this is updated
345 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
349 /* Already available somewhere? */
350 new = topology_phys_to_logical_pkg(pkg);
354 new = logical_packages++;
356 pr_info("CPU %u Converting physical %u to logical package %u\n",
360 cpu_data(cpu).logical_proc_id = new;
364 * topology_update_die_map - Update the physical to logical die map
365 * @die: The die id as retrieved via CPUID
366 * @cpu: The cpu for which this is updated
368 int topology_update_die_map(unsigned int die, unsigned int cpu)
372 /* Already available somewhere? */
373 new = topology_phys_to_logical_die(die, cpu);
379 pr_info("CPU %u Converting physical %u to logical die %u\n",
383 cpu_data(cpu).logical_die_id = new;
387 void __init smp_store_boot_cpu_info(void)
389 int id = 0; /* CPU 0 */
390 struct cpuinfo_x86 *c = &cpu_data(id);
394 topology_update_package_map(c->phys_proc_id, id);
395 topology_update_die_map(c->cpu_die_id, id);
396 c->initialized = true;
400 * The bootstrap kernel entry code has set these up. Save them for
403 void smp_store_cpu_info(int id)
405 struct cpuinfo_x86 *c = &cpu_data(id);
407 /* Copy boot_cpu_data only on the first bringup */
412 * During boot time, CPU0 has this setup already. Save the info when
413 * bringing up AP or offlined CPU0.
415 identify_secondary_cpu(c);
416 c->initialized = true;
420 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
422 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
424 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
428 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
430 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
432 return !WARN_ONCE(!topology_same_node(c, o),
433 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
434 "[node: %d != %d]. Ignoring dependency.\n",
435 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
438 #define link_mask(mfunc, c1, c2) \
440 cpumask_set_cpu((c1), mfunc(c2)); \
441 cpumask_set_cpu((c2), mfunc(c1)); \
444 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
446 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
447 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
449 if (c->phys_proc_id == o->phys_proc_id &&
450 c->cpu_die_id == o->cpu_die_id &&
451 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
452 if (c->cpu_core_id == o->cpu_core_id)
453 return topology_sane(c, o, "smt");
455 if ((c->cu_id != 0xff) &&
456 (o->cu_id != 0xff) &&
457 (c->cu_id == o->cu_id))
458 return topology_sane(c, o, "smt");
461 } else if (c->phys_proc_id == o->phys_proc_id &&
462 c->cpu_die_id == o->cpu_die_id &&
463 c->cpu_core_id == o->cpu_core_id) {
464 return topology_sane(c, o, "smt");
470 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
472 if (c->phys_proc_id == o->phys_proc_id &&
473 c->cpu_die_id == o->cpu_die_id)
478 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
480 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
482 /* If the arch didn't set up l2c_id, fall back to SMT */
483 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID)
484 return match_smt(c, o);
486 /* Do not match if L2 cache id does not match: */
487 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2))
490 return topology_sane(c, o, "l2c");
494 * Unlike the other levels, we do not enforce keeping a
495 * multicore group inside a NUMA node. If this happens, we will
496 * discard the MC level of the topology later.
498 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
500 if (c->phys_proc_id == o->phys_proc_id)
506 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
508 * Any Intel CPU that has multiple nodes per package and does not
509 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
511 * When in SNC mode, these CPUs enumerate an LLC that is shared
512 * by multiple NUMA nodes. The LLC is shared for off-package data
513 * access but private to the NUMA node (half of the package) for
514 * on-package access. CPUID (the source of the information about
515 * the LLC) can only enumerate the cache as shared or unshared,
516 * but not this particular configuration.
519 static const struct x86_cpu_id intel_cod_cpu[] = {
520 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
521 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
522 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
526 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
528 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
529 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
530 bool intel_snc = id && id->driver_data;
532 /* Do not match if we do not have a valid APICID for cpu: */
533 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
536 /* Do not match if LLC id does not match: */
537 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
541 * Allow the SNC topology without warning. Return of false
542 * means 'c' does not share the LLC of 'o'. This will be
543 * reflected to userspace.
545 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
548 return topology_sane(c, o, "llc");
552 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC)
553 static inline int x86_sched_itmt_flags(void)
555 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
558 #ifdef CONFIG_SCHED_MC
559 static int x86_core_flags(void)
561 return cpu_core_flags() | x86_sched_itmt_flags();
564 #ifdef CONFIG_SCHED_SMT
565 static int x86_smt_flags(void)
567 return cpu_smt_flags() | x86_sched_itmt_flags();
570 #ifdef CONFIG_SCHED_CLUSTER
571 static int x86_cluster_flags(void)
573 return cpu_cluster_flags() | x86_sched_itmt_flags();
578 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
579 #ifdef CONFIG_SCHED_SMT
580 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
582 #ifdef CONFIG_SCHED_CLUSTER
583 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
585 #ifdef CONFIG_SCHED_MC
586 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
591 static struct sched_domain_topology_level x86_hybrid_topology[] = {
592 #ifdef CONFIG_SCHED_SMT
593 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
595 #ifdef CONFIG_SCHED_MC
596 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
598 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
602 static struct sched_domain_topology_level x86_topology[] = {
603 #ifdef CONFIG_SCHED_SMT
604 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
606 #ifdef CONFIG_SCHED_CLUSTER
607 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
609 #ifdef CONFIG_SCHED_MC
610 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
612 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
617 * Set if a package/die has multiple NUMA nodes inside.
618 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
619 * Sub-NUMA Clustering have this.
621 static bool x86_has_numa_in_package;
623 void set_cpu_sibling_map(int cpu)
625 bool has_smt = smp_num_siblings > 1;
626 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
627 struct cpuinfo_x86 *c = &cpu_data(cpu);
628 struct cpuinfo_x86 *o;
631 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
634 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
635 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
636 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
637 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
638 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
643 for_each_cpu(i, cpu_sibling_setup_mask) {
646 if (match_pkg(c, o) && !topology_same_node(c, o))
647 x86_has_numa_in_package = true;
649 if ((i == cpu) || (has_smt && match_smt(c, o)))
650 link_mask(topology_sibling_cpumask, cpu, i);
652 if ((i == cpu) || (has_mp && match_llc(c, o)))
653 link_mask(cpu_llc_shared_mask, cpu, i);
655 if ((i == cpu) || (has_mp && match_l2c(c, o)))
656 link_mask(cpu_l2c_shared_mask, cpu, i);
658 if ((i == cpu) || (has_mp && match_die(c, o)))
659 link_mask(topology_die_cpumask, cpu, i);
662 threads = cpumask_weight(topology_sibling_cpumask(cpu));
663 if (threads > __max_smt_threads)
664 __max_smt_threads = threads;
666 for_each_cpu(i, topology_sibling_cpumask(cpu))
667 cpu_data(i).smt_active = threads > 1;
670 * This needs a separate iteration over the cpus because we rely on all
671 * topology_sibling_cpumask links to be set-up.
673 for_each_cpu(i, cpu_sibling_setup_mask) {
676 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
677 link_mask(topology_core_cpumask, cpu, i);
680 * Does this new cpu bringup a new core?
684 * for each core in package, increment
685 * the booted_cores for this new cpu
688 topology_sibling_cpumask(i)) == i)
691 * increment the core count for all
692 * the other cpus in this package
695 cpu_data(i).booted_cores++;
696 } else if (i != cpu && !c->booted_cores)
697 c->booted_cores = cpu_data(i).booted_cores;
702 /* maps the cpu to the sched domain representing multi-core */
703 const struct cpumask *cpu_coregroup_mask(int cpu)
705 return cpu_llc_shared_mask(cpu);
708 const struct cpumask *cpu_clustergroup_mask(int cpu)
710 return cpu_l2c_shared_mask(cpu);
713 static void impress_friends(void)
716 unsigned long bogosum = 0;
718 * Allow the user to impress friends.
720 pr_debug("Before bogomips\n");
721 for_each_possible_cpu(cpu)
722 if (cpumask_test_cpu(cpu, cpu_callout_mask))
723 bogosum += cpu_data(cpu).loops_per_jiffy;
724 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
727 (bogosum/(5000/HZ))%100);
729 pr_debug("Before bogocount - setting activated=1\n");
732 void __inquire_remote_apic(int apicid)
734 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
735 const char * const names[] = { "ID", "VERSION", "SPIV" };
739 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
741 for (i = 0; i < ARRAY_SIZE(regs); i++) {
742 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
747 status = safe_apic_wait_icr_idle();
749 pr_cont("a previous APIC delivery may have failed\n");
751 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
756 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
757 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
760 case APIC_ICR_RR_VALID:
761 status = apic_read(APIC_RRR);
762 pr_cont("%08x\n", status);
771 * The Multiprocessor Specification 1.4 (1997) example code suggests
772 * that there should be a 10ms delay between the BSP asserting INIT
773 * and de-asserting INIT, when starting a remote processor.
774 * But that slows boot and resume on modern processors, which include
775 * many cores and don't require that delay.
777 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
778 * Modern processor families are quirked to remove the delay entirely.
780 #define UDELAY_10MS_DEFAULT 10000
782 static unsigned int init_udelay = UINT_MAX;
784 static int __init cpu_init_udelay(char *str)
786 get_option(&str, &init_udelay);
790 early_param("cpu_init_udelay", cpu_init_udelay);
792 static void __init smp_quirk_init_udelay(void)
794 /* if cmdline changed it from default, leave it alone */
795 if (init_udelay != UINT_MAX)
798 /* if modern processor, use no delay */
799 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
800 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
801 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
805 /* else, use legacy delay */
806 init_udelay = UDELAY_10MS_DEFAULT;
810 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
811 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
812 * won't ... remember to clear down the APIC, etc later.
815 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
817 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
818 unsigned long send_status, accept_status = 0;
822 /* Boot on the stack */
823 /* Kick the second */
824 apic_icr_write(APIC_DM_NMI | dm, apicid);
826 pr_debug("Waiting for send to finish...\n");
827 send_status = safe_apic_wait_icr_idle();
830 * Give the other CPU some time to accept the IPI.
833 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
834 maxlvt = lapic_get_maxlvt();
835 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
836 apic_write(APIC_ESR, 0);
837 accept_status = (apic_read(APIC_ESR) & 0xEF);
839 pr_debug("NMI sent\n");
842 pr_err("APIC never delivered???\n");
844 pr_err("APIC delivery error (%lx)\n", accept_status);
846 return (send_status | accept_status);
850 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
852 unsigned long send_status = 0, accept_status = 0;
853 int maxlvt, num_starts, j;
855 maxlvt = lapic_get_maxlvt();
858 * Be paranoid about clearing APIC errors.
860 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
861 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
862 apic_write(APIC_ESR, 0);
866 pr_debug("Asserting INIT\n");
869 * Turn INIT on target chip
874 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
877 pr_debug("Waiting for send to finish...\n");
878 send_status = safe_apic_wait_icr_idle();
882 pr_debug("Deasserting INIT\n");
886 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
888 pr_debug("Waiting for send to finish...\n");
889 send_status = safe_apic_wait_icr_idle();
894 * Should we send STARTUP IPIs ?
896 * Determine this based on the APIC version.
897 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
899 if (APIC_INTEGRATED(boot_cpu_apic_version))
905 * Run STARTUP IPI loop.
907 pr_debug("#startup loops: %d\n", num_starts);
909 for (j = 1; j <= num_starts; j++) {
910 pr_debug("Sending STARTUP #%d\n", j);
911 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
912 apic_write(APIC_ESR, 0);
914 pr_debug("After apic_write\n");
921 /* Boot on the stack */
922 /* Kick the second */
923 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
927 * Give the other CPU some time to accept the IPI.
929 if (init_udelay == 0)
934 pr_debug("Startup point 1\n");
936 pr_debug("Waiting for send to finish...\n");
937 send_status = safe_apic_wait_icr_idle();
940 * Give the other CPU some time to accept the IPI.
942 if (init_udelay == 0)
947 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
948 apic_write(APIC_ESR, 0);
949 accept_status = (apic_read(APIC_ESR) & 0xEF);
950 if (send_status || accept_status)
953 pr_debug("After Startup\n");
956 pr_err("APIC never delivered???\n");
958 pr_err("APIC delivery error (%lx)\n", accept_status);
960 return (send_status | accept_status);
963 /* reduce the number of lines printed when booting a large cpu count system */
964 static void announce_cpu(int cpu, int apicid)
966 static int current_node = NUMA_NO_NODE;
967 int node = early_cpu_to_node(cpu);
968 static int width, node_width;
971 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
974 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
977 printk(KERN_INFO "x86: Booting SMP configuration:\n");
979 if (system_state < SYSTEM_RUNNING) {
980 if (node != current_node) {
981 if (current_node > (-1))
985 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
986 node_width - num_digits(node), " ", node);
989 /* Add padding for the BSP */
991 pr_cont("%*s", width + 1, " ");
993 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
996 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
1000 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
1004 cpu = smp_processor_id();
1005 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
1012 * Wake up AP by INIT, INIT, STARTUP sequence.
1014 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
1015 * boot-strap code which is not a desired behavior for waking up BSP. To
1016 * void the boot-strap code, wake up CPU0 by NMI instead.
1018 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
1019 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
1020 * We'll change this code in the future to wake up hard offlined CPU0 if
1021 * real platform and request are available.
1024 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
1025 int *cpu0_nmi_registered)
1033 * Wake up AP by INIT, INIT, STARTUP sequence.
1036 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
1041 * Wake up BSP by nmi.
1043 * Register a NMI handler to help wake up CPU0.
1045 boot_error = register_nmi_handler(NMI_LOCAL,
1046 wakeup_cpu0_nmi, 0, "wake_cpu0");
1049 enable_start_cpu0 = 1;
1050 *cpu0_nmi_registered = 1;
1051 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
1052 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1061 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1065 /* Just in case we booted with a single CPU. */
1066 alternatives_enable_smp();
1068 per_cpu(current_task, cpu) = idle;
1069 cpu_init_stack_canary(cpu, idle);
1071 /* Initialize the interrupt stack(s) */
1072 ret = irq_init_percpu_irqstack(cpu);
1076 #ifdef CONFIG_X86_32
1077 /* Stack for startup_32 can be just as for start_secondary onwards */
1078 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1080 initial_gs = per_cpu_offset(cpu);
1086 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1087 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1088 * Returns zero if CPU booted OK, else error code from
1089 * ->wakeup_secondary_cpu.
1091 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1092 int *cpu0_nmi_registered)
1094 /* start_ip had better be page-aligned! */
1095 unsigned long start_ip = real_mode_header->trampoline_start;
1097 unsigned long boot_error = 0;
1098 unsigned long timeout;
1100 #ifdef CONFIG_X86_64
1101 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
1102 if (apic->wakeup_secondary_cpu_64)
1103 start_ip = real_mode_header->trampoline_start64;
1105 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1106 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1107 initial_code = (unsigned long)start_secondary;
1108 initial_stack = idle->thread.sp;
1110 /* Enable the espfix hack for this CPU */
1111 init_espfix_ap(cpu);
1113 /* So we see what's up */
1114 announce_cpu(cpu, apicid);
1117 * This grunge runs the startup process for
1118 * the targeted processor.
1121 if (x86_platform.legacy.warm_reset) {
1123 pr_debug("Setting warm reset code and vector.\n");
1125 smpboot_setup_warm_reset_vector(start_ip);
1127 * Be paranoid about clearing APIC errors.
1129 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1130 apic_write(APIC_ESR, 0);
1131 apic_read(APIC_ESR);
1136 * AP might wait on cpu_callout_mask in cpu_init() with
1137 * cpu_initialized_mask set if previous attempt to online
1138 * it timed-out. Clear cpu_initialized_mask so that after
1139 * INIT/SIPI it could start with a clean state.
1141 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1145 * Wake up a CPU in difference cases:
1146 * - Use a method from the APIC driver if one defined, with wakeup
1147 * straight to 64-bit mode preferred over wakeup to RM.
1149 * - Use an INIT boot APIC message for APs or NMI for BSP.
1151 if (apic->wakeup_secondary_cpu_64)
1152 boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip);
1153 else if (apic->wakeup_secondary_cpu)
1154 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1156 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1157 cpu0_nmi_registered);
1161 * Wait 10s total for first sign of life from AP
1164 timeout = jiffies + 10*HZ;
1165 while (time_before(jiffies, timeout)) {
1166 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1168 * Tell AP to proceed with initialization
1170 cpumask_set_cpu(cpu, cpu_callout_mask);
1180 * Wait till AP completes initial initialization
1182 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1184 * Allow other tasks to run while we wait for the
1185 * AP to come online. This also gives a chance
1186 * for the MTRR work(triggered by the AP coming online)
1187 * to be completed in the stop machine context.
1193 if (x86_platform.legacy.warm_reset) {
1195 * Cleanup possible dangling ends...
1197 smpboot_restore_warm_reset_vector();
1203 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1205 int apicid = apic->cpu_present_to_apicid(cpu);
1206 int cpu0_nmi_registered = 0;
1207 unsigned long flags;
1210 lockdep_assert_irqs_enabled();
1212 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1214 if (apicid == BAD_APICID ||
1215 !physid_isset(apicid, phys_cpu_present_map) ||
1216 !apic->apic_id_valid(apicid)) {
1217 pr_err("%s: bad cpu %d\n", __func__, cpu);
1222 * Already booted CPU?
1224 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1225 pr_debug("do_boot_cpu %d Already started\n", cpu);
1230 * Save current MTRR state in case it was changed since early boot
1231 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1235 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1236 err = cpu_check_up_prepare(cpu);
1237 if (err && err != -EBUSY)
1240 /* the FPU context is blank, nobody can own it */
1241 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1243 err = common_cpu_up(cpu, tidle);
1247 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1249 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1255 * Check TSC synchronization with the AP (keep irqs disabled
1258 local_irq_save(flags);
1259 check_tsc_sync_source(cpu);
1260 local_irq_restore(flags);
1262 while (!cpu_online(cpu)) {
1264 touch_nmi_watchdog();
1269 * Clean up the nmi handler. Do this after the callin and callout sync
1270 * to avoid impact of possible long unregister time.
1272 if (cpu0_nmi_registered)
1273 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1279 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1281 void arch_disable_smp_support(void)
1283 disable_ioapic_support();
1287 * Fall back to non SMP mode after errors.
1289 * RED-PEN audit/test this more. I bet there is more state messed up here.
1291 static __init void disable_smp(void)
1293 pr_info("SMP disabled\n");
1295 disable_ioapic_support();
1297 init_cpu_present(cpumask_of(0));
1298 init_cpu_possible(cpumask_of(0));
1300 if (smp_found_config)
1301 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1303 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1304 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1305 cpumask_set_cpu(0, topology_core_cpumask(0));
1306 cpumask_set_cpu(0, topology_die_cpumask(0));
1310 * Various sanity checks.
1312 static void __init smp_sanity_check(void)
1316 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1317 if (def_to_bigsmp && nr_cpu_ids > 8) {
1321 pr_warn("More than 8 CPUs detected - skipping them\n"
1322 "Use CONFIG_X86_BIGSMP\n");
1325 for_each_present_cpu(cpu) {
1327 set_cpu_present(cpu, false);
1332 for_each_possible_cpu(cpu) {
1334 set_cpu_possible(cpu, false);
1342 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1343 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1344 hard_smp_processor_id());
1346 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1350 * Should not be necessary because the MP table should list the boot
1351 * CPU too, but we do it for the sake of robustness anyway.
1353 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1354 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1355 boot_cpu_physical_apicid);
1356 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1361 static void __init smp_cpu_index_default(void)
1364 struct cpuinfo_x86 *c;
1366 for_each_possible_cpu(i) {
1368 /* mark all to hotplug */
1369 c->cpu_index = nr_cpu_ids;
1373 static void __init smp_get_logical_apicid(void)
1376 cpu0_logical_apicid = apic_read(APIC_LDR);
1378 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1381 void __init smp_prepare_cpus_common(void)
1385 smp_cpu_index_default();
1388 * Setup boot CPU information
1390 smp_store_boot_cpu_info(); /* Final full version of the data */
1391 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1394 for_each_possible_cpu(i) {
1395 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1396 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1397 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1398 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1399 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1403 * Set 'default' x86 topology, this matches default_topology() in that
1404 * it has NUMA nodes as a topology level. See also
1405 * native_smp_cpus_done().
1407 * Must be done before set_cpus_sibling_map() is ran.
1409 set_sched_topology(x86_topology);
1411 set_cpu_sibling_map(0);
1415 * Prepare for SMP bootup.
1416 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1417 * for common interface support.
1419 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1421 smp_prepare_cpus_common();
1425 switch (apic_intr_mode) {
1427 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1430 case APIC_SYMMETRIC_IO_NO_ROUTING:
1432 /* Setup local timer */
1433 x86_init.timers.setup_percpu_clockev();
1435 case APIC_VIRTUAL_WIRE:
1436 case APIC_SYMMETRIC_IO:
1440 /* Setup local timer */
1441 x86_init.timers.setup_percpu_clockev();
1443 smp_get_logical_apicid();
1446 print_cpu_info(&cpu_data(0));
1450 set_mtrr_aps_delayed_init();
1452 smp_quirk_init_udelay();
1454 speculative_store_bypass_ht_init();
1456 snp_set_wakeup_secondary_cpu();
1459 void arch_thaw_secondary_cpus_begin(void)
1461 set_mtrr_aps_delayed_init();
1464 void arch_thaw_secondary_cpus_end(void)
1470 * Early setup to make printk work.
1472 void __init native_smp_prepare_boot_cpu(void)
1474 int me = smp_processor_id();
1475 switch_to_new_gdt(me);
1476 /* already set me in cpu_online_mask in boot_cpu_init() */
1477 cpumask_set_cpu(me, cpu_callout_mask);
1478 cpu_set_state_online(me);
1479 native_pv_lock_init();
1482 void __init calculate_max_logical_packages(void)
1487 * Today neither Intel nor AMD support heterogeneous systems so
1488 * extrapolate the boot cpu's data to all packages.
1490 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1491 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1492 pr_info("Max logical packages: %u\n", __max_logical_packages);
1495 void __init native_smp_cpus_done(unsigned int max_cpus)
1497 pr_debug("Boot done\n");
1499 calculate_max_logical_packages();
1501 /* XXX for now assume numa-in-package and hybrid don't overlap */
1502 if (x86_has_numa_in_package)
1503 set_sched_topology(x86_numa_in_package_topology);
1504 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1505 set_sched_topology(x86_hybrid_topology);
1512 static int __initdata setup_possible_cpus = -1;
1513 static int __init _setup_possible_cpus(char *str)
1515 get_option(&str, &setup_possible_cpus);
1518 early_param("possible_cpus", _setup_possible_cpus);
1522 * cpu_possible_mask should be static, it cannot change as cpu's
1523 * are onlined, or offlined. The reason is per-cpu data-structures
1524 * are allocated by some modules at init time, and don't expect to
1525 * do this dynamically on cpu arrival/departure.
1526 * cpu_present_mask on the other hand can change dynamically.
1527 * In case when cpu_hotplug is not compiled, then we resort to current
1528 * behaviour, which is cpu_possible == cpu_present.
1531 * Three ways to find out the number of additional hotplug CPUs:
1532 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1533 * - The user can overwrite it with possible_cpus=NUM
1534 * - Otherwise don't reserve additional CPUs.
1535 * We do this because additional CPUs waste a lot of memory.
1538 __init void prefill_possible_map(void)
1542 /* No boot processor was found in mptable or ACPI MADT */
1543 if (!num_processors) {
1544 if (boot_cpu_has(X86_FEATURE_APIC)) {
1545 int apicid = boot_cpu_physical_apicid;
1546 int cpu = hard_smp_processor_id();
1548 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1550 /* Make sure boot cpu is enumerated */
1551 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1552 apic->apic_id_valid(apicid))
1553 generic_processor_info(apicid, boot_cpu_apic_version);
1556 if (!num_processors)
1560 i = setup_max_cpus ?: 1;
1561 if (setup_possible_cpus == -1) {
1562 possible = num_processors;
1563 #ifdef CONFIG_HOTPLUG_CPU
1565 possible += disabled_cpus;
1571 possible = setup_possible_cpus;
1573 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1575 /* nr_cpu_ids could be reduced via nr_cpus= */
1576 if (possible > nr_cpu_ids) {
1577 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1578 possible, nr_cpu_ids);
1579 possible = nr_cpu_ids;
1582 #ifdef CONFIG_HOTPLUG_CPU
1583 if (!setup_max_cpus)
1586 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1587 possible, setup_max_cpus);
1591 set_nr_cpu_ids(possible);
1593 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1594 possible, max_t(int, possible - num_processors, 0));
1596 reset_cpu_possible_mask();
1598 for (i = 0; i < possible; i++)
1599 set_cpu_possible(i, true);
1602 #ifdef CONFIG_HOTPLUG_CPU
1604 /* Recompute SMT state for all CPUs on offline */
1605 static void recompute_smt_state(void)
1607 int max_threads, cpu;
1610 for_each_online_cpu (cpu) {
1611 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1613 if (threads > max_threads)
1614 max_threads = threads;
1616 __max_smt_threads = max_threads;
1619 static void remove_siblinginfo(int cpu)
1622 struct cpuinfo_x86 *c = &cpu_data(cpu);
1624 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1625 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1627 * last thread sibling in this cpu core going down
1629 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1630 cpu_data(sibling).booted_cores--;
1633 for_each_cpu(sibling, topology_die_cpumask(cpu))
1634 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1636 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1637 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1638 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1639 cpu_data(sibling).smt_active = false;
1642 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1643 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1644 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1645 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1646 cpumask_clear(cpu_llc_shared_mask(cpu));
1647 cpumask_clear(cpu_l2c_shared_mask(cpu));
1648 cpumask_clear(topology_sibling_cpumask(cpu));
1649 cpumask_clear(topology_core_cpumask(cpu));
1650 cpumask_clear(topology_die_cpumask(cpu));
1652 c->booted_cores = 0;
1653 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1654 recompute_smt_state();
1657 static void remove_cpu_from_maps(int cpu)
1659 set_cpu_online(cpu, false);
1660 cpumask_clear_cpu(cpu, cpu_callout_mask);
1661 cpumask_clear_cpu(cpu, cpu_callin_mask);
1662 /* was set by cpu_init() */
1663 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1664 numa_remove_cpu(cpu);
1667 void cpu_disable_common(void)
1669 int cpu = smp_processor_id();
1671 remove_siblinginfo(cpu);
1673 /* It's now safe to remove this processor from the online map */
1675 remove_cpu_from_maps(cpu);
1676 unlock_vector_lock();
1681 int native_cpu_disable(void)
1685 ret = lapic_can_unplug_cpu();
1689 cpu_disable_common();
1692 * Disable the local APIC. Otherwise IPI broadcasts will reach
1693 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1696 * Disabling the APIC must happen after cpu_disable_common()
1697 * which invokes fixup_irqs().
1699 * Disabling the APIC preserves already set bits in IRR, but
1700 * an interrupt arriving after disabling the local APIC does not
1701 * set the corresponding IRR bit.
1703 * fixup_irqs() scans IRR for set bits so it can raise a not
1704 * yet handled interrupt on the new destination CPU via an IPI
1705 * but obviously it can't do so for IRR bits which are not set.
1706 * IOW, interrupts arriving after disabling the local APIC will
1709 apic_soft_disable();
1714 int common_cpu_die(unsigned int cpu)
1718 /* We don't do anything here: idle task is faking death itself. */
1720 /* They ack this in play_dead() by setting CPU_DEAD */
1721 if (cpu_wait_death(cpu, 5)) {
1722 if (system_state == SYSTEM_RUNNING)
1723 pr_info("CPU %u is now offline\n", cpu);
1725 pr_err("CPU %u didn't die...\n", cpu);
1732 void native_cpu_die(unsigned int cpu)
1734 common_cpu_die(cpu);
1737 void play_dead_common(void)
1742 (void)cpu_report_death();
1745 * With physical CPU hotplug, we should halt the cpu
1747 local_irq_disable();
1751 * cond_wakeup_cpu0 - Wake up CPU0 if needed.
1753 * If NMI wants to wake up CPU0, start CPU0.
1755 void cond_wakeup_cpu0(void)
1757 if (smp_processor_id() == 0 && enable_start_cpu0)
1760 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0);
1763 * We need to flush the caches before going to sleep, lest we have
1764 * dirty data in our caches when we come back up.
1766 static inline void mwait_play_dead(void)
1768 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1769 unsigned int eax, ebx, ecx, edx;
1770 unsigned int highest_cstate = 0;
1771 unsigned int highest_subcstate = 0;
1774 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1775 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1777 if (!this_cpu_has(X86_FEATURE_MWAIT))
1779 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1781 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1784 eax = CPUID_MWAIT_LEAF;
1786 native_cpuid(&eax, &ebx, &ecx, &edx);
1789 * eax will be 0 if EDX enumeration is not valid.
1790 * Initialized below to cstate, sub_cstate value when EDX is valid.
1792 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1795 edx >>= MWAIT_SUBSTATE_SIZE;
1796 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1797 if (edx & MWAIT_SUBSTATE_MASK) {
1799 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1802 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1803 (highest_subcstate - 1);
1806 /* Set up state for the kexec() hack below */
1807 md->status = CPUDEAD_MWAIT_WAIT;
1808 md->control = CPUDEAD_MWAIT_WAIT;
1814 * The CLFLUSH is a workaround for erratum AAI65 for
1815 * the Xeon 7400 series. It's not clear it is actually
1816 * needed, but it should be harmless in either case.
1817 * The WBINVD is insufficient due to the spurious-wakeup
1818 * case where we return around the loop.
1823 __monitor(md, 0, 0);
1827 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1829 * Kexec is about to happen. Don't go back into mwait() as
1830 * the kexec kernel might overwrite text and data including
1831 * page tables and stack. So mwait() would resume when the
1832 * monitor cache line is written to and then the CPU goes
1833 * south due to overwritten text, page tables and stack.
1835 * Note: This does _NOT_ protect against a stray MCE, NMI,
1836 * SMI. They will resume execution at the instruction
1837 * following the HLT instruction and run into the problem
1838 * which this is trying to prevent.
1840 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1850 * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1851 * mwait_play_dead().
1853 void smp_kick_mwait_play_dead(void)
1855 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1856 struct mwait_cpu_dead *md;
1857 unsigned int cpu, i;
1859 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1860 md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1862 /* Does it sit in mwait_play_dead() ? */
1863 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1866 /* Wait up to 5ms */
1867 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1868 /* Bring it out of mwait */
1869 WRITE_ONCE(md->control, newstate);
1873 if (READ_ONCE(md->status) != newstate)
1874 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1878 void hlt_play_dead(void)
1880 if (__this_cpu_read(cpu_info.x86) >= 4)
1890 void native_play_dead(void)
1893 tboot_shutdown(TB_SHUTDOWN_WFS);
1895 mwait_play_dead(); /* Only returns on failure */
1896 if (cpuidle_play_dead())
1900 #else /* ... !CONFIG_HOTPLUG_CPU */
1901 int native_cpu_disable(void)
1906 void native_cpu_die(unsigned int cpu)
1908 /* We said "no" in __cpu_disable */
1912 void native_play_dead(void)