1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for x86 and x86_64 platform bugs.
10 #include <asm/setup.h>
13 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
15 static void quirk_intel_irqbalance(struct pci_dev *dev)
20 /* BIOS may enable hardware IRQ balancing for
21 * E7520/E7320/E7525(revision ID 0x9 and below)
23 * Disable SW irqbalance/affinity on those platforms.
25 if (dev->revision > 0x9)
28 /* enable access to config space*/
29 pci_read_config_byte(dev, 0xf4, &config);
30 pci_write_config_byte(dev, 0xf4, config|0x2);
33 * read xTPR register. We may not have a pci_dev for device 8
34 * because it might be hidden until the above write.
36 pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
38 if (!(word & (1 << 13))) {
39 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
40 "disabling irq balancing and affinity\n");
47 /* put back the original value for config space*/
49 pci_write_config_byte(dev, 0xf4, config);
51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
52 quirk_intel_irqbalance);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
54 quirk_intel_irqbalance);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
56 quirk_intel_irqbalance);
59 #if defined(CONFIG_HPET_TIMER)
60 unsigned long force_hpet_address;
63 NONE_FORCE_HPET_RESUME,
64 OLD_ICH_FORCE_HPET_RESUME,
65 ICH_FORCE_HPET_RESUME,
66 VT8237_FORCE_HPET_RESUME,
67 NVIDIA_FORCE_HPET_RESUME,
68 ATI_FORCE_HPET_RESUME,
69 } force_hpet_resume_type;
71 static void __iomem *rcba_base;
73 static void ich_force_hpet_resume(void)
77 if (!force_hpet_address)
80 BUG_ON(rcba_base == NULL);
82 /* read the Function Disable register, dword mode only */
83 val = readl(rcba_base + 0x3404);
85 /* HPET disabled in HPTC. Trying to enable */
86 writel(val | 0x80, rcba_base + 0x3404);
89 val = readl(rcba_base + 0x3404);
93 printk(KERN_DEBUG "Force enabled HPET at resume\n");
96 static void ich_force_enable_hpet(struct pci_dev *dev)
102 if (hpet_address || force_hpet_address)
105 pci_read_config_dword(dev, 0xF0, &rcba);
108 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
109 "cannot force enable HPET\n");
113 /* use bits 31:14, 16 kB aligned */
114 rcba_base = ioremap(rcba, 0x4000);
115 if (rcba_base == NULL) {
116 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
117 "cannot force enable HPET\n");
121 /* read the Function Disable register, dword mode only */
122 val = readl(rcba_base + 0x3404);
125 /* HPET is enabled in HPTC. Just not reported by BIOS */
127 force_hpet_address = 0xFED00000 | (val << 12);
128 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
129 "0x%lx\n", force_hpet_address);
134 /* HPET disabled in HPTC. Trying to enable */
135 writel(val | 0x80, rcba_base + 0x3404);
137 val = readl(rcba_base + 0x3404);
142 force_hpet_address = 0xFED00000 | (val << 12);
146 force_hpet_address = 0;
148 dev_printk(KERN_DEBUG, &dev->dev,
149 "Failed to force enable HPET\n");
151 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
152 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
153 "0x%lx\n", force_hpet_address);
157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
158 ich_force_enable_hpet);
159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
160 ich_force_enable_hpet);
161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
162 ich_force_enable_hpet);
163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
164 ich_force_enable_hpet);
165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
166 ich_force_enable_hpet);
167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
168 ich_force_enable_hpet);
169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
170 ich_force_enable_hpet);
171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
172 ich_force_enable_hpet);
173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
174 ich_force_enable_hpet);
175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */
176 ich_force_enable_hpet);
178 static struct pci_dev *cached_dev;
180 static void hpet_print_force_info(void)
182 printk(KERN_INFO "HPET not enabled in BIOS. "
183 "You might try hpet=force boot option\n");
186 static void old_ich_force_hpet_resume(void)
191 if (!force_hpet_address || !cached_dev)
194 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
195 gen_cntl &= (~(0x7 << 15));
196 gen_cntl |= (0x4 << 15);
198 pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
199 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
200 val = gen_cntl >> 15;
203 printk(KERN_DEBUG "Force enabled HPET at resume\n");
208 static void old_ich_force_enable_hpet(struct pci_dev *dev)
213 if (hpet_address || force_hpet_address)
216 pci_read_config_dword(dev, 0xD0, &gen_cntl);
218 * Bit 17 is HPET enable bit.
219 * Bit 16:15 control the HPET base address.
221 val = gen_cntl >> 15;
225 force_hpet_address = 0xFED00000 | (val << 12);
226 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
232 * HPET is disabled. Trying enabling at FED00000 and check
235 gen_cntl &= (~(0x7 << 15));
236 gen_cntl |= (0x4 << 15);
237 pci_write_config_dword(dev, 0xD0, gen_cntl);
239 pci_read_config_dword(dev, 0xD0, &gen_cntl);
241 val = gen_cntl >> 15;
244 /* HPET is enabled in HPTC. Just not reported by BIOS */
246 force_hpet_address = 0xFED00000 | (val << 12);
247 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
248 "0x%lx\n", force_hpet_address);
250 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
254 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
258 * Undocumented chipset features. Make sure that the user enforced
261 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
264 old_ich_force_enable_hpet(dev);
267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
268 old_ich_force_enable_hpet_user);
269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
270 old_ich_force_enable_hpet_user);
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
272 old_ich_force_enable_hpet_user);
273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
274 old_ich_force_enable_hpet_user);
275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
276 old_ich_force_enable_hpet_user);
277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
278 old_ich_force_enable_hpet);
279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
280 old_ich_force_enable_hpet);
283 static void vt8237_force_hpet_resume(void)
287 if (!force_hpet_address || !cached_dev)
290 val = 0xfed00000 | 0x80;
291 pci_write_config_dword(cached_dev, 0x68, val);
293 pci_read_config_dword(cached_dev, 0x68, &val);
295 printk(KERN_DEBUG "Force enabled HPET at resume\n");
300 static void vt8237_force_enable_hpet(struct pci_dev *dev)
304 if (hpet_address || force_hpet_address)
307 if (!hpet_force_user) {
308 hpet_print_force_info();
312 pci_read_config_dword(dev, 0x68, &val);
314 * Bit 7 is HPET enable bit.
315 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
318 force_hpet_address = (val & ~0x3ff);
319 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
325 * HPET is disabled. Trying enabling at FED00000 and check
328 val = 0xfed00000 | 0x80;
329 pci_write_config_dword(dev, 0x68, val);
331 pci_read_config_dword(dev, 0x68, &val);
333 force_hpet_address = (val & ~0x3ff);
334 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
335 "0x%lx\n", force_hpet_address);
337 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
341 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
345 vt8237_force_enable_hpet);
346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
347 vt8237_force_enable_hpet);
348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700,
349 vt8237_force_enable_hpet);
351 static void ati_force_hpet_resume(void)
353 pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
354 printk(KERN_DEBUG "Force enabled HPET at resume\n");
357 static u32 ati_ixp4x0_rev(struct pci_dev *dev)
363 err = pci_read_config_byte(dev, 0xac, &b);
365 err |= pci_write_config_byte(dev, 0xac, b);
366 err |= pci_read_config_dword(dev, 0x70, &d);
368 err |= pci_write_config_dword(dev, 0x70, d);
369 err |= pci_read_config_dword(dev, 0x8, &d);
371 dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
378 static void ati_force_enable_hpet(struct pci_dev *dev)
383 if (hpet_address || force_hpet_address)
386 if (!hpet_force_user) {
387 hpet_print_force_info();
391 d = ati_ixp4x0_rev(dev);
396 pci_write_config_dword(dev, 0x14, 0xfed00000);
397 pci_read_config_dword(dev, 0x14, &val);
399 /* enable interrupt */
400 outb(0x72, 0xcd6); b = inb(0xcd7);
402 outb(0x72, 0xcd6); outb(b, 0xcd7);
403 outb(0x72, 0xcd6); b = inb(0xcd7);
406 pci_read_config_dword(dev, 0x64, &d);
408 pci_write_config_dword(dev, 0x64, d);
409 pci_read_config_dword(dev, 0x64, &d);
413 force_hpet_address = val;
414 force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
415 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
420 ati_force_enable_hpet);
423 * Undocumented chipset feature taken from LinuxBIOS.
425 static void nvidia_force_hpet_resume(void)
427 pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
428 printk(KERN_DEBUG "Force enabled HPET at resume\n");
431 static void nvidia_force_enable_hpet(struct pci_dev *dev)
435 if (hpet_address || force_hpet_address)
438 if (!hpet_force_user) {
439 hpet_print_force_info();
443 pci_write_config_dword(dev, 0x44, 0xfed00001);
444 pci_read_config_dword(dev, 0x44, &val);
445 force_hpet_address = val & 0xfffffffe;
446 force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
447 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
454 nvidia_force_enable_hpet);
455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
456 nvidia_force_enable_hpet);
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
460 nvidia_force_enable_hpet);
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
462 nvidia_force_enable_hpet);
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
464 nvidia_force_enable_hpet);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
466 nvidia_force_enable_hpet);
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
468 nvidia_force_enable_hpet);
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
470 nvidia_force_enable_hpet);
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
472 nvidia_force_enable_hpet);
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
474 nvidia_force_enable_hpet);
475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
476 nvidia_force_enable_hpet);
478 void force_hpet_resume(void)
480 switch (force_hpet_resume_type) {
481 case ICH_FORCE_HPET_RESUME:
482 ich_force_hpet_resume();
484 case OLD_ICH_FORCE_HPET_RESUME:
485 old_ich_force_hpet_resume();
487 case VT8237_FORCE_HPET_RESUME:
488 vt8237_force_hpet_resume();
490 case NVIDIA_FORCE_HPET_RESUME:
491 nvidia_force_hpet_resume();
493 case ATI_FORCE_HPET_RESUME:
494 ati_force_hpet_resume();
502 * According to the datasheet e6xx systems have the HPET hardwired to
505 static void e6xx_force_enable_hpet(struct pci_dev *dev)
507 if (hpet_address || force_hpet_address)
510 force_hpet_address = 0xFED00000;
511 force_hpet_resume_type = NONE_FORCE_HPET_RESUME;
512 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
513 "0x%lx\n", force_hpet_address);
515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU,
516 e6xx_force_enable_hpet);
519 * HPET MSI on some boards (ATI SB700/SB800) has side effect on
520 * floppy DMA. Disable HPET MSI on such platforms.
521 * See erratum #27 (Misinterpreted MSI Requests May Result in
522 * Corrupted LPC DMA Data) in AMD Publication #46837,
523 * "SB700 Family Product Errata", Rev. 1.0, March 2010.
525 static void force_disable_hpet_msi(struct pci_dev *unused)
527 hpet_msi_disable = true;
530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
531 force_disable_hpet_msi);
535 #if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
536 /* Set correct numa_node information for AMD NB functions */
537 static void quirk_amd_nb_node(struct pci_dev *dev)
539 struct pci_dev *nb_ht;
544 devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
545 nb_ht = pci_get_slot(dev->bus, devfn);
549 pci_read_config_dword(nb_ht, 0x60, &val);
550 node = pcibus_to_node(dev->bus) | (val & 7);
552 * Some hardware may return an invalid node ID,
555 if (node_online(node))
556 set_dev_node(&dev->dev, node);
560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F0,
580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F1,
582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F2,
584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3,
586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4,
588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
595 * Processor does not ensure DRAM scrub read/write sequence
596 * is atomic wrt accesses to CC6 save state area. Therefore
597 * if a concurrent scrub read/write access is to same address
598 * the entry may appear as if it is not written. This quirk
599 * applies to Fam16h models 00h-0Fh
601 * See "Revision Guide" for AMD F16h models 00h-0fh,
602 * document 51810 rev. 3.04, Nov 2013
604 static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
609 * Suggested workaround:
610 * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
612 pci_read_config_dword(dev, 0x58, &val);
615 pci_write_config_dword(dev, 0x58, val);
618 pci_read_config_dword(dev, 0x5C, &val);
621 pci_write_config_dword(dev, 0x5c, val);
625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
626 amd_disable_seq_and_redirect_scrub);
628 /* Ivy Bridge, Haswell, Broadwell */
629 static void quirk_intel_brickland_xeon_ras_cap(struct pci_dev *pdev)
633 pci_read_config_dword(pdev, 0x84, &capid0);
636 enable_copy_mc_fragile();
640 static void quirk_intel_purley_xeon_ras_cap(struct pci_dev *pdev)
644 pci_read_config_dword(pdev, 0x84, &capid0);
645 pci_read_config_dword(pdev, 0x98, &capid5);
648 * CAPID0{7:6} indicate whether this is an advanced RAS SKU
649 * CAPID5{8:5} indicate that various NVDIMM usage modes are
650 * enabled, so memory machine check recovery is also enabled.
652 if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
653 enable_copy_mc_fragile();
656 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap);
657 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap);
658 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap);
659 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap);
662 bool x86_apple_machine;
663 EXPORT_SYMBOL(x86_apple_machine);
665 void __init early_platform_quirks(void)
667 x86_apple_machine = dmi_match(DMI_SYS_VENDOR, "Apple Inc.") ||
668 dmi_match(DMI_SYS_VENDOR, "Apple Computer, Inc.");