x86/kernel/cpu/intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/kernel.h>
   3 #include <linux/pgtable.h>
   4
   5 #include <linux/string.h>
   6 #include <linux/bitops.h>
   7 #include <linux/smp.h>
   8 #include <linux/sched.h>
   9 #include <linux/sched/clock.h>
  10 #include <linux/semaphore.h>
  11 #include <linux/thread_info.h>
  12 #include <linux/init.h>
  13 #include <linux/uaccess.h>
  14 #include <linux/workqueue.h>
  15 #include <linux/delay.h>
  16 #include <linux/cpuhotplug.h>
  17
  18 #include <asm/cpufeature.h>
  19 #include <asm/msr.h>
  20 #include <asm/bugs.h>
  21 #include <asm/cpu.h>
  22 #include <asm/intel-family.h>
  23 #include <asm/microcode_intel.h>
  24 #include <asm/hwcap2.h>
  25 #include <asm/elf.h>
  26 #include <asm/cpu_device_id.h>
  27 #include <asm/cmdline.h>
  28 #include <asm/traps.h>
  29 #include <asm/resctrl.h>
  30 #include <asm/numa.h>
  31 #include <asm/thermal.h>
  32
  33 #ifdef CONFIG_X86_64
  34 #include <linux/topology.h>
  35 #endif
  36
  37 #include "cpu.h"
  38
  39 #ifdef CONFIG_X86_LOCAL_APIC
  40 #include <asm/mpspec.h>
  41 #include <asm/apic.h>
  42 #endif
  43
  44 enum split_lock_detect_state {
  45         sld_off = 0,
  46         sld_warn,
  47         sld_fatal,
  48         sld_ratelimit,
  49 };
  50
  51 /*
  52  * Default to sld_off because most systems do not support split lock detection.
  53  * sld_state_setup() will switch this to sld_warn on systems that support
  54  * split lock/bus lock detect, unless there is a command line override.
  55  */
  56 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
  57 static u64 msr_test_ctrl_cache __ro_after_init;
  58
  59 /*
  60  * With a name like MSR_TEST_CTL it should go without saying, but don't touch
  61  * MSR_TEST_CTL unless the CPU is one of the whitelisted models.  Writing it
  62  * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
  63  */
  64 static bool cpu_model_supports_sld __ro_after_init;
  65
  66 /*
  67  * Processors which have self-snooping capability can handle conflicting
  68  * memory type across CPUs by snooping its own cache. However, there exists
  69  * CPU models in which having conflicting memory types still leads to
  70  * unpredictable behavior, machine check errors, or hangs. Clear this
  71  * feature to prevent its use on machines with known erratas.
  72  */
  73 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
  74 {
  75         switch (c->x86_model) {
  76         case INTEL_FAM6_CORE_YONAH:
  77         case INTEL_FAM6_CORE2_MEROM:
  78         case INTEL_FAM6_CORE2_MEROM_L:
  79         case INTEL_FAM6_CORE2_PENRYN:
  80         case INTEL_FAM6_CORE2_DUNNINGTON:
  81         case INTEL_FAM6_NEHALEM:
  82         case INTEL_FAM6_NEHALEM_G:
  83         case INTEL_FAM6_NEHALEM_EP:
  84         case INTEL_FAM6_NEHALEM_EX:
  85         case INTEL_FAM6_WESTMERE:
  86         case INTEL_FAM6_WESTMERE_EP:
  87         case INTEL_FAM6_SANDYBRIDGE:
  88                 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
  89         }
  90 }
  91
  92 static bool ring3mwait_disabled __read_mostly;
  93
  94 static int __init ring3mwait_disable(char *__unused)
  95 {
  96         ring3mwait_disabled = true;
  97         return 1;
  98 }
  99 __setup("ring3mwait=disable", ring3mwait_disable);
 100
 101 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
 102 {
 103         /*
 104          * Ring 3 MONITOR/MWAIT feature cannot be detected without
 105          * cpu model and family comparison.
 106          */
 107         if (c->x86 != 6)
 108                 return;
 109         switch (c->x86_model) {
 110         case INTEL_FAM6_XEON_PHI_KNL:
 111         case INTEL_FAM6_XEON_PHI_KNM:
 112                 break;
 113         default:
 114                 return;
 115         }
 116
 117         if (ring3mwait_disabled)
 118                 return;
 119
 120         set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
 121         this_cpu_or(msr_misc_features_shadow,
 122                     1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
 123
 124         if (c == &boot_cpu_data)
 125                 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
 126 }
 127
 128 /*
 129  * Early microcode releases for the Spectre v2 mitigation were broken.
 130  * Information taken from;
 131  * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
 132  * - https://kb.vmware.com/s/article/52345
 133  * - Microcode revisions observed in the wild
 134  * - Release note from 20180108 microcode release
 135  */
 136 struct sku_microcode {
 137         u8 model;
 138         u8 stepping;
 139         u32 microcode;
 140 };
 141 static const struct sku_microcode spectre_bad_microcodes[] = {
 142         { INTEL_FAM6_KABYLAKE,          0x0B,   0x80 },
 143         { INTEL_FAM6_KABYLAKE,          0x0A,   0x80 },
 144         { INTEL_FAM6_KABYLAKE,          0x09,   0x80 },
 145         { INTEL_FAM6_KABYLAKE_L,        0x0A,   0x80 },
 146         { INTEL_FAM6_KABYLAKE_L,        0x09,   0x80 },
 147         { INTEL_FAM6_SKYLAKE_X,         0x03,   0x0100013e },
 148         { INTEL_FAM6_SKYLAKE_X,         0x04,   0x0200003c },
 149         { INTEL_FAM6_BROADWELL,         0x04,   0x28 },
 150         { INTEL_FAM6_BROADWELL_G,       0x01,   0x1b },
 151         { INTEL_FAM6_BROADWELL_D,       0x02,   0x14 },
 152         { INTEL_FAM6_BROADWELL_D,       0x03,   0x07000011 },
 153         { INTEL_FAM6_BROADWELL_X,       0x01,   0x0b000025 },
 154         { INTEL_FAM6_HASWELL_L,         0x01,   0x21 },
 155         { INTEL_FAM6_HASWELL_G,         0x01,   0x18 },
 156         { INTEL_FAM6_HASWELL,           0x03,   0x23 },
 157         { INTEL_FAM6_HASWELL_X,         0x02,   0x3b },
 158         { INTEL_FAM6_HASWELL_X,         0x04,   0x10 },
 159         { INTEL_FAM6_IVYBRIDGE_X,       0x04,   0x42a },
 160         /* Observed in the wild */
 161         { INTEL_FAM6_SANDYBRIDGE_X,     0x06,   0x61b },
 162         { INTEL_FAM6_SANDYBRIDGE_X,     0x07,   0x712 },
 163 };
 164
 165 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
 166 {
 167         int i;
 168
 169         /*
 170          * We know that the hypervisor lie to us on the microcode version so
 171          * we may as well hope that it is running the correct version.
 172          */
 173         if (cpu_has(c, X86_FEATURE_HYPERVISOR))
 174                 return false;
 175
 176         if (c->x86 != 6)
 177                 return false;
 178
 179         for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
 180                 if (c->x86_model == spectre_bad_microcodes[i].model &&
 181                     c->x86_stepping == spectre_bad_microcodes[i].stepping)
 182                         return (c->microcode <= spectre_bad_microcodes[i].microcode);
 183         }
 184         return false;
 185 }
 186
 187 int intel_cpu_collect_info(struct ucode_cpu_info *uci)
 188 {
 189         unsigned int val[2];
 190         unsigned int family, model;
 191         struct cpu_signature csig = { 0 };
 192         unsigned int eax, ebx, ecx, edx;
 193
 194         memset(uci, 0, sizeof(*uci));
 195
 196         eax = 0x00000001;
 197         ecx = 0;
 198         native_cpuid(&eax, &ebx, &ecx, &edx);
 199         csig.sig = eax;
 200
 201         family = x86_family(eax);
 202         model  = x86_model(eax);
 203
 204         if (model >= 5 || family > 6) {
 205                 /* get processor flags from MSR 0x17 */
 206                 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
 207                 csig.pf = 1 << ((val[1] >> 18) & 7);
 208         }
 209
 210         csig.rev = intel_get_microcode_revision();
 211
 212         uci->cpu_sig = csig;
 213         uci->valid = 1;
 214
 215         return 0;
 216 }
 217 EXPORT_SYMBOL_GPL(intel_cpu_collect_info);
 218
 219 #define MSR_IA32_TME_ACTIVATE           0x982
 220
 221 /* Helpers to access TME_ACTIVATE MSR */
 222 #define TME_ACTIVATE_LOCKED(x)          (x & 0x1)
 223 #define TME_ACTIVATE_ENABLED(x)         (x & 0x2)
 224
 225 #define TME_ACTIVATE_POLICY(x)          ((x >> 4) & 0xf)        /* Bits 7:4 */
 226 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
 227
 228 #define TME_ACTIVATE_KEYID_BITS(x)      ((x >> 32) & 0xf)       /* Bits 35:32 */
 229
 230 #define TME_ACTIVATE_CRYPTO_ALGS(x)     ((x >> 48) & 0xffff)    /* Bits 63:48 */
 231 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
 232
 233 /* Values for mktme_status (SW only construct) */
 234 #define MKTME_ENABLED                   0
 235 #define MKTME_DISABLED                  1
 236 #define MKTME_UNINITIALIZED             2
 237 static int mktme_status = MKTME_UNINITIALIZED;
 238
 239 static void detect_tme_early(struct cpuinfo_x86 *c)
 240 {
 241         u64 tme_activate, tme_policy, tme_crypto_algs;
 242         int keyid_bits = 0, nr_keyids = 0;
 243         static u64 tme_activate_cpu0 = 0;
 244
 245         rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
 246
 247         if (mktme_status != MKTME_UNINITIALIZED) {
 248                 if (tme_activate != tme_activate_cpu0) {
 249                         /* Broken BIOS? */
 250                         pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
 251                         pr_err_once("x86/tme: MKTME is not usable\n");
 252                         mktme_status = MKTME_DISABLED;
 253
 254                         /* Proceed. We may need to exclude bits from x86_phys_bits. */
 255                 }
 256         } else {
 257                 tme_activate_cpu0 = tme_activate;
 258         }
 259
 260         if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
 261                 pr_info_once("x86/tme: not enabled by BIOS\n");
 262                 mktme_status = MKTME_DISABLED;
 263                 return;
 264         }
 265
 266         if (mktme_status != MKTME_UNINITIALIZED)
 267                 goto detect_keyid_bits;
 268
 269         pr_info("x86/tme: enabled by BIOS\n");
 270
 271         tme_policy = TME_ACTIVATE_POLICY(tme_activate);
 272         if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
 273                 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
 274
 275         tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
 276         if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
 277                 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
 278                                 tme_crypto_algs);
 279                 mktme_status = MKTME_DISABLED;
 280         }
 281 detect_keyid_bits:
 282         keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
 283         nr_keyids = (1UL << keyid_bits) - 1;
 284         if (nr_keyids) {
 285                 pr_info_once("x86/mktme: enabled by BIOS\n");
 286                 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
 287         } else {
 288                 pr_info_once("x86/mktme: disabled by BIOS\n");
 289         }
 290
 291         if (mktme_status == MKTME_UNINITIALIZED) {
 292                 /* MKTME is usable */
 293                 mktme_status = MKTME_ENABLED;
 294         }
 295
 296         /*
 297          * KeyID bits effectively lower the number of physical address
 298          * bits.  Update cpuinfo_x86::x86_phys_bits accordingly.
 299          */
 300         c->x86_phys_bits -= keyid_bits;
 301 }
 302
 303 static void early_init_intel(struct cpuinfo_x86 *c)
 304 {
 305         u64 misc_enable;
 306
 307         /* Unmask CPUID levels if masked: */
 308         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
 309                 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
 310                                   MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
 311                         c->cpuid_level = cpuid_eax(0);
 312                         get_cpu_cap(c);
 313                 }
 314         }
 315
 316         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
 317                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
 318                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 319
 320         if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
 321                 c->microcode = intel_get_microcode_revision();
 322
 323         /* Now if any of them are set, check the blacklist and clear the lot */
 324         if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
 325              cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
 326              cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
 327              cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
 328                 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
 329                 setup_clear_cpu_cap(X86_FEATURE_IBRS);
 330                 setup_clear_cpu_cap(X86_FEATURE_IBPB);
 331                 setup_clear_cpu_cap(X86_FEATURE_STIBP);
 332                 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
 333                 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
 334                 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
 335                 setup_clear_cpu_cap(X86_FEATURE_SSBD);
 336                 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
 337         }
 338
 339         /*
 340          * Atom erratum AAE44/AAF40/AAG38/AAH41:
 341          *
 342          * A race condition between speculative fetches and invalidating
 343          * a large page.  This is worked around in microcode, but we
 344          * need the microcode to have already been loaded... so if it is
 345          * not, recommend a BIOS update and disable large pages.
 346          */
 347         if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
 348             c->microcode < 0x20e) {
 349                 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
 350                 clear_cpu_cap(c, X86_FEATURE_PSE);
 351         }
 352
 353 #ifdef CONFIG_X86_64
 354         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 355 #else
 356         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
 357         if (c->x86 == 15 && c->x86_cache_alignment == 64)
 358                 c->x86_cache_alignment = 128;
 359 #endif
 360
 361         /* CPUID workaround for 0F33/0F34 CPU */
 362         if (c->x86 == 0xF && c->x86_model == 0x3
 363             && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
 364                 c->x86_phys_bits = 36;
 365
 366         /*
 367          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
 368          * with P/T states and does not stop in deep C-states.
 369          *
 370          * It is also reliable across cores and sockets. (but not across
 371          * cabinets - we turn it off in that case explicitly.)
 372          */
 373         if (c->x86_power & (1 << 8)) {
 374                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 375                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 376         }
 377
 378         /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
 379         if (c->x86 == 6) {
 380                 switch (c->x86_model) {
 381                 case INTEL_FAM6_ATOM_SALTWELL_MID:
 382                 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
 383                 case INTEL_FAM6_ATOM_SILVERMONT_MID:
 384                 case INTEL_FAM6_ATOM_AIRMONT_NP:
 385                         set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
 386                         break;
 387                 default:
 388                         break;
 389                 }
 390         }
 391
 392         /*
 393          * There is a known erratum on Pentium III and Core Solo
 394          * and Core Duo CPUs.
 395          * " Page with PAT set to WC while associated MTRR is UC
 396          *   may consolidate to UC "
 397          * Because of this erratum, it is better to stick with
 398          * setting WC in MTRR rather than using PAT on these CPUs.
 399          *
 400          * Enable PAT WC only on P4, Core 2 or later CPUs.
 401          */
 402         if (c->x86 == 6 && c->x86_model < 15)
 403                 clear_cpu_cap(c, X86_FEATURE_PAT);
 404
 405         /*
 406          * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
 407          * clear the fast string and enhanced fast string CPU capabilities.
 408          */
 409         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
 410                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 411                 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
 412                         pr_info("Disabled fast string operations\n");
 413                         setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
 414                         setup_clear_cpu_cap(X86_FEATURE_ERMS);
 415                 }
 416         }
 417
 418         /*
 419          * Intel Quark Core DevMan_001.pdf section 6.4.11
 420          * "The operating system also is required to invalidate (i.e., flush)
 421          *  the TLB when any changes are made to any of the page table entries.
 422          *  The operating system must reload CR3 to cause the TLB to be flushed"
 423          *
 424          * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
 425          * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
 426          * to be modified.
 427          */
 428         if (c->x86 == 5 && c->x86_model == 9) {
 429                 pr_info("Disabling PGE capability bit\n");
 430                 setup_clear_cpu_cap(X86_FEATURE_PGE);
 431         }
 432
 433         if (c->cpuid_level >= 0x00000001) {
 434                 u32 eax, ebx, ecx, edx;
 435
 436                 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
 437                 /*
 438                  * If HTT (EDX[28]) is set EBX[16:23] contain the number of
 439                  * apicids which are reserved per package. Store the resulting
 440                  * shift value for the package management code.
 441                  */
 442                 if (edx & (1U << 28))
 443                         c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
 444         }
 445
 446         check_memory_type_self_snoop_errata(c);
 447
 448         /*
 449          * Get the number of SMT siblings early from the extended topology
 450          * leaf, if available. Otherwise try the legacy SMT detection.
 451          */
 452         if (detect_extended_topology_early(c) < 0)
 453                 detect_ht_early(c);
 454
 455         /*
 456          * Adjust the number of physical bits early because it affects the
 457          * valid bits of the MTRR mask registers.
 458          */
 459         if (cpu_has(c, X86_FEATURE_TME))
 460                 detect_tme_early(c);
 461 }
 462
 463 static void bsp_init_intel(struct cpuinfo_x86 *c)
 464 {
 465         resctrl_cpu_detect(c);
 466 }
 467
 468 #ifdef CONFIG_X86_32
 469 /*
 470  *      Early probe support logic for ppro memory erratum #50
 471  *
 472  *      This is called before we do cpu ident work
 473  */
 474
 475 int ppro_with_ram_bug(void)
 476 {
 477         /* Uses data from early_cpu_detect now */
 478         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 479             boot_cpu_data.x86 == 6 &&
 480             boot_cpu_data.x86_model == 1 &&
 481             boot_cpu_data.x86_stepping < 8) {
 482                 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
 483                 return 1;
 484         }
 485         return 0;
 486 }
 487
 488 static void intel_smp_check(struct cpuinfo_x86 *c)
 489 {
 490         /* calling is from identify_secondary_cpu() ? */
 491         if (!c->cpu_index)
 492                 return;
 493
 494         /*
 495          * Mask B, Pentium, but not Pentium MMX
 496          */
 497         if (c->x86 == 5 &&
 498             c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
 499             c->x86_model <= 3) {
 500                 /*
 501                  * Remember we have B step Pentia with bugs
 502                  */
 503                 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
 504                                     "with B stepping processors.\n");
 505         }
 506 }
 507
 508 static int forcepae;
 509 static int __init forcepae_setup(char *__unused)
 510 {
 511         forcepae = 1;
 512         return 1;
 513 }
 514 __setup("forcepae", forcepae_setup);
 515
 516 static void intel_workarounds(struct cpuinfo_x86 *c)
 517 {
 518 #ifdef CONFIG_X86_F00F_BUG
 519         /*
 520          * All models of Pentium and Pentium with MMX technology CPUs
 521          * have the F0 0F bug, which lets nonprivileged users lock up the
 522          * system. Announce that the fault handler will be checking for it.
 523          * The Quark is also family 5, but does not have the same bug.
 524          */
 525         clear_cpu_bug(c, X86_BUG_F00F);
 526         if (c->x86 == 5 && c->x86_model < 9) {
 527                 static int f00f_workaround_enabled;
 528
 529                 set_cpu_bug(c, X86_BUG_F00F);
 530                 if (!f00f_workaround_enabled) {
 531                         pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
 532                         f00f_workaround_enabled = 1;
 533                 }
 534         }
 535 #endif
 536
 537         /*
 538          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 539          * model 3 mask 3
 540          */
 541         if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
 542                 clear_cpu_cap(c, X86_FEATURE_SEP);
 543
 544         /*
 545          * PAE CPUID issue: many Pentium M report no PAE but may have a
 546          * functionally usable PAE implementation.
 547          * Forcefully enable PAE if kernel parameter "forcepae" is present.
 548          */
 549         if (forcepae) {
 550                 pr_warn("PAE forced!\n");
 551                 set_cpu_cap(c, X86_FEATURE_PAE);
 552                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
 553         }
 554
 555         /*
 556          * P4 Xeon erratum 037 workaround.
 557          * Hardware prefetcher may cause stale data to be loaded into the cache.
 558          */
 559         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
 560                 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
 561                                 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
 562                         pr_info("CPU: C0 stepping P4 Xeon detected.\n");
 563                         pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
 564                 }
 565         }
 566
 567         /*
 568          * See if we have a good local APIC by checking for buggy Pentia,
 569          * i.e. all B steppings and the C2 stepping of P54C when using their
 570          * integrated APIC (see 11AP erratum in "Pentium Processor
 571          * Specification Update").
 572          */
 573         if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 574             (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
 575                 set_cpu_bug(c, X86_BUG_11AP);
 576
 577
 578 #ifdef CONFIG_X86_INTEL_USERCOPY
 579         /*
 580          * Set up the preferred alignment for movsl bulk memory moves
 581          */
 582         switch (c->x86) {
 583         case 4:         /* 486: untested */
 584                 break;
 585         case 5:         /* Old Pentia: untested */
 586                 break;
 587         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 588                 movsl_mask.mask = 7;
 589                 break;
 590         case 15:        /* P4 is OK down to 8-byte alignment */
 591                 movsl_mask.mask = 7;
 592                 break;
 593         }
 594 #endif
 595
 596         intel_smp_check(c);
 597 }
 598 #else
 599 static void intel_workarounds(struct cpuinfo_x86 *c)
 600 {
 601 }
 602 #endif
 603
 604 static void srat_detect_node(struct cpuinfo_x86 *c)
 605 {
 606 #ifdef CONFIG_NUMA
 607         unsigned node;
 608         int cpu = smp_processor_id();
 609
 610         /* Don't do the funky fallback heuristics the AMD version employs
 611            for now. */
 612         node = numa_cpu_node(cpu);
 613         if (node == NUMA_NO_NODE || !node_online(node)) {
 614                 /* reuse the value from init_cpu_to_node() */
 615                 node = cpu_to_node(cpu);
 616         }
 617         numa_set_node(cpu, node);
 618 #endif
 619 }
 620
 621 static void init_cpuid_fault(struct cpuinfo_x86 *c)
 622 {
 623         u64 msr;
 624
 625         if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
 626                 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
 627                         set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
 628         }
 629 }
 630
 631 static void init_intel_misc_features(struct cpuinfo_x86 *c)
 632 {
 633         u64 msr;
 634
 635         if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
 636                 return;
 637
 638         /* Clear all MISC features */
 639         this_cpu_write(msr_misc_features_shadow, 0);
 640
 641         /* Check features and update capabilities and shadow control bits */
 642         init_cpuid_fault(c);
 643         probe_xeon_phi_r3mwait(c);
 644
 645         msr = this_cpu_read(msr_misc_features_shadow);
 646         wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
 647 }
 648
 649 static void split_lock_init(void);
 650 static void bus_lock_init(void);
 651
 652 static void init_intel(struct cpuinfo_x86 *c)
 653 {
 654         early_init_intel(c);
 655
 656         intel_workarounds(c);
 657
 658         /*
 659          * Detect the extended topology information if available. This
 660          * will reinitialise the initial_apicid which will be used
 661          * in init_intel_cacheinfo()
 662          */
 663         detect_extended_topology(c);
 664
 665         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 666                 /*
 667                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 668                  * detection.
 669                  */
 670                 detect_num_cpu_cores(c);
 671 #ifdef CONFIG_X86_32
 672                 detect_ht(c);
 673 #endif
 674         }
 675
 676         init_intel_cacheinfo(c);
 677
 678         if (c->cpuid_level > 9) {
 679                 unsigned eax = cpuid_eax(10);
 680                 /* Check for version and the number of counters */
 681                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 682                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 683         }
 684
 685         if (cpu_has(c, X86_FEATURE_XMM2))
 686                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 687
 688         if (boot_cpu_has(X86_FEATURE_DS)) {
 689                 unsigned int l1, l2;
 690
 691                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 692                 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
 693                         set_cpu_cap(c, X86_FEATURE_BTS);
 694                 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
 695                         set_cpu_cap(c, X86_FEATURE_PEBS);
 696         }
 697
 698         if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
 699             (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
 700                 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
 701
 702         if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
 703                 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
 704                 set_cpu_bug(c, X86_BUG_MONITOR);
 705
 706 #ifdef CONFIG_X86_64
 707         if (c->x86 == 15)
 708                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 709         if (c->x86 == 6)
 710                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 711 #else
 712         /*
 713          * Names for the Pentium II/Celeron processors
 714          * detectable only by also checking the cache size.
 715          * Dixon is NOT a Celeron.
 716          */
 717         if (c->x86 == 6) {
 718                 unsigned int l2 = c->x86_cache_size;
 719                 char *p = NULL;
 720
 721                 switch (c->x86_model) {
 722                 case 5:
 723                         if (l2 == 0)
 724                                 p = "Celeron (Covington)";
 725                         else if (l2 == 256)
 726                                 p = "Mobile Pentium II (Dixon)";
 727                         break;
 728
 729                 case 6:
 730                         if (l2 == 128)
 731                                 p = "Celeron (Mendocino)";
 732                         else if (c->x86_stepping == 0 || c->x86_stepping == 5)
 733                                 p = "Celeron-A";
 734                         break;
 735
 736                 case 8:
 737                         if (l2 == 128)
 738                                 p = "Celeron (Coppermine)";
 739                         break;
 740                 }
 741
 742                 if (p)
 743                         strcpy(c->x86_model_id, p);
 744         }
 745
 746         if (c->x86 == 15)
 747                 set_cpu_cap(c, X86_FEATURE_P4);
 748         if (c->x86 == 6)
 749                 set_cpu_cap(c, X86_FEATURE_P3);
 750 #endif
 751
 752         /* Work around errata */
 753         srat_detect_node(c);
 754
 755         init_ia32_feat_ctl(c);
 756
 757         init_intel_misc_features(c);
 758
 759         split_lock_init();
 760         bus_lock_init();
 761
 762         intel_init_thermal(c);
 763 }
 764
 765 #ifdef CONFIG_X86_32
 766 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 767 {
 768         /*
 769          * Intel PIII Tualatin. This comes in two flavours.
 770          * One has 256kb of cache, the other 512. We have no way
 771          * to determine which, so we use a boottime override
 772          * for the 512kb model, and assume 256 otherwise.
 773          */
 774         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 775                 size = 256;
 776
 777         /*
 778          * Intel Quark SoC X1000 contains a 4-way set associative
 779          * 16K cache with a 16 byte cache line and 256 lines per tag
 780          */
 781         if ((c->x86 == 5) && (c->x86_model == 9))
 782                 size = 16;
 783         return size;
 784 }
 785 #endif
 786
 787 #define TLB_INST_4K     0x01
 788 #define TLB_INST_4M     0x02
 789 #define TLB_INST_2M_4M  0x03
 790
 791 #define TLB_INST_ALL    0x05
 792 #define TLB_INST_1G     0x06
 793
 794 #define TLB_DATA_4K     0x11
 795 #define TLB_DATA_4M     0x12
 796 #define TLB_DATA_2M_4M  0x13
 797 #define TLB_DATA_4K_4M  0x14
 798
 799 #define TLB_DATA_1G     0x16
 800
 801 #define TLB_DATA0_4K    0x21
 802 #define TLB_DATA0_4M    0x22
 803 #define TLB_DATA0_2M_4M 0x23
 804
 805 #define STLB_4K         0x41
 806 #define STLB_4K_2M      0x42
 807
 808 static const struct _tlb_table intel_tlb_table[] = {
 809         { 0x01, TLB_INST_4K,            32,     " TLB_INST 4 KByte pages, 4-way set associative" },
 810         { 0x02, TLB_INST_4M,            2,      " TLB_INST 4 MByte pages, full associative" },
 811         { 0x03, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way set associative" },
 812         { 0x04, TLB_DATA_4M,            8,      " TLB_DATA 4 MByte pages, 4-way set associative" },
 813         { 0x05, TLB_DATA_4M,            32,     " TLB_DATA 4 MByte pages, 4-way set associative" },
 814         { 0x0b, TLB_INST_4M,            4,      " TLB_INST 4 MByte pages, 4-way set associative" },
 815         { 0x4f, TLB_INST_4K,            32,     " TLB_INST 4 KByte pages" },
 816         { 0x50, TLB_INST_ALL,           64,     " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
 817         { 0x51, TLB_INST_ALL,           128,    " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
 818         { 0x52, TLB_INST_ALL,           256,    " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
 819         { 0x55, TLB_INST_2M_4M,         7,      " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
 820         { 0x56, TLB_DATA0_4M,           16,     " TLB_DATA0 4 MByte pages, 4-way set associative" },
 821         { 0x57, TLB_DATA0_4K,           16,     " TLB_DATA0 4 KByte pages, 4-way associative" },
 822         { 0x59, TLB_DATA0_4K,           16,     " TLB_DATA0 4 KByte pages, fully associative" },
 823         { 0x5a, TLB_DATA0_2M_4M,        32,     " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
 824         { 0x5b, TLB_DATA_4K_4M,         64,     " TLB_DATA 4 KByte and 4 MByte pages" },
 825         { 0x5c, TLB_DATA_4K_4M,         128,    " TLB_DATA 4 KByte and 4 MByte pages" },
 826         { 0x5d, TLB_DATA_4K_4M,         256,    " TLB_DATA 4 KByte and 4 MByte pages" },
 827         { 0x61, TLB_INST_4K,            48,     " TLB_INST 4 KByte pages, full associative" },
 828         { 0x63, TLB_DATA_1G,            4,      " TLB_DATA 1 GByte pages, 4-way set associative" },
 829         { 0x6b, TLB_DATA_4K,            256,    " TLB_DATA 4 KByte pages, 8-way associative" },
 830         { 0x6c, TLB_DATA_2M_4M,         128,    " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
 831         { 0x6d, TLB_DATA_1G,            16,     " TLB_DATA 1 GByte pages, fully associative" },
 832         { 0x76, TLB_INST_2M_4M,         8,      " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
 833         { 0xb0, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 4-way set associative" },
 834         { 0xb1, TLB_INST_2M_4M,         4,      " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
 835         { 0xb2, TLB_INST_4K,            64,     " TLB_INST 4KByte pages, 4-way set associative" },
 836         { 0xb3, TLB_DATA_4K,            128,    " TLB_DATA 4 KByte pages, 4-way set associative" },
 837         { 0xb4, TLB_DATA_4K,            256,    " TLB_DATA 4 KByte pages, 4-way associative" },
 838         { 0xb5, TLB_INST_4K,            64,     " TLB_INST 4 KByte pages, 8-way set associative" },
 839         { 0xb6, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 8-way set associative" },
 840         { 0xba, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way associative" },
 841         { 0xc0, TLB_DATA_4K_4M,         8,      " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
 842         { 0xc1, STLB_4K_2M,             1024,   " STLB 4 KByte and 2 MByte pages, 8-way associative" },
 843         { 0xc2, TLB_DATA_2M_4M,         16,     " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
 844         { 0xca, STLB_4K,                512,    " STLB 4 KByte pages, 4-way associative" },
 845         { 0x00, 0, 0 }
 846 };
 847
 848 static void intel_tlb_lookup(const unsigned char desc)
 849 {
 850         unsigned char k;
 851         if (desc == 0)
 852                 return;
 853
 854         /* look up this descriptor in the table */
 855         for (k = 0; intel_tlb_table[k].descriptor != desc &&
 856              intel_tlb_table[k].descriptor != 0; k++)
 857                 ;
 858
 859         if (intel_tlb_table[k].tlb_type == 0)
 860                 return;
 861
 862         switch (intel_tlb_table[k].tlb_type) {
 863         case STLB_4K:
 864                 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
 865                         tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
 866                 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
 867                         tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
 868                 break;
 869         case STLB_4K_2M:
 870                 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
 871                         tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
 872                 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
 873                         tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
 874                 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
 875                         tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
 876                 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
 877                         tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
 878                 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
 879                         tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
 880                 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
 881                         tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
 882                 break;
 883         case TLB_INST_ALL:
 884                 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
 885                         tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
 886                 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
 887                         tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
 888                 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
 889                         tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
 890                 break;
 891         case TLB_INST_4K:
 892                 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
 893                         tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
 894                 break;
 895         case TLB_INST_4M:
 896                 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
 897                         tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
 898                 break;
 899         case TLB_INST_2M_4M:
 900                 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
 901                         tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
 902                 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
 903                         tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
 904                 break;
 905         case TLB_DATA_4K:
 906         case TLB_DATA0_4K:
 907                 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
 908                         tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
 909                 break;
 910         case TLB_DATA_4M:
 911         case TLB_DATA0_4M:
 912                 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
 913                         tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
 914                 break;
 915         case TLB_DATA_2M_4M:
 916         case TLB_DATA0_2M_4M:
 917                 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
 918                         tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
 919                 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
 920                         tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
 921                 break;
 922         case TLB_DATA_4K_4M:
 923                 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
 924                         tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
 925                 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
 926                         tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
 927                 break;
 928         case TLB_DATA_1G:
 929                 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
 930                         tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
 931                 break;
 932         }
 933 }
 934
 935 static void intel_detect_tlb(struct cpuinfo_x86 *c)
 936 {
 937         int i, j, n;
 938         unsigned int regs[4];
 939         unsigned char *desc = (unsigned char *)regs;
 940
 941         if (c->cpuid_level < 2)
 942                 return;
 943
 944         /* Number of times to iterate */
 945         n = cpuid_eax(2) & 0xFF;
 946
 947         for (i = 0 ; i < n ; i++) {
 948                 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
 949
 950                 /* If bit 31 is set, this is an unknown format */
 951                 for (j = 0 ; j < 3 ; j++)
 952                         if (regs[j] & (1 << 31))
 953                                 regs[j] = 0;
 954
 955                 /* Byte 0 is level count, not a descriptor */
 956                 for (j = 1 ; j < 16 ; j++)
 957                         intel_tlb_lookup(desc[j]);
 958         }
 959 }
 960
 961 static const struct cpu_dev intel_cpu_dev = {
 962         .c_vendor       = "Intel",
 963         .c_ident        = { "GenuineIntel" },
 964 #ifdef CONFIG_X86_32
 965         .legacy_models = {
 966                 { .family = 4, .model_names =
 967                   {
 968                           [0] = "486 DX-25/33",
 969                           [1] = "486 DX-50",
 970                           [2] = "486 SX",
 971                           [3] = "486 DX/2",
 972                           [4] = "486 SL",
 973                           [5] = "486 SX/2",
 974                           [7] = "486 DX/2-WB",
 975                           [8] = "486 DX/4",
 976                           [9] = "486 DX/4-WB"
 977                   }
 978                 },
 979                 { .family = 5, .model_names =
 980                   {
 981                           [0] = "Pentium 60/66 A-step",
 982                           [1] = "Pentium 60/66",
 983                           [2] = "Pentium 75 - 200",
 984                           [3] = "OverDrive PODP5V83",
 985                           [4] = "Pentium MMX",
 986                           [7] = "Mobile Pentium 75 - 200",
 987                           [8] = "Mobile Pentium MMX",
 988                           [9] = "Quark SoC X1000",
 989                   }
 990                 },
 991                 { .family = 6, .model_names =
 992                   {
 993                           [0] = "Pentium Pro A-step",
 994                           [1] = "Pentium Pro",
 995                           [3] = "Pentium II (Klamath)",
 996                           [4] = "Pentium II (Deschutes)",
 997                           [5] = "Pentium II (Deschutes)",
 998                           [6] = "Mobile Pentium II",
 999                           [7] = "Pentium III (Katmai)",
1000                           [8] = "Pentium III (Coppermine)",
1001                           [10] = "Pentium III (Cascades)",
1002                           [11] = "Pentium III (Tualatin)",
1003                   }
1004                 },
1005                 { .family = 15, .model_names =
1006                   {
1007                           [0] = "Pentium 4 (Unknown)",
1008                           [1] = "Pentium 4 (Willamette)",
1009                           [2] = "Pentium 4 (Northwood)",
1010                           [4] = "Pentium 4 (Foster)",
1011                           [5] = "Pentium 4 (Foster)",
1012                   }
1013                 },
1014         },
1015         .legacy_cache_size = intel_size_cache,
1016 #endif
1017         .c_detect_tlb   = intel_detect_tlb,
1018         .c_early_init   = early_init_intel,
1019         .c_bsp_init     = bsp_init_intel,
1020         .c_init         = init_intel,
1021         .c_x86_vendor   = X86_VENDOR_INTEL,
1022 };
1023
1024 cpu_dev_register(intel_cpu_dev);
1025
1026 #undef pr_fmt
1027 #define pr_fmt(fmt) "x86/split lock detection: " fmt
1028
1029 static const struct {
1030         const char                      *option;
1031         enum split_lock_detect_state    state;
1032 } sld_options[] __initconst = {
1033         { "off",        sld_off   },
1034         { "warn",       sld_warn  },
1035         { "fatal",      sld_fatal },
1036         { "ratelimit:", sld_ratelimit },
1037 };
1038
1039 static struct ratelimit_state bld_ratelimit;
1040
1041 static unsigned int sysctl_sld_mitigate = 1;
1042 static DEFINE_SEMAPHORE(buslock_sem);
1043
1044 #ifdef CONFIG_PROC_SYSCTL
1045 static struct ctl_table sld_sysctls[] = {
1046         {
1047                 .procname       = "split_lock_mitigate",
1048                 .data           = &sysctl_sld_mitigate,
1049                 .maxlen         = sizeof(unsigned int),
1050                 .mode           = 0644,
1051                 .proc_handler   = proc_douintvec_minmax,
1052                 .extra1         = SYSCTL_ZERO,
1053                 .extra2         = SYSCTL_ONE,
1054         },
1055         {}
1056 };
1057
1058 static int __init sld_mitigate_sysctl_init(void)
1059 {
1060         register_sysctl_init("kernel", sld_sysctls);
1061         return 0;
1062 }
1063
1064 late_initcall(sld_mitigate_sysctl_init);
1065 #endif
1066
1067 static inline bool match_option(const char *arg, int arglen, const char *opt)
1068 {
1069         int len = strlen(opt), ratelimit;
1070
1071         if (strncmp(arg, opt, len))
1072                 return false;
1073
1074         /*
1075          * Min ratelimit is 1 bus lock/sec.
1076          * Max ratelimit is 1000 bus locks/sec.
1077          */
1078         if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 &&
1079             ratelimit > 0 && ratelimit <= 1000) {
1080                 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit);
1081                 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE);
1082                 return true;
1083         }
1084
1085         return len == arglen;
1086 }
1087
1088 static bool split_lock_verify_msr(bool on)
1089 {
1090         u64 ctrl, tmp;
1091
1092         if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
1093                 return false;
1094         if (on)
1095                 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1096         else
1097                 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1098         if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1099                 return false;
1100         rdmsrl(MSR_TEST_CTRL, tmp);
1101         return ctrl == tmp;
1102 }
1103
1104 static void __init sld_state_setup(void)
1105 {
1106         enum split_lock_detect_state state = sld_warn;
1107         char arg[20];
1108         int i, ret;
1109
1110         if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1111             !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1112                 return;
1113
1114         ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1115                                   arg, sizeof(arg));
1116         if (ret >= 0) {
1117                 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1118                         if (match_option(arg, ret, sld_options[i].option)) {
1119                                 state = sld_options[i].state;
1120                                 break;
1121                         }
1122                 }
1123         }
1124         sld_state = state;
1125 }
1126
1127 static void __init __split_lock_setup(void)
1128 {
1129         if (!split_lock_verify_msr(false)) {
1130                 pr_info("MSR access failed: Disabled\n");
1131                 return;
1132         }
1133
1134         rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1135
1136         if (!split_lock_verify_msr(true)) {
1137                 pr_info("MSR access failed: Disabled\n");
1138                 return;
1139         }
1140
1141         /* Restore the MSR to its cached value. */
1142         wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1143
1144         setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1145 }
1146
1147 /*
1148  * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1149  * is not implemented as one thread could undo the setting of the other
1150  * thread immediately after dropping the lock anyway.
1151  */
1152 static void sld_update_msr(bool on)
1153 {
1154         u64 test_ctrl_val = msr_test_ctrl_cache;
1155
1156         if (on)
1157                 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1158
1159         wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1160 }
1161
1162 static void split_lock_init(void)
1163 {
1164         /*
1165          * #DB for bus lock handles ratelimit and #AC for split lock is
1166          * disabled.
1167          */
1168         if (sld_state == sld_ratelimit) {
1169                 split_lock_verify_msr(false);
1170                 return;
1171         }
1172
1173         if (cpu_model_supports_sld)
1174                 split_lock_verify_msr(sld_state != sld_off);
1175 }
1176
1177 static void __split_lock_reenable_unlock(struct work_struct *work)
1178 {
1179         sld_update_msr(true);
1180         up(&buslock_sem);
1181 }
1182
1183 static DECLARE_DELAYED_WORK(sl_reenable_unlock, __split_lock_reenable_unlock);
1184
1185 static void __split_lock_reenable(struct work_struct *work)
1186 {
1187         sld_update_msr(true);
1188 }
1189 static DECLARE_DELAYED_WORK(sl_reenable, __split_lock_reenable);
1190
1191 /*
1192  * If a CPU goes offline with pending delayed work to re-enable split lock
1193  * detection then the delayed work will be executed on some other CPU. That
1194  * handles releasing the buslock_sem, but because it executes on a
1195  * different CPU probably won't re-enable split lock detection. This is a
1196  * problem on HT systems since the sibling CPU on the same core may then be
1197  * left running with split lock detection disabled.
1198  *
1199  * Unconditionally re-enable detection here.
1200  */
1201 static int splitlock_cpu_offline(unsigned int cpu)
1202 {
1203         sld_update_msr(true);
1204
1205         return 0;
1206 }
1207
1208 static void split_lock_warn(unsigned long ip)
1209 {
1210         struct delayed_work *work;
1211         int cpu;
1212
1213         if (!current->reported_split_lock)
1214                 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1215                                     current->comm, current->pid, ip);
1216         current->reported_split_lock = 1;
1217
1218         if (sysctl_sld_mitigate) {
1219                 /*
1220                  * misery factor #1:
1221                  * sleep 10ms before trying to execute split lock.
1222                  */
1223                 if (msleep_interruptible(10) > 0)
1224                         return;
1225                 /*
1226                  * Misery factor #2:
1227                  * only allow one buslocked disabled core at a time.
1228                  */
1229                 if (down_interruptible(&buslock_sem) == -EINTR)
1230                         return;
1231                 work = &sl_reenable_unlock;
1232         } else {
1233                 work = &sl_reenable;
1234         }
1235
1236         cpu = get_cpu();
1237         schedule_delayed_work_on(cpu, work, 2);
1238
1239         /* Disable split lock detection on this CPU to make progress */
1240         sld_update_msr(false);
1241         put_cpu();
1242 }
1243
1244 bool handle_guest_split_lock(unsigned long ip)
1245 {
1246         if (sld_state == sld_warn) {
1247                 split_lock_warn(ip);
1248                 return true;
1249         }
1250
1251         pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1252                      current->comm, current->pid,
1253                      sld_state == sld_fatal ? "fatal" : "bogus", ip);
1254
1255         current->thread.error_code = 0;
1256         current->thread.trap_nr = X86_TRAP_AC;
1257         force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1258         return false;
1259 }
1260 EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1261
1262 static void bus_lock_init(void)
1263 {
1264         u64 val;
1265
1266         if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1267                 return;
1268
1269         rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
1270
1271         if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1272             (sld_state == sld_warn || sld_state == sld_fatal)) ||
1273             sld_state == sld_off) {
1274                 /*
1275                  * Warn and fatal are handled by #AC for split lock if #AC for
1276                  * split lock is supported.
1277                  */
1278                 val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1279         } else {
1280                 val |= DEBUGCTLMSR_BUS_LOCK_DETECT;
1281         }
1282
1283         wrmsrl(MSR_IA32_DEBUGCTLMSR, val);
1284 }
1285
1286 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1287 {
1288         if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1289                 return false;
1290         split_lock_warn(regs->ip);
1291         return true;
1292 }
1293
1294 void handle_bus_lock(struct pt_regs *regs)
1295 {
1296         switch (sld_state) {
1297         case sld_off:
1298                 break;
1299         case sld_ratelimit:
1300                 /* Enforce no more than bld_ratelimit bus locks/sec. */
1301                 while (!__ratelimit(&bld_ratelimit))
1302                         msleep(20);
1303                 /* Warn on the bus lock. */
1304                 fallthrough;
1305         case sld_warn:
1306                 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",
1307                                     current->comm, current->pid, regs->ip);
1308                 break;
1309         case sld_fatal:
1310                 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1311                 break;
1312         }
1313 }
1314
1315 /*
1316  * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should
1317  * only be trusted if it is confirmed that a CPU model implements a
1318  * specific feature at a particular bit position.
1319  *
1320  * The possible driver data field values:
1321  *
1322  * - 0: CPU models that are known to have the per-core split-lock detection
1323  *      feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1324  *
1325  * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
1326  *      bit 5 to enumerate the per-core split-lock detection feature.
1327  */
1328 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1329         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,           0),
1330         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           0),
1331         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,           0),
1332         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,        1),
1333         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      1),
1334         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      1),
1335         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,         1),
1336         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,           1),
1337         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    1),
1338         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           1),
1339         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         1),
1340         X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          1),
1341         {}
1342 };
1343
1344 static void __init split_lock_setup(struct cpuinfo_x86 *c)
1345 {
1346         const struct x86_cpu_id *m;
1347         u64 ia32_core_caps;
1348
1349         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1350                 return;
1351
1352         m = x86_match_cpu(split_lock_cpu_ids);
1353         if (!m)
1354                 return;
1355
1356         switch (m->driver_data) {
1357         case 0:
1358                 break;
1359         case 1:
1360                 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1361                         return;
1362                 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1363                 if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))
1364                         return;
1365                 break;
1366         default:
1367                 return;
1368         }
1369
1370         cpu_model_supports_sld = true;
1371         __split_lock_setup();
1372 }
1373
1374 static void sld_state_show(void)
1375 {
1376         if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
1377             !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1378                 return;
1379
1380         switch (sld_state) {
1381         case sld_off:
1382                 pr_info("disabled\n");
1383                 break;
1384         case sld_warn:
1385                 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1386                         pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1387                         if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1388                                               "x86/splitlock", NULL, splitlock_cpu_offline) < 0)
1389                                 pr_warn("No splitlock CPU offline handler\n");
1390                 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1391                         pr_info("#DB: warning on user-space bus_locks\n");
1392                 }
1393                 break;
1394         case sld_fatal:
1395                 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1396                         pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1397                 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1398                         pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1399                                 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
1400                                 " from non-WB" : "");
1401                 }
1402                 break;
1403         case sld_ratelimit:
1404                 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1405                         pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst);
1406                 break;
1407         }
1408 }
1409
1410 void __init sld_setup(struct cpuinfo_x86 *c)
1411 {
1412         split_lock_setup(c);
1413         sld_state_setup();
1414         sld_state_show();
1415 }
1416
1417 #define X86_HYBRID_CPU_TYPE_ID_SHIFT    24
1418
1419 /**
1420  * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
1421  *
1422  * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
1423  * a hybrid processor. If the processor is not hybrid, returns 0.
1424  */
1425 u8 get_this_hybrid_cpu_type(void)
1426 {
1427         if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1428                 return 0;
1429
1430         return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;
1431 }