1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
8 #include <asm/hyperv-tlfs.h>
11 * 32-bit intercept words in the VMCB Control Area, starting
12 * at Byte offset 000h.
15 enum intercept_words {
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
28 INTERCEPT_CR3_READ = 3,
29 INTERCEPT_CR4_READ = 4,
30 INTERCEPT_CR8_READ = 8,
31 INTERCEPT_CR0_WRITE = 16,
32 INTERCEPT_CR3_WRITE = 16 + 3,
33 INTERCEPT_CR4_WRITE = 16 + 4,
34 INTERCEPT_CR8_WRITE = 16 + 8,
35 /* Byte offset 004h (word 1) */
36 INTERCEPT_DR0_READ = 32,
44 INTERCEPT_DR0_WRITE = 48,
52 /* Byte offset 008h (word 2) */
53 INTERCEPT_EXCEPTION_OFFSET = 64,
54 /* Byte offset 00Ch (word 3) */
60 INTERCEPT_SELECTIVE_CR0,
84 INTERCEPT_TASK_SWITCH,
85 INTERCEPT_FERR_FREEZE,
87 /* Byte offset 010h (word 4) */
88 INTERCEPT_VMRUN = 128,
100 INTERCEPT_MWAIT_COND,
113 /* Byte offset 014h (word 5) */
114 INTERCEPT_INVLPGB = 160,
115 INTERCEPT_INVLPGB_ILLEGAL,
122 struct __attribute__ ((__packed__)) vmcb_control_area {
123 u32 intercepts[MAX_INTERCEPT];
124 u32 reserved_1[15 - MAX_INTERCEPT];
125 u16 pause_filter_thresh;
126 u16 pause_filter_count;
142 u32 exit_int_info_err;
155 u64 avic_backing_page; /* Offset 0xe0 */
156 u8 reserved_6[8]; /* Offset 0xe8 */
157 u64 avic_logical_id; /* Offset 0xf0 */
158 u64 avic_physical_id; /* Offset 0xf8 */
160 u64 vmsa_pa; /* Used for an SEV-ES guest */
163 * Offset 0x3e0, 32 bytes reserved
164 * for use by hypervisor/software.
167 struct hv_vmcb_enlightenments hv_enlightenments;
173 #define TLB_CONTROL_DO_NOTHING 0
174 #define TLB_CONTROL_FLUSH_ALL_ASID 1
175 #define TLB_CONTROL_FLUSH_ASID 3
176 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
178 #define V_TPR_MASK 0x0f
180 #define V_IRQ_SHIFT 8
181 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
183 #define V_GIF_SHIFT 9
184 #define V_GIF_MASK (1 << V_GIF_SHIFT)
186 #define V_INTR_PRIO_SHIFT 16
187 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
189 #define V_IGN_TPR_SHIFT 20
190 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
192 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
194 #define V_INTR_MASKING_SHIFT 24
195 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
197 #define V_GIF_ENABLE_SHIFT 25
198 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
200 #define AVIC_ENABLE_SHIFT 31
201 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
203 #define X2APIC_MODE_SHIFT 30
204 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
206 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
207 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
209 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
210 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
212 #define SVM_IOIO_STR_SHIFT 2
213 #define SVM_IOIO_REP_SHIFT 3
214 #define SVM_IOIO_SIZE_SHIFT 4
215 #define SVM_IOIO_ASIZE_SHIFT 7
217 #define SVM_IOIO_TYPE_MASK 1
218 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
219 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
220 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
221 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
223 #define SVM_VM_CR_VALID_MASK 0x001fULL
224 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
225 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
227 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
228 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
229 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
232 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
233 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
234 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
235 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
239 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
240 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
241 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
243 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
244 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
245 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
246 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
247 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
249 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
251 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
253 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
254 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
255 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
257 enum avic_ipi_failure_cause {
258 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
259 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
260 AVIC_IPI_FAILURE_INVALID_TARGET,
261 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
262 AVIC_IPI_FAILURE_INVALID_IPI_VECTOR,
265 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(8, 0)
268 * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as
269 * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually.
271 #define AVIC_MAX_PHYSICAL_ID 0XFEULL
274 * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511).
276 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL
278 static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID);
279 static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID);
281 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
282 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
292 /* Save area definition for legacy and SEV-MEM guests */
293 struct vmcb_save_area {
300 struct vmcb_seg gdtr;
301 struct vmcb_seg ldtr;
302 struct vmcb_seg idtr;
340 u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
343 /* Save area definition for SEV-ES and SEV-SNP guests */
344 struct sev_es_save_area {
351 struct vmcb_seg gdtr;
352 struct vmcb_seg ldtr;
353 struct vmcb_seg idtr;
407 u64 reserved_9; /* rax already available at 0x01f8 */
411 u64 reserved_10; /* rsp already available at 0x01d8 */
424 u64 guest_exit_info_1;
425 u64 guest_exit_info_2;
426 u64 guest_exit_int_info;
438 /* Floating point area */
453 struct ghcb_save_area {
493 #define GHCB_SHARED_BUF_SIZE 2032
496 struct ghcb_save_area save;
497 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
499 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
502 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
507 #define EXPECTED_VMCB_SAVE_AREA_SIZE 740
508 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
509 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
510 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
511 #define EXPECTED_GHCB_SIZE PAGE_SIZE
513 static inline void __unused_size_checks(void)
515 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
516 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
517 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
518 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
519 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
523 struct vmcb_control_area control;
524 struct vmcb_save_area save;
527 #define SVM_CPUID_FUNC 0x8000000a
529 #define SVM_VM_CR_SVM_DISABLE 4
531 #define SVM_SELECTOR_S_SHIFT 4
532 #define SVM_SELECTOR_DPL_SHIFT 5
533 #define SVM_SELECTOR_P_SHIFT 7
534 #define SVM_SELECTOR_AVL_SHIFT 8
535 #define SVM_SELECTOR_L_SHIFT 9
536 #define SVM_SELECTOR_DB_SHIFT 10
537 #define SVM_SELECTOR_G_SHIFT 11
539 #define SVM_SELECTOR_TYPE_MASK (0xf)
540 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
541 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
542 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
543 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
544 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
545 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
546 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
548 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
549 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
550 #define SVM_SELECTOR_CODE_MASK (1 << 3)
552 #define SVM_EVTINJ_VEC_MASK 0xff
554 #define SVM_EVTINJ_TYPE_SHIFT 8
555 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
557 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
558 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
559 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
560 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
562 #define SVM_EVTINJ_VALID (1 << 31)
563 #define SVM_EVTINJ_VALID_ERR (1 << 11)
565 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
566 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
568 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
569 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
570 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
571 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
573 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
574 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
576 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
577 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
578 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
580 #define SVM_EXITINFO_REG_MASK 0x0F
582 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
584 /* GHCB Accessor functions */
586 #define GHCB_BITMAP_IDX(field) \
587 (offsetof(struct ghcb_save_area, field) / sizeof(u64))
589 #define DEFINE_GHCB_ACCESSORS(field) \
590 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
592 return test_bit(GHCB_BITMAP_IDX(field), \
593 (unsigned long *)&ghcb->save.valid_bitmap); \
596 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
598 return ghcb->save.field; \
601 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
603 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
606 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
608 __set_bit(GHCB_BITMAP_IDX(field), \
609 (unsigned long *)&ghcb->save.valid_bitmap); \
610 ghcb->save.field = value; \
613 DEFINE_GHCB_ACCESSORS(cpl)
614 DEFINE_GHCB_ACCESSORS(rip)
615 DEFINE_GHCB_ACCESSORS(rsp)
616 DEFINE_GHCB_ACCESSORS(rax)
617 DEFINE_GHCB_ACCESSORS(rcx)
618 DEFINE_GHCB_ACCESSORS(rdx)
619 DEFINE_GHCB_ACCESSORS(rbx)
620 DEFINE_GHCB_ACCESSORS(rbp)
621 DEFINE_GHCB_ACCESSORS(rsi)
622 DEFINE_GHCB_ACCESSORS(rdi)
623 DEFINE_GHCB_ACCESSORS(r8)
624 DEFINE_GHCB_ACCESSORS(r9)
625 DEFINE_GHCB_ACCESSORS(r10)
626 DEFINE_GHCB_ACCESSORS(r11)
627 DEFINE_GHCB_ACCESSORS(r12)
628 DEFINE_GHCB_ACCESSORS(r13)
629 DEFINE_GHCB_ACCESSORS(r14)
630 DEFINE_GHCB_ACCESSORS(r15)
631 DEFINE_GHCB_ACCESSORS(sw_exit_code)
632 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
633 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
634 DEFINE_GHCB_ACCESSORS(sw_scratch)
635 DEFINE_GHCB_ACCESSORS(xcr0)