1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This file contains the definitions for the x86 IO instructions
7 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
8 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
9 * versions of the single-IO instructions (inb_p/inw_p/..).
11 * This file is not meant to be obfuscating: it's just complicated
12 * to (a) handle it all in a way that makes gcc able to optimize it
13 * as well as possible and (b) trying to avoid writing the same thing
14 * over and over again with slight variations and possibly making a
19 * Thanks to James van Artsdalen for a better timing-fix than
20 * the two short jumps: using outb's to a nonexistent port seems
21 * to guarantee better timings even on fast machines.
23 * On the other hand, I'd like to be sure of a non-existent port:
24 * I feel a bit unsafe about using 0x80 (should be safe, though)
30 * Bit simplified and optimized by Jan Hubicka
31 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
33 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
34 * isa_read[wl] and isa_write[wl] fixed
35 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
38 #define ARCH_HAS_IOREMAP_WC
39 #define ARCH_HAS_IOREMAP_WT
41 #include <linux/string.h>
42 #include <linux/compiler.h>
43 #include <linux/cc_platform.h>
45 #include <asm/early_ioremap.h>
46 #include <asm/pgtable_types.h>
47 #include <asm/shared/io.h>
49 #define build_mmio_read(name, size, type, reg, barrier) \
50 static inline type name(const volatile void __iomem *addr) \
51 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
52 :"m" (*(volatile type __force *)addr) barrier); return ret; }
54 #define build_mmio_write(name, size, type, reg, barrier) \
55 static inline void name(type val, volatile void __iomem *addr) \
56 { asm volatile("mov" size " %0,%1": :reg (val), \
57 "m" (*(volatile type __force *)addr) barrier); }
59 build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
60 build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
61 build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
63 build_mmio_read(__readb, "b", unsigned char, "=q", )
64 build_mmio_read(__readw, "w", unsigned short, "=r", )
65 build_mmio_read(__readl, "l", unsigned int, "=r", )
67 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
68 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
69 build_mmio_write(writel, "l", unsigned int, "r", :"memory")
71 build_mmio_write(__writeb, "b", unsigned char, "q", )
72 build_mmio_write(__writew, "w", unsigned short, "r", )
73 build_mmio_write(__writel, "l", unsigned int, "r", )
78 #define readb_relaxed(a) __readb(a)
79 #define readw_relaxed(a) __readw(a)
80 #define readl_relaxed(a) __readl(a)
81 #define __raw_readb __readb
82 #define __raw_readw __readw
83 #define __raw_readl __readl
88 #define writeb_relaxed(v, a) __writeb(v, a)
89 #define writew_relaxed(v, a) __writew(v, a)
90 #define writel_relaxed(v, a) __writel(v, a)
91 #define __raw_writeb __writeb
92 #define __raw_writew __writew
93 #define __raw_writel __writel
97 build_mmio_read(readq, "q", u64, "=r", :"memory")
98 build_mmio_read(__readq, "q", u64, "=r", )
99 build_mmio_write(writeq, "q", u64, "r", :"memory")
100 build_mmio_write(__writeq, "q", u64, "r", )
102 #define readq_relaxed(a) __readq(a)
103 #define writeq_relaxed(v, a) __writeq(v, a)
105 #define __raw_readq __readq
106 #define __raw_writeq __writeq
108 /* Let people know that we have them */
110 #define writeq writeq
114 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
115 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
116 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
119 * virt_to_phys - map virtual addresses to physical
120 * @address: address to remap
122 * The returned physical address is the physical (CPU) mapping for
123 * the memory address given. It is only valid to use this function on
124 * addresses directly mapped or allocated via kmalloc.
126 * This function does not give bus mappings for DMA transfers. In
127 * almost all conceivable cases a device driver should not be using
131 static inline phys_addr_t virt_to_phys(volatile void *address)
133 return __pa(address);
135 #define virt_to_phys virt_to_phys
138 * phys_to_virt - map physical address to virtual
139 * @address: address to remap
141 * The returned virtual address is a current CPU mapping for
142 * the memory address given. It is only valid to use this function on
143 * addresses that have a kernel mapping
145 * This function does not handle bus mappings for DMA transfers. In
146 * almost all conceivable cases a device driver should not be using
150 static inline void *phys_to_virt(phys_addr_t address)
152 return __va(address);
154 #define phys_to_virt phys_to_virt
157 * Change "struct page" to physical address.
159 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
162 * ISA I/O bus memory addresses are 1:1 with the physical address.
163 * However, we truncate the address to unsigned int to avoid undesirable
164 * promotions in legacy drivers.
166 static inline unsigned int isa_virt_to_bus(volatile void *address)
168 return (unsigned int)virt_to_phys(address);
170 #define isa_bus_to_virt phys_to_virt
173 * The default ioremap() behavior is non-cached; if you need something
174 * else, you probably want one of the following.
176 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
177 #define ioremap_uc ioremap_uc
178 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
179 #define ioremap_cache ioremap_cache
180 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
181 #define ioremap_prot ioremap_prot
182 extern void __iomem *ioremap_encrypted(resource_size_t phys_addr, unsigned long size);
183 #define ioremap_encrypted ioremap_encrypted
186 * ioremap - map bus memory into CPU space
187 * @offset: bus address of the memory
188 * @size: size of the resource to map
190 * ioremap performs a platform specific sequence of operations to
191 * make bus memory CPU accessible via the readb/readw/readl/writeb/
192 * writew/writel functions and the other mmio helpers. The returned
193 * address is not guaranteed to be usable directly as a virtual
196 * If the area you are trying to map is a PCI BAR you should have a
197 * look at pci_iomap().
199 void __iomem *ioremap(resource_size_t offset, unsigned long size);
200 #define ioremap ioremap
202 extern void iounmap(volatile void __iomem *addr);
203 #define iounmap iounmap
207 void memcpy_fromio(void *, const volatile void __iomem *, size_t);
208 void memcpy_toio(volatile void __iomem *, const void *, size_t);
209 void memset_io(volatile void __iomem *, int, size_t);
211 #define memcpy_fromio memcpy_fromio
212 #define memcpy_toio memcpy_toio
213 #define memset_io memset_io
215 #include <asm-generic/iomap.h>
218 * ISA space is 'always mapped' on a typical x86 system, no need to
219 * explicitly ioremap() it. The fact that the ISA IO space is mapped
220 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
221 * are physical addresses. The following constant pointer can be
222 * used as the IO-area pointer (it can be iounmapped as well, so the
223 * analogy with PCI is quite large):
225 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
227 #endif /* __KERNEL__ */
229 extern void native_io_delay(void);
231 extern int io_delay_type;
232 extern void io_delay_init(void);
234 #if defined(CONFIG_PARAVIRT)
235 #include <asm/paravirt.h>
238 static inline void slow_down_io(void)
241 #ifdef REALLY_SLOW_IO
250 #define BUILDIO(bwl, bw, type) \
251 static inline void out##bwl##_p(type value, u16 port) \
253 out##bwl(value, port); \
257 static inline type in##bwl##_p(u16 port) \
259 type value = in##bwl(port); \
264 static inline void outs##bwl(u16 port, const void *addr, unsigned long count) \
266 if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \
267 type *value = (type *)addr; \
269 out##bwl(*value, port); \
274 asm volatile("rep; outs" #bwl \
275 : "+S"(addr), "+c"(count) \
276 : "d"(port) : "memory"); \
280 static inline void ins##bwl(u16 port, void *addr, unsigned long count) \
282 if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \
283 type *value = (type *)addr; \
285 *value = in##bwl(port); \
290 asm volatile("rep; ins" #bwl \
291 : "+D"(addr), "+c"(count) \
292 : "d"(port) : "memory"); \
308 #define outb_p outb_p
309 #define outw_p outw_p
310 #define outl_p outl_p
315 extern void *xlate_dev_mem_ptr(phys_addr_t phys);
316 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
318 #define xlate_dev_mem_ptr xlate_dev_mem_ptr
319 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
321 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
322 enum page_cache_mode pcm);
323 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
324 #define ioremap_wc ioremap_wc
325 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
326 #define ioremap_wt ioremap_wt
328 extern bool is_early_ioremap_ptep(pte_t *ptep);
330 #define IO_SPACE_LIMIT 0xffff
332 #include <asm-generic/io.h>
336 extern int __must_check arch_phys_wc_index(int handle);
337 #define arch_phys_wc_index arch_phys_wc_index
339 extern int __must_check arch_phys_wc_add(unsigned long base,
341 extern void arch_phys_wc_del(int handle);
342 #define arch_phys_wc_add arch_phys_wc_add
345 #ifdef CONFIG_X86_PAT
346 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
347 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
348 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
351 #ifdef CONFIG_AMD_MEM_ENCRYPT
352 extern bool arch_memremap_can_ram_remap(resource_size_t offset,
354 unsigned long flags);
355 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
357 extern bool phys_mem_access_encrypted(unsigned long phys_addr,
360 static inline bool phys_mem_access_encrypted(unsigned long phys_addr,
368 * iosubmit_cmds512 - copy data to single MMIO location, in 512-bit units
369 * @dst: destination, in MMIO space (must be 512-bit aligned)
371 * @count: number of 512 bits quantities to submit
373 * Submit data from kernel space to MMIO space, in units of 512 bits at a
374 * time. Order of access is not guaranteed, nor is a memory barrier
375 * performed afterwards.
377 * Warning: Do not use this helper unless your driver has checked that the CPU
378 * instruction is supported on the platform.
380 static inline void iosubmit_cmds512(void __iomem *dst, const void *src,
383 const u8 *from = src;
384 const u8 *end = from + count * 64;
387 movdir64b(dst, from);
392 #endif /* _ASM_X86_IO_H */