x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13 #include <asm/page.h>
  14 /*
  15  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  16  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  17  */
  18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  19 #define HYPERV_CPUID_INTERFACE                  0x40000001
  20 #define HYPERV_CPUID_VERSION                    0x40000002
  21 #define HYPERV_CPUID_FEATURES                   0x40000003
  22 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  23 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  24 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES    0x40000007
  25 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  26 #define HYPERV_CPUID_ISOLATION_CONFIG           0x4000000C
  27
  28 #define HYPERV_CPUID_VIRT_STACK_INTERFACE       0x40000081
  29 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE       0x31235356  /* "VS#1" */
  30
  31 #define HYPERV_CPUID_VIRT_STACK_PROPERTIES      0x40000082
  32 /* Support for the extended IOAPIC RTE format */
  33 #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE    BIT(2)
  34
  35 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  36 #define HYPERV_CPUID_MIN                        0x40000005
  37 #define HYPERV_CPUID_MAX                        0x4000ffff
  38
  39 /*
  40  * Group D Features.  The bit assignments are custom to each architecture.
  41  * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits.
  42  */
  43 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
  44 #define HV_X64_MWAIT_AVAILABLE                          BIT(0)
  45 /* Guest debugging support is available */
  46 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                BIT(1)
  47 /* Performance Monitor support is available*/
  48 #define HV_X64_PERF_MONITOR_AVAILABLE                   BIT(2)
  49 /* Support for physical CPU dynamic partitioning events is available*/
  50 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       BIT(3)
  51 /*
  52  * Support for passing hypercall input parameter block via XMM
  53  * registers is available
  54  */
  55 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE            BIT(4)
  56 /* Support for a virtual guest idle state is available */
  57 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               BIT(5)
  58 /* Frequency MSRs available */
  59 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE             BIT(8)
  60 /* Crash MSR available */
  61 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE            BIT(10)
  62 /* Support for debug MSRs available */
  63 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE                 BIT(11)
  64 /*
  65  * Support for returning hypercall output block via XMM
  66  * registers is available
  67  */
  68 #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE           BIT(15)
  69 /* stimer Direct Mode is available */
  70 #define HV_STIMER_DIRECT_MODE_AVAILABLE                 BIT(19)
  71
  72 /*
  73  * Implementation recommendations. Indicates which behaviors the hypervisor
  74  * recommends the OS implement for optimal performance.
  75  * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
  76  */
  77 /*
  78  * Recommend using hypercall for address space switches rather
  79  * than MOV to CR3 instruction
  80  */
  81 #define HV_X64_AS_SWITCH_RECOMMENDED                    BIT(0)
  82 /* Recommend using hypercall for local TLB flushes rather
  83  * than INVLPG or MOV to CR3 instructions */
  84 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED              BIT(1)
  85 /*
  86  * Recommend using hypercall for remote TLB flushes rather
  87  * than inter-processor interrupts
  88  */
  89 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED             BIT(2)
  90 /*
  91  * Recommend using MSRs for accessing APIC registers
  92  * EOI, ICR and TPR rather than their memory-mapped counterparts
  93  */
  94 #define HV_X64_APIC_ACCESS_RECOMMENDED                  BIT(3)
  95 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
  96 #define HV_X64_SYSTEM_RESET_RECOMMENDED                 BIT(4)
  97 /*
  98  * Recommend using relaxed timing for this partition. If used,
  99  * the VM should disable any watchdog timeouts that rely on the
 100  * timely delivery of external interrupts
 101  */
 102 #define HV_X64_RELAXED_TIMING_RECOMMENDED               BIT(5)
 103
 104 /*
 105  * Recommend not using Auto End-Of-Interrupt feature
 106  */
 107 #define HV_DEPRECATING_AEOI_RECOMMENDED                 BIT(9)
 108
 109 /*
 110  * Recommend using cluster IPI hypercalls.
 111  */
 112 #define HV_X64_CLUSTER_IPI_RECOMMENDED                  BIT(10)
 113
 114 /* Recommend using the newer ExProcessorMasks interface */
 115 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED           BIT(11)
 116
 117 /* Recommend using enlightened VMCS */
 118 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED             BIT(14)
 119
 120 /*
 121  * CPU management features identification.
 122  * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits.
 123  */
 124 #define HV_X64_START_LOGICAL_PROCESSOR                  BIT(0)
 125 #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR            BIT(1)
 126 #define HV_X64_PERFORMANCE_COUNTER_SYNC                 BIT(2)
 127 #define HV_X64_RESERVED_IDENTITY_BIT                    BIT(31)
 128
 129 /*
 130  * Virtual processor will never share a physical core with another virtual
 131  * processor, except for virtual processors that are reported as sibling SMT
 132  * threads.
 133  */
 134 #define HV_X64_NO_NONARCH_CORESHARING                   BIT(18)
 135
 136 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
 137 #define HV_X64_NESTED_DIRECT_FLUSH                      BIT(17)
 138 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH               BIT(18)
 139 #define HV_X64_NESTED_MSR_BITMAP                        BIT(19)
 140
 141 /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */
 142 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL           BIT(0)
 143
 144 /*
 145  * This is specific to AMD and specifies that enlightened TLB flush is
 146  * supported. If guest opts in to this feature, ASID invalidations only
 147  * flushes gva -> hpa mapping entries. To flush the TLB entries derived
 148  * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
 149  * or HvFlushGuestPhysicalAddressList).
 150  */
 151 #define HV_X64_NESTED_ENLIGHTENED_TLB                   BIT(22)
 152
 153 /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
 154 #define HV_PARAVISOR_PRESENT                            BIT(0)
 155
 156 /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */
 157 #define HV_ISOLATION_TYPE                               GENMASK(3, 0)
 158 #define HV_SHARED_GPA_BOUNDARY_ACTIVE                   BIT(5)
 159 #define HV_SHARED_GPA_BOUNDARY_BITS                     GENMASK(11, 6)
 160
 161 enum hv_isolation_type {
 162         HV_ISOLATION_TYPE_NONE  = 0,
 163         HV_ISOLATION_TYPE_VBS   = 1,
 164         HV_ISOLATION_TYPE_SNP   = 2
 165 };
 166
 167 /* Hyper-V specific model specific registers (MSRs) */
 168
 169 /* MSR used to identify the guest OS. */
 170 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 171
 172 /* MSR used to setup pages used to communicate with the hypervisor. */
 173 #define HV_X64_MSR_HYPERCALL                    0x40000001
 174
 175 /* MSR used to provide vcpu index */
 176 #define HV_REGISTER_VP_INDEX                    0x40000002
 177
 178 /* MSR used to reset the guest OS. */
 179 #define HV_X64_MSR_RESET                        0x40000003
 180
 181 /* MSR used to provide vcpu runtime in 100ns units */
 182 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 183
 184 /* MSR used to read the per-partition time reference counter */
 185 #define HV_REGISTER_TIME_REF_COUNT              0x40000020
 186
 187 /* A partition's reference time stamp counter (TSC) page */
 188 #define HV_REGISTER_REFERENCE_TSC               0x40000021
 189
 190 /* MSR used to retrieve the TSC frequency */
 191 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 192
 193 /* MSR used to retrieve the local APIC timer frequency */
 194 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 195
 196 /* Define the virtual APIC registers */
 197 #define HV_X64_MSR_EOI                          0x40000070
 198 #define HV_X64_MSR_ICR                          0x40000071
 199 #define HV_X64_MSR_TPR                          0x40000072
 200 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 201
 202 /* Define synthetic interrupt controller model specific registers. */
 203 #define HV_REGISTER_SCONTROL                    0x40000080
 204 #define HV_REGISTER_SVERSION                    0x40000081
 205 #define HV_REGISTER_SIEFP                       0x40000082
 206 #define HV_REGISTER_SIMP                        0x40000083
 207 #define HV_REGISTER_EOM                         0x40000084
 208 #define HV_REGISTER_SINT0                       0x40000090
 209 #define HV_REGISTER_SINT1                       0x40000091
 210 #define HV_REGISTER_SINT2                       0x40000092
 211 #define HV_REGISTER_SINT3                       0x40000093
 212 #define HV_REGISTER_SINT4                       0x40000094
 213 #define HV_REGISTER_SINT5                       0x40000095
 214 #define HV_REGISTER_SINT6                       0x40000096
 215 #define HV_REGISTER_SINT7                       0x40000097
 216 #define HV_REGISTER_SINT8                       0x40000098
 217 #define HV_REGISTER_SINT9                       0x40000099
 218 #define HV_REGISTER_SINT10                      0x4000009A
 219 #define HV_REGISTER_SINT11                      0x4000009B
 220 #define HV_REGISTER_SINT12                      0x4000009C
 221 #define HV_REGISTER_SINT13                      0x4000009D
 222 #define HV_REGISTER_SINT14                      0x4000009E
 223 #define HV_REGISTER_SINT15                      0x4000009F
 224
 225 /*
 226  * Synthetic Timer MSRs. Four timers per vcpu.
 227  */
 228 #define HV_REGISTER_STIMER0_CONFIG              0x400000B0
 229 #define HV_REGISTER_STIMER0_COUNT               0x400000B1
 230 #define HV_REGISTER_STIMER1_CONFIG              0x400000B2
 231 #define HV_REGISTER_STIMER1_COUNT               0x400000B3
 232 #define HV_REGISTER_STIMER2_CONFIG              0x400000B4
 233 #define HV_REGISTER_STIMER2_COUNT               0x400000B5
 234 #define HV_REGISTER_STIMER3_CONFIG              0x400000B6
 235 #define HV_REGISTER_STIMER3_COUNT               0x400000B7
 236
 237 /* Hyper-V guest idle MSR */
 238 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 239
 240 /* Hyper-V guest crash notification MSR's */
 241 #define HV_REGISTER_CRASH_P0                    0x40000100
 242 #define HV_REGISTER_CRASH_P1                    0x40000101
 243 #define HV_REGISTER_CRASH_P2                    0x40000102
 244 #define HV_REGISTER_CRASH_P3                    0x40000103
 245 #define HV_REGISTER_CRASH_P4                    0x40000104
 246 #define HV_REGISTER_CRASH_CTL                   0x40000105
 247
 248 /* TSC emulation after migration */
 249 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 250 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 251 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 252
 253 /* TSC invariant control */
 254 #define HV_X64_MSR_TSC_INVARIANT_CONTROL        0x40000118
 255
 256 /* Register name aliases for temporary compatibility */
 257 #define HV_X64_MSR_STIMER0_COUNT        HV_REGISTER_STIMER0_COUNT
 258 #define HV_X64_MSR_STIMER0_CONFIG       HV_REGISTER_STIMER0_CONFIG
 259 #define HV_X64_MSR_STIMER1_COUNT        HV_REGISTER_STIMER1_COUNT
 260 #define HV_X64_MSR_STIMER1_CONFIG       HV_REGISTER_STIMER1_CONFIG
 261 #define HV_X64_MSR_STIMER2_COUNT        HV_REGISTER_STIMER2_COUNT
 262 #define HV_X64_MSR_STIMER2_CONFIG       HV_REGISTER_STIMER2_CONFIG
 263 #define HV_X64_MSR_STIMER3_COUNT        HV_REGISTER_STIMER3_COUNT
 264 #define HV_X64_MSR_STIMER3_CONFIG       HV_REGISTER_STIMER3_CONFIG
 265 #define HV_X64_MSR_SCONTROL             HV_REGISTER_SCONTROL
 266 #define HV_X64_MSR_SVERSION             HV_REGISTER_SVERSION
 267 #define HV_X64_MSR_SIMP                 HV_REGISTER_SIMP
 268 #define HV_X64_MSR_SIEFP                HV_REGISTER_SIEFP
 269 #define HV_X64_MSR_VP_INDEX             HV_REGISTER_VP_INDEX
 270 #define HV_X64_MSR_EOM                  HV_REGISTER_EOM
 271 #define HV_X64_MSR_SINT0                HV_REGISTER_SINT0
 272 #define HV_X64_MSR_SINT15               HV_REGISTER_SINT15
 273 #define HV_X64_MSR_CRASH_P0             HV_REGISTER_CRASH_P0
 274 #define HV_X64_MSR_CRASH_P1             HV_REGISTER_CRASH_P1
 275 #define HV_X64_MSR_CRASH_P2             HV_REGISTER_CRASH_P2
 276 #define HV_X64_MSR_CRASH_P3             HV_REGISTER_CRASH_P3
 277 #define HV_X64_MSR_CRASH_P4             HV_REGISTER_CRASH_P4
 278 #define HV_X64_MSR_CRASH_CTL            HV_REGISTER_CRASH_CTL
 279 #define HV_X64_MSR_TIME_REF_COUNT       HV_REGISTER_TIME_REF_COUNT
 280 #define HV_X64_MSR_REFERENCE_TSC        HV_REGISTER_REFERENCE_TSC
 281
 282 /* Hyper-V memory host visibility */
 283 enum hv_mem_host_visibility {
 284         VMBUS_PAGE_NOT_VISIBLE          = 0,
 285         VMBUS_PAGE_VISIBLE_READ_ONLY    = 1,
 286         VMBUS_PAGE_VISIBLE_READ_WRITE   = 3
 287 };
 288
 289 /* HvCallModifySparseGpaPageHostVisibility hypercall */
 290 #define HV_MAX_MODIFY_GPA_REP_COUNT     ((PAGE_SIZE / sizeof(u64)) - 2)
 291 struct hv_gpa_range_for_visibility {
 292         u64 partition_id;
 293         u32 host_visibility:2;
 294         u32 reserved0:30;
 295         u32 reserved1;
 296         u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT];
 297 } __packed;
 298
 299 /*
 300  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 301  */
 302 union hv_x64_msr_hypercall_contents {
 303         u64 as_uint64;
 304         struct {
 305                 u64 enable:1;
 306                 u64 reserved:11;
 307                 u64 guest_physical_address:52;
 308         } __packed;
 309 };
 310
 311 union hv_vp_assist_msr_contents {
 312         u64 as_uint64;
 313         struct {
 314                 u64 enable:1;
 315                 u64 reserved:11;
 316                 u64 pfn:52;
 317         } __packed;
 318 };
 319
 320 struct hv_reenlightenment_control {
 321         __u64 vector:8;
 322         __u64 reserved1:8;
 323         __u64 enabled:1;
 324         __u64 reserved2:15;
 325         __u64 target_vp:32;
 326 }  __packed;
 327
 328 struct hv_tsc_emulation_control {
 329         __u64 enabled:1;
 330         __u64 reserved:63;
 331 } __packed;
 332
 333 struct hv_tsc_emulation_status {
 334         __u64 inprogress:1;
 335         __u64 reserved:63;
 336 } __packed;
 337
 338 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 339 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 340 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 341                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 342
 343 #define HV_X64_MSR_CRASH_PARAMS         \
 344                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 345
 346 #define HV_IPI_LOW_VECTOR       0x10
 347 #define HV_IPI_HIGH_VECTOR      0xff
 348
 349 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 350 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 351 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 352                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 353
 354 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 355 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 356
 357 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 358 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 359
 360 /* Number of XMM registers used in hypercall input/output */
 361 #define HV_HYPERCALL_MAX_XMM_REGISTERS          6
 362
 363 struct hv_nested_enlightenments_control {
 364         struct {
 365                 __u32 directhypercall:1;
 366                 __u32 reserved:31;
 367         } features;
 368         struct {
 369                 __u32 reserved;
 370         } hypercallControls;
 371 } __packed;
 372
 373 /* Define virtual processor assist page structure. */
 374 struct hv_vp_assist_page {
 375         __u32 apic_assist;
 376         __u32 reserved1;
 377         __u64 vtl_control[3];
 378         struct hv_nested_enlightenments_control nested_control;
 379         __u8 enlighten_vmentry;
 380         __u8 reserved2[7];
 381         __u64 current_nested_vmcs;
 382 } __packed;
 383
 384 struct hv_enlightened_vmcs {
 385         u32 revision_id;
 386         u32 abort;
 387
 388         u16 host_es_selector;
 389         u16 host_cs_selector;
 390         u16 host_ss_selector;
 391         u16 host_ds_selector;
 392         u16 host_fs_selector;
 393         u16 host_gs_selector;
 394         u16 host_tr_selector;
 395
 396         u16 padding16_1;
 397
 398         u64 host_ia32_pat;
 399         u64 host_ia32_efer;
 400
 401         u64 host_cr0;
 402         u64 host_cr3;
 403         u64 host_cr4;
 404
 405         u64 host_ia32_sysenter_esp;
 406         u64 host_ia32_sysenter_eip;
 407         u64 host_rip;
 408         u32 host_ia32_sysenter_cs;
 409
 410         u32 pin_based_vm_exec_control;
 411         u32 vm_exit_controls;
 412         u32 secondary_vm_exec_control;
 413
 414         u64 io_bitmap_a;
 415         u64 io_bitmap_b;
 416         u64 msr_bitmap;
 417
 418         u16 guest_es_selector;
 419         u16 guest_cs_selector;
 420         u16 guest_ss_selector;
 421         u16 guest_ds_selector;
 422         u16 guest_fs_selector;
 423         u16 guest_gs_selector;
 424         u16 guest_ldtr_selector;
 425         u16 guest_tr_selector;
 426
 427         u32 guest_es_limit;
 428         u32 guest_cs_limit;
 429         u32 guest_ss_limit;
 430         u32 guest_ds_limit;
 431         u32 guest_fs_limit;
 432         u32 guest_gs_limit;
 433         u32 guest_ldtr_limit;
 434         u32 guest_tr_limit;
 435         u32 guest_gdtr_limit;
 436         u32 guest_idtr_limit;
 437
 438         u32 guest_es_ar_bytes;
 439         u32 guest_cs_ar_bytes;
 440         u32 guest_ss_ar_bytes;
 441         u32 guest_ds_ar_bytes;
 442         u32 guest_fs_ar_bytes;
 443         u32 guest_gs_ar_bytes;
 444         u32 guest_ldtr_ar_bytes;
 445         u32 guest_tr_ar_bytes;
 446
 447         u64 guest_es_base;
 448         u64 guest_cs_base;
 449         u64 guest_ss_base;
 450         u64 guest_ds_base;
 451         u64 guest_fs_base;
 452         u64 guest_gs_base;
 453         u64 guest_ldtr_base;
 454         u64 guest_tr_base;
 455         u64 guest_gdtr_base;
 456         u64 guest_idtr_base;
 457
 458         u64 padding64_1[3];
 459
 460         u64 vm_exit_msr_store_addr;
 461         u64 vm_exit_msr_load_addr;
 462         u64 vm_entry_msr_load_addr;
 463
 464         u64 cr3_target_value0;
 465         u64 cr3_target_value1;
 466         u64 cr3_target_value2;
 467         u64 cr3_target_value3;
 468
 469         u32 page_fault_error_code_mask;
 470         u32 page_fault_error_code_match;
 471
 472         u32 cr3_target_count;
 473         u32 vm_exit_msr_store_count;
 474         u32 vm_exit_msr_load_count;
 475         u32 vm_entry_msr_load_count;
 476
 477         u64 tsc_offset;
 478         u64 virtual_apic_page_addr;
 479         u64 vmcs_link_pointer;
 480
 481         u64 guest_ia32_debugctl;
 482         u64 guest_ia32_pat;
 483         u64 guest_ia32_efer;
 484
 485         u64 guest_pdptr0;
 486         u64 guest_pdptr1;
 487         u64 guest_pdptr2;
 488         u64 guest_pdptr3;
 489
 490         u64 guest_pending_dbg_exceptions;
 491         u64 guest_sysenter_esp;
 492         u64 guest_sysenter_eip;
 493
 494         u32 guest_activity_state;
 495         u32 guest_sysenter_cs;
 496
 497         u64 cr0_guest_host_mask;
 498         u64 cr4_guest_host_mask;
 499         u64 cr0_read_shadow;
 500         u64 cr4_read_shadow;
 501         u64 guest_cr0;
 502         u64 guest_cr3;
 503         u64 guest_cr4;
 504         u64 guest_dr7;
 505
 506         u64 host_fs_base;
 507         u64 host_gs_base;
 508         u64 host_tr_base;
 509         u64 host_gdtr_base;
 510         u64 host_idtr_base;
 511         u64 host_rsp;
 512
 513         u64 ept_pointer;
 514
 515         u16 virtual_processor_id;
 516         u16 padding16_2[3];
 517
 518         u64 padding64_2[5];
 519         u64 guest_physical_address;
 520
 521         u32 vm_instruction_error;
 522         u32 vm_exit_reason;
 523         u32 vm_exit_intr_info;
 524         u32 vm_exit_intr_error_code;
 525         u32 idt_vectoring_info_field;
 526         u32 idt_vectoring_error_code;
 527         u32 vm_exit_instruction_len;
 528         u32 vmx_instruction_info;
 529
 530         u64 exit_qualification;
 531         u64 exit_io_instruction_ecx;
 532         u64 exit_io_instruction_esi;
 533         u64 exit_io_instruction_edi;
 534         u64 exit_io_instruction_eip;
 535
 536         u64 guest_linear_address;
 537         u64 guest_rsp;
 538         u64 guest_rflags;
 539
 540         u32 guest_interruptibility_info;
 541         u32 cpu_based_vm_exec_control;
 542         u32 exception_bitmap;
 543         u32 vm_entry_controls;
 544         u32 vm_entry_intr_info_field;
 545         u32 vm_entry_exception_error_code;
 546         u32 vm_entry_instruction_len;
 547         u32 tpr_threshold;
 548
 549         u64 guest_rip;
 550
 551         u32 hv_clean_fields;
 552         u32 padding32_1;
 553         u32 hv_synthetic_controls;
 554         struct {
 555                 u32 nested_flush_hypercall:1;
 556                 u32 msr_bitmap:1;
 557                 u32 reserved:30;
 558         }  __packed hv_enlightenments_control;
 559         u32 hv_vp_id;
 560         u32 padding32_2;
 561         u64 hv_vm_id;
 562         u64 partition_assist_page;
 563         u64 padding64_4[4];
 564         u64 guest_bndcfgs;
 565         u64 guest_ia32_perf_global_ctrl;
 566         u64 guest_ia32_s_cet;
 567         u64 guest_ssp;
 568         u64 guest_ia32_int_ssp_table_addr;
 569         u64 guest_ia32_lbr_ctl;
 570         u64 padding64_5[2];
 571         u64 xss_exit_bitmap;
 572         u64 encls_exiting_bitmap;
 573         u64 host_ia32_perf_global_ctrl;
 574         u64 tsc_multiplier;
 575         u64 host_ia32_s_cet;
 576         u64 host_ssp;
 577         u64 host_ia32_int_ssp_table_addr;
 578         u64 padding64_6;
 579 } __packed;
 580
 581 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 582 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 583 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 584 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 585 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 586 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 587 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 588 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 589 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 590 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 591 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 592 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 593 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 594 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 595 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 596 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 597 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 598
 599 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 600
 601 /*
 602  * Hyper-V uses the software reserved 32 bytes in VMCB control area to expose
 603  * SVM enlightenments to guests.
 604  */
 605 struct hv_vmcb_enlightenments {
 606         struct __packed hv_enlightenments_control {
 607                 u32 nested_flush_hypercall:1;
 608                 u32 msr_bitmap:1;
 609                 u32 enlightened_npt_tlb: 1;
 610                 u32 reserved:29;
 611         } __packed hv_enlightenments_control;
 612         u32 hv_vp_id;
 613         u64 hv_vm_id;
 614         u64 partition_assist_page;
 615         u64 reserved;
 616 } __packed;
 617
 618 /*
 619  * Hyper-V uses the software reserved clean bit in VMCB.
 620  */
 621 #define HV_VMCB_NESTED_ENLIGHTENMENTS           31
 622
 623 struct hv_partition_assist_pg {
 624         u32 tlb_lock_count;
 625 };
 626
 627 enum hv_interrupt_type {
 628         HV_X64_INTERRUPT_TYPE_FIXED             = 0x0000,
 629         HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY    = 0x0001,
 630         HV_X64_INTERRUPT_TYPE_SMI               = 0x0002,
 631         HV_X64_INTERRUPT_TYPE_REMOTEREAD        = 0x0003,
 632         HV_X64_INTERRUPT_TYPE_NMI               = 0x0004,
 633         HV_X64_INTERRUPT_TYPE_INIT              = 0x0005,
 634         HV_X64_INTERRUPT_TYPE_SIPI              = 0x0006,
 635         HV_X64_INTERRUPT_TYPE_EXTINT            = 0x0007,
 636         HV_X64_INTERRUPT_TYPE_LOCALINT0         = 0x0008,
 637         HV_X64_INTERRUPT_TYPE_LOCALINT1         = 0x0009,
 638         HV_X64_INTERRUPT_TYPE_MAXIMUM           = 0x000A,
 639 };
 640
 641 union hv_msi_address_register {
 642         u32 as_uint32;
 643         struct {
 644                 u32 reserved1:2;
 645                 u32 destination_mode:1;
 646                 u32 redirection_hint:1;
 647                 u32 reserved2:8;
 648                 u32 destination_id:8;
 649                 u32 msi_base:12;
 650         };
 651 } __packed;
 652
 653 union hv_msi_data_register {
 654         u32 as_uint32;
 655         struct {
 656                 u32 vector:8;
 657                 u32 delivery_mode:3;
 658                 u32 reserved1:3;
 659                 u32 level_assert:1;
 660                 u32 trigger_mode:1;
 661                 u32 reserved2:16;
 662         };
 663 } __packed;
 664
 665 /* HvRetargetDeviceInterrupt hypercall */
 666 union hv_msi_entry {
 667         u64 as_uint64;
 668         struct {
 669                 union hv_msi_address_register address;
 670                 union hv_msi_data_register data;
 671         } __packed;
 672 };
 673
 674 #include <asm-generic/hyperv-tlfs.h>
 675
 676 #endif