1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
5 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
14 #include <asm/hardirq.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
26 /* Macros for apic_extnmi which controls external NMI masking */
27 #define APIC_EXTNMI_BSP 0 /* Default */
28 #define APIC_EXTNMI_ALL 1
29 #define APIC_EXTNMI_NONE 2
32 * Define the default level of output to be very little
33 * This can be turned up by using apic=verbose for more
34 * information and apic=debug for _lots_ of information.
35 * apic_verbosity is defined in apic.c
37 #define apic_printk(v, s, a...) do { \
38 if ((v) <= apic_verbosity) \
43 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
44 extern void generic_apic_probe(void);
46 static inline void generic_apic_probe(void)
51 #ifdef CONFIG_X86_LOCAL_APIC
53 extern int apic_verbosity;
54 extern int local_apic_timer_c2_ok;
56 extern int disable_apic;
57 extern unsigned int lapic_timer_period;
59 extern enum apic_intr_mode_id apic_intr_mode;
60 enum apic_intr_mode_id {
63 APIC_VIRTUAL_WIRE_NO_CONFIG,
65 APIC_SYMMETRIC_IO_NO_ROUTING
69 extern void __inquire_remote_apic(int apicid);
70 #else /* CONFIG_SMP */
71 static inline void __inquire_remote_apic(int apicid)
74 #endif /* CONFIG_SMP */
76 static inline void default_inquire_remote_apic(int apicid)
78 if (apic_verbosity >= APIC_DEBUG)
79 __inquire_remote_apic(apicid);
83 * With 82489DX we can't rely on apic feature bit
84 * retrieved via cpuid but still have to deal with
85 * such an apic chip so we assume that SMP configuration
86 * is found from MP table (64bit case uses ACPI mostly
87 * which set smp presence flag as well so we are safe
88 * to use this helper too).
90 static inline bool apic_from_smp_config(void)
92 return smp_found_config && !disable_apic;
96 * Basic functions accessing APICs.
98 #ifdef CONFIG_PARAVIRT
99 #include <asm/paravirt.h>
102 static inline void native_apic_mem_write(u32 reg, u32 v)
104 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
106 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
107 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
108 ASM_OUTPUT2("0" (v), "m" (*addr)));
111 static inline u32 native_apic_mem_read(u32 reg)
113 return readl((void __iomem *)(APIC_BASE + reg));
116 extern void native_apic_wait_icr_idle(void);
117 extern u32 native_safe_apic_wait_icr_idle(void);
118 extern void native_apic_icr_write(u32 low, u32 id);
119 extern u64 native_apic_icr_read(void);
121 static inline bool apic_is_x2apic_enabled(void)
125 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
127 return msr & X2APIC_ENABLE;
130 extern void enable_IR_x2apic(void);
132 extern int get_physical_broadcast(void);
134 extern int lapic_get_maxlvt(void);
135 extern void clear_local_APIC(void);
136 extern void disconnect_bsp_APIC(int virt_wire_setup);
137 extern void disable_local_APIC(void);
138 extern void apic_soft_disable(void);
139 extern void lapic_shutdown(void);
140 extern void sync_Arb_IDs(void);
141 extern void init_bsp_APIC(void);
142 extern void apic_intr_mode_select(void);
143 extern void apic_intr_mode_init(void);
144 extern void init_apic_mappings(void);
145 void register_lapic_address(unsigned long address);
146 extern void setup_boot_APIC_clock(void);
147 extern void setup_secondary_APIC_clock(void);
148 extern void lapic_update_tsc_freq(void);
151 static inline int apic_force_enable(unsigned long addr)
156 extern int apic_force_enable(unsigned long addr);
159 extern void apic_ap_setup(void);
162 * On 32bit this is mach-xxx local
165 extern int apic_is_clustered_box(void);
167 static inline int apic_is_clustered_box(void)
173 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
174 extern void lapic_assign_system_vectors(void);
175 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
176 extern void lapic_update_legacy_vectors(void);
177 extern void lapic_online(void);
178 extern void lapic_offline(void);
179 extern bool apic_needs_pit(void);
181 extern void apic_send_IPI_allbutself(unsigned int vector);
183 #else /* !CONFIG_X86_LOCAL_APIC */
184 static inline void lapic_shutdown(void) { }
185 #define local_apic_timer_c2_ok 1
186 static inline void init_apic_mappings(void) { }
187 static inline void disable_local_APIC(void) { }
188 # define setup_boot_APIC_clock x86_init_noop
189 # define setup_secondary_APIC_clock x86_init_noop
190 static inline void lapic_update_tsc_freq(void) { }
191 static inline void init_bsp_APIC(void) { }
192 static inline void apic_intr_mode_select(void) { }
193 static inline void apic_intr_mode_init(void) { }
194 static inline void lapic_assign_system_vectors(void) { }
195 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
196 static inline bool apic_needs_pit(void) { return true; }
197 #endif /* !CONFIG_X86_LOCAL_APIC */
199 #ifdef CONFIG_X86_X2APIC
200 static inline void native_apic_msr_write(u32 reg, u32 v)
202 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
206 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
209 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
211 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
214 static inline u32 native_apic_msr_read(u32 reg)
221 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
225 static inline void native_x2apic_wait_icr_idle(void)
227 /* no need to wait for icr idle in x2apic */
231 static inline u32 native_safe_x2apic_wait_icr_idle(void)
233 /* no need to wait for icr idle in x2apic */
237 static inline void native_x2apic_icr_write(u32 low, u32 id)
239 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
242 static inline u64 native_x2apic_icr_read(void)
246 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
250 extern int x2apic_mode;
251 extern int x2apic_phys;
252 extern void __init x2apic_set_max_apicid(u32 apicid);
253 extern void x2apic_setup(void);
254 static inline int x2apic_enabled(void)
256 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
259 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
260 #else /* !CONFIG_X86_X2APIC */
261 static inline void x2apic_setup(void) { }
262 static inline int x2apic_enabled(void) { return 0; }
264 #define x2apic_mode (0)
265 #define x2apic_supported() (0)
266 #endif /* !CONFIG_X86_X2APIC */
267 extern void __init check_x2apic(void);
272 * Copyright 2004 James Cleverdon, IBM.
274 * Generic APIC sub-arch data struct.
276 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
277 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
281 /* Hotpath functions first */
282 void (*eoi_write)(u32 reg, u32 v);
283 void (*native_eoi_write)(u32 reg, u32 v);
284 void (*write)(u32 reg, u32 v);
285 u32 (*read)(u32 reg);
287 /* IPI related functions */
288 void (*wait_icr_idle)(void);
289 u32 (*safe_wait_icr_idle)(void);
291 void (*send_IPI)(int cpu, int vector);
292 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
293 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
294 void (*send_IPI_allbutself)(int vector);
295 void (*send_IPI_all)(int vector);
296 void (*send_IPI_self)(int vector);
300 enum apic_delivery_modes delivery_mode;
301 bool dest_mode_logical;
303 u32 (*calc_dest_apicid)(unsigned int cpu);
305 /* ICR related functions */
306 u64 (*icr_read)(void);
307 void (*icr_write)(u32 low, u32 high);
309 /* Probe, setup and smpboot functions */
311 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
312 int (*apic_id_valid)(u32 apicid);
313 int (*apic_id_registered)(void);
315 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
316 void (*init_apic_ldr)(void);
317 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
318 void (*setup_apic_routing)(void);
319 int (*cpu_present_to_apicid)(int mps_cpu);
320 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
321 int (*check_phys_apicid_present)(int phys_apicid);
322 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
324 u32 (*get_apic_id)(unsigned long x);
325 u32 (*set_apic_id)(unsigned int id);
327 /* wakeup_secondary_cpu */
328 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
329 /* wakeup secondary CPU using 64-bit wakeup point */
330 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
332 void (*inquire_remote_apic)(int apicid);
336 * Called very early during boot from get_smp_config(). It should
337 * return the logical apicid. x86_[bios]_cpu_to_apicid is
338 * initialized before this function is called.
340 * If logical apicid can't be determined that early, the function
341 * may return BAD_APICID. Logical apicid will be configured after
342 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
343 * won't be applied properly during early boot in this case.
345 int (*x86_32_early_logical_apicid)(int cpu);
351 * Pointer to the local APIC driver in use on this system (there's
352 * always just one such driver in use - the kernel decides via an
353 * early probing process which one it picks - and then sticks to it):
355 extern struct apic *apic;
358 * APIC drivers are probed based on how they are listed in the .apicdrivers
359 * section. So the order is important and enforced by the ordering
360 * of different apic driver files in the Makefile.
362 * For the files having two apic drivers, we use apic_drivers()
363 * to enforce the order with in them.
365 #define apic_driver(sym) \
366 static const struct apic *__apicdrivers_##sym __used \
367 __aligned(sizeof(struct apic *)) \
368 __section(".apicdrivers") = { &sym }
370 #define apic_drivers(sym1, sym2) \
371 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
372 __aligned(sizeof(struct apic *)) \
373 __section(".apicdrivers") = { &sym1, &sym2 }
375 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
378 * APIC functionality to boot other CPUs - only used on SMP:
381 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
382 extern int lapic_can_unplug_cpu(void);
385 #ifdef CONFIG_X86_LOCAL_APIC
387 static inline u32 apic_read(u32 reg)
389 return apic->read(reg);
392 static inline void apic_write(u32 reg, u32 val)
394 apic->write(reg, val);
397 static inline void apic_eoi(void)
399 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
402 static inline u64 apic_icr_read(void)
404 return apic->icr_read();
407 static inline void apic_icr_write(u32 low, u32 high)
409 apic->icr_write(low, high);
412 static inline void apic_wait_icr_idle(void)
414 apic->wait_icr_idle();
417 static inline u32 safe_apic_wait_icr_idle(void)
419 return apic->safe_wait_icr_idle();
422 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
424 #else /* CONFIG_X86_LOCAL_APIC */
426 static inline u32 apic_read(u32 reg) { return 0; }
427 static inline void apic_write(u32 reg, u32 val) { }
428 static inline void apic_eoi(void) { }
429 static inline u64 apic_icr_read(void) { return 0; }
430 static inline void apic_icr_write(u32 low, u32 high) { }
431 static inline void apic_wait_icr_idle(void) { }
432 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
433 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
435 #endif /* CONFIG_X86_LOCAL_APIC */
437 extern void apic_ack_irq(struct irq_data *data);
439 static inline void ack_APIC_irq(void)
442 * ack_APIC_irq() actually gets compiled as a single instruction
449 static inline bool lapic_vector_set_in_irr(unsigned int vector)
451 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
453 return !!(irr & (1U << (vector % 32)));
456 static inline unsigned default_get_apic_id(unsigned long x)
458 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
460 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
461 return (x >> 24) & 0xFF;
463 return (x >> 24) & 0x0F;
467 * Warm reset vector position:
469 #define TRAMPOLINE_PHYS_LOW 0x467
470 #define TRAMPOLINE_PHYS_HIGH 0x469
472 extern void generic_bigsmp_probe(void);
474 #ifdef CONFIG_X86_LOCAL_APIC
478 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
480 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
482 extern struct apic apic_noop;
484 static inline unsigned int read_apic_id(void)
486 unsigned int reg = apic_read(APIC_ID);
488 return apic->get_apic_id(reg);
492 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
493 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler);
496 extern int default_apic_id_valid(u32 apicid);
497 extern int default_acpi_madt_oem_check(char *, char *);
498 extern void default_setup_apic_routing(void);
500 extern u32 apic_default_calc_apicid(unsigned int cpu);
501 extern u32 apic_flat_calc_apicid(unsigned int cpu);
503 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
504 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
505 extern int default_cpu_present_to_apicid(int mps_cpu);
506 extern int default_check_phys_apicid_present(int phys_apicid);
508 #endif /* CONFIG_X86_LOCAL_APIC */
511 bool apic_id_is_primary_thread(unsigned int id);
512 void apic_smt_update(void);
514 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
515 static inline void apic_smt_update(void) { }
521 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
524 extern void ioapic_zap_locks(void);
526 #endif /* _ASM_X86_APIC_H */