x86/events/intel/uncore_discovery.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Support Intel uncore PerfMon discovery mechanism.
   4  * Copyright(c) 2021 Intel Corporation.
   5  */
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include "uncore.h"
   9 #include "uncore_discovery.h"
  10
  11 static struct rb_root discovery_tables = RB_ROOT;
  12 static int num_discovered_types[UNCORE_ACCESS_MAX];
  13
  14 static bool has_generic_discovery_table(void)
  15 {
  16         struct pci_dev *dev;
  17         int dvsec;
  18
  19         dev = pci_get_device(PCI_VENDOR_ID_INTEL, UNCORE_DISCOVERY_TABLE_DEVICE, NULL);
  20         if (!dev)
  21                 return false;
  22
  23         /* A discovery table device has the unique capability ID. */
  24         dvsec = pci_find_next_ext_capability(dev, 0, UNCORE_EXT_CAP_ID_DISCOVERY);
  25         pci_dev_put(dev);
  26         if (dvsec)
  27                 return true;
  28
  29         return false;
  30 }
  31
  32 static int logical_die_id;
  33
  34 static int get_device_die_id(struct pci_dev *dev)
  35 {
  36         int cpu, node = pcibus_to_node(dev->bus);
  37
  38         /*
  39          * If the NUMA info is not available, assume that the logical die id is
  40          * continuous in the order in which the discovery table devices are
  41          * detected.
  42          */
  43         if (node < 0)
  44                 return logical_die_id++;
  45
  46         for_each_cpu(cpu, cpumask_of_node(node)) {
  47                 struct cpuinfo_x86 *c = &cpu_data(cpu);
  48
  49                 if (c->initialized && cpu_to_node(cpu) == node)
  50                         return c->logical_die_id;
  51         }
  52
  53         /*
  54          * All CPUs of a node may be offlined. For this case,
  55          * the PCI and MMIO type of uncore blocks which are
  56          * enumerated by the device will be unavailable.
  57          */
  58         return -1;
  59 }
  60
  61 #define __node_2_type(cur)      \
  62         rb_entry((cur), struct intel_uncore_discovery_type, node)
  63
  64 static inline int __type_cmp(const void *key, const struct rb_node *b)
  65 {
  66         struct intel_uncore_discovery_type *type_b = __node_2_type(b);
  67         const u16 *type_id = key;
  68
  69         if (type_b->type > *type_id)
  70                 return -1;
  71         else if (type_b->type < *type_id)
  72                 return 1;
  73
  74         return 0;
  75 }
  76
  77 static inline struct intel_uncore_discovery_type *
  78 search_uncore_discovery_type(u16 type_id)
  79 {
  80         struct rb_node *node = rb_find(&type_id, &discovery_tables, __type_cmp);
  81
  82         return (node) ? __node_2_type(node) : NULL;
  83 }
  84
  85 static inline bool __type_less(struct rb_node *a, const struct rb_node *b)
  86 {
  87         return (__node_2_type(a)->type < __node_2_type(b)->type);
  88 }
  89
  90 static struct intel_uncore_discovery_type *
  91 add_uncore_discovery_type(struct uncore_unit_discovery *unit)
  92 {
  93         struct intel_uncore_discovery_type *type;
  94
  95         if (unit->access_type >= UNCORE_ACCESS_MAX) {
  96                 pr_warn("Unsupported access type %d\n", unit->access_type);
  97                 return NULL;
  98         }
  99
 100         type = kzalloc(sizeof(struct intel_uncore_discovery_type), GFP_KERNEL);
 101         if (!type)
 102                 return NULL;
 103
 104         type->box_ctrl_die = kcalloc(__uncore_max_dies, sizeof(u64), GFP_KERNEL);
 105         if (!type->box_ctrl_die)
 106                 goto free_type;
 107
 108         type->access_type = unit->access_type;
 109         num_discovered_types[type->access_type]++;
 110         type->type = unit->box_type;
 111
 112         rb_add(&type->node, &discovery_tables, __type_less);
 113
 114         return type;
 115
 116 free_type:
 117         kfree(type);
 118
 119         return NULL;
 120
 121 }
 122
 123 static struct intel_uncore_discovery_type *
 124 get_uncore_discovery_type(struct uncore_unit_discovery *unit)
 125 {
 126         struct intel_uncore_discovery_type *type;
 127
 128         type = search_uncore_discovery_type(unit->box_type);
 129         if (type)
 130                 return type;
 131
 132         return add_uncore_discovery_type(unit);
 133 }
 134
 135 static void
 136 uncore_insert_box_info(struct uncore_unit_discovery *unit,
 137                        int die, bool parsed)
 138 {
 139         struct intel_uncore_discovery_type *type;
 140         unsigned int *box_offset, *ids;
 141         int i;
 142
 143         if (!unit->ctl || !unit->ctl_offset || !unit->ctr_offset) {
 144                 pr_info("Invalid address is detected for uncore type %d box %d, "
 145                         "Disable the uncore unit.\n",
 146                         unit->box_type, unit->box_id);
 147                 return;
 148         }
 149
 150         if (parsed) {
 151                 type = search_uncore_discovery_type(unit->box_type);
 152                 if (!type) {
 153                         pr_info("A spurious uncore type %d is detected, "
 154                                 "Disable the uncore type.\n",
 155                                 unit->box_type);
 156                         return;
 157                 }
 158                 /* Store the first box of each die */
 159                 if (!type->box_ctrl_die[die])
 160                         type->box_ctrl_die[die] = unit->ctl;
 161                 return;
 162         }
 163
 164         type = get_uncore_discovery_type(unit);
 165         if (!type)
 166                 return;
 167
 168         box_offset = kcalloc(type->num_boxes + 1, sizeof(unsigned int), GFP_KERNEL);
 169         if (!box_offset)
 170                 return;
 171
 172         ids = kcalloc(type->num_boxes + 1, sizeof(unsigned int), GFP_KERNEL);
 173         if (!ids)
 174                 goto free_box_offset;
 175
 176         /* Store generic information for the first box */
 177         if (!type->num_boxes) {
 178                 type->box_ctrl = unit->ctl;
 179                 type->box_ctrl_die[die] = unit->ctl;
 180                 type->num_counters = unit->num_regs;
 181                 type->counter_width = unit->bit_width;
 182                 type->ctl_offset = unit->ctl_offset;
 183                 type->ctr_offset = unit->ctr_offset;
 184                 *ids = unit->box_id;
 185                 goto end;
 186         }
 187
 188         for (i = 0; i < type->num_boxes; i++) {
 189                 ids[i] = type->ids[i];
 190                 box_offset[i] = type->box_offset[i];
 191
 192                 if (unit->box_id == ids[i]) {
 193                         pr_info("Duplicate uncore type %d box ID %d is detected, "
 194                                 "Drop the duplicate uncore unit.\n",
 195                                 unit->box_type, unit->box_id);
 196                         goto free_ids;
 197                 }
 198         }
 199         ids[i] = unit->box_id;
 200         box_offset[i] = unit->ctl - type->box_ctrl;
 201         kfree(type->ids);
 202         kfree(type->box_offset);
 203 end:
 204         type->ids = ids;
 205         type->box_offset = box_offset;
 206         type->num_boxes++;
 207         return;
 208
 209 free_ids:
 210         kfree(ids);
 211
 212 free_box_offset:
 213         kfree(box_offset);
 214
 215 }
 216
 217 static int parse_discovery_table(struct pci_dev *dev, int die,
 218                                  u32 bar_offset, bool *parsed)
 219 {
 220         struct uncore_global_discovery global;
 221         struct uncore_unit_discovery unit;
 222         void __iomem *io_addr;
 223         resource_size_t addr;
 224         unsigned long size;
 225         u32 val;
 226         int i;
 227
 228         pci_read_config_dword(dev, bar_offset, &val);
 229
 230         if (val & ~PCI_BASE_ADDRESS_MEM_MASK & ~PCI_BASE_ADDRESS_MEM_TYPE_64)
 231                 return -EINVAL;
 232
 233         addr = (resource_size_t)(val & PCI_BASE_ADDRESS_MEM_MASK);
 234 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 235         if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) {
 236                 u32 val2;
 237
 238                 pci_read_config_dword(dev, bar_offset + 4, &val2);
 239                 addr |= ((resource_size_t)val2) << 32;
 240         }
 241 #endif
 242         size = UNCORE_DISCOVERY_GLOBAL_MAP_SIZE;
 243         io_addr = ioremap(addr, size);
 244         if (!io_addr)
 245                 return -ENOMEM;
 246
 247         /* Read Global Discovery State */
 248         memcpy_fromio(&global, io_addr, sizeof(struct uncore_global_discovery));
 249         if (uncore_discovery_invalid_unit(global)) {
 250                 pr_info("Invalid Global Discovery State: 0x%llx 0x%llx 0x%llx\n",
 251                         global.table1, global.ctl, global.table3);
 252                 iounmap(io_addr);
 253                 return -EINVAL;
 254         }
 255         iounmap(io_addr);
 256
 257         size = (1 + global.max_units) * global.stride * 8;
 258         io_addr = ioremap(addr, size);
 259         if (!io_addr)
 260                 return -ENOMEM;
 261
 262         /* Parsing Unit Discovery State */
 263         for (i = 0; i < global.max_units; i++) {
 264                 memcpy_fromio(&unit, io_addr + (i + 1) * (global.stride * 8),
 265                               sizeof(struct uncore_unit_discovery));
 266
 267                 if (uncore_discovery_invalid_unit(unit))
 268                         continue;
 269
 270                 if (unit.access_type >= UNCORE_ACCESS_MAX)
 271                         continue;
 272
 273                 uncore_insert_box_info(&unit, die, *parsed);
 274         }
 275
 276         *parsed = true;
 277         iounmap(io_addr);
 278         return 0;
 279 }
 280
 281 bool intel_uncore_has_discovery_tables(void)
 282 {
 283         u32 device, val, entry_id, bar_offset;
 284         int die, dvsec = 0, ret = true;
 285         struct pci_dev *dev = NULL;
 286         bool parsed = false;
 287
 288         if (has_generic_discovery_table())
 289                 device = UNCORE_DISCOVERY_TABLE_DEVICE;
 290         else
 291                 device = PCI_ANY_ID;
 292
 293         /*
 294          * Start a new search and iterates through the list of
 295          * the discovery table devices.
 296          */
 297         while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, dev)) != NULL) {
 298                 while ((dvsec = pci_find_next_ext_capability(dev, dvsec, UNCORE_EXT_CAP_ID_DISCOVERY))) {
 299                         pci_read_config_dword(dev, dvsec + UNCORE_DISCOVERY_DVSEC_OFFSET, &val);
 300                         entry_id = val & UNCORE_DISCOVERY_DVSEC_ID_MASK;
 301                         if (entry_id != UNCORE_DISCOVERY_DVSEC_ID_PMON)
 302                                 continue;
 303
 304                         pci_read_config_dword(dev, dvsec + UNCORE_DISCOVERY_DVSEC2_OFFSET, &val);
 305
 306                         if (val & ~UNCORE_DISCOVERY_DVSEC2_BIR_MASK) {
 307                                 ret = false;
 308                                 goto err;
 309                         }
 310                         bar_offset = UNCORE_DISCOVERY_BIR_BASE +
 311                                      (val & UNCORE_DISCOVERY_DVSEC2_BIR_MASK) * UNCORE_DISCOVERY_BIR_STEP;
 312
 313                         die = get_device_die_id(dev);
 314                         if (die < 0)
 315                                 continue;
 316
 317                         parse_discovery_table(dev, die, bar_offset, &parsed);
 318                 }
 319         }
 320
 321         /* None of the discovery tables are available */
 322         if (!parsed)
 323                 ret = false;
 324 err:
 325         pci_dev_put(dev);
 326
 327         return ret;
 328 }
 329
 330 void intel_uncore_clear_discovery_tables(void)
 331 {
 332         struct intel_uncore_discovery_type *type, *next;
 333
 334         rbtree_postorder_for_each_entry_safe(type, next, &discovery_tables, node) {
 335                 kfree(type->box_ctrl_die);
 336                 kfree(type);
 337         }
 338 }
 339
 340 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
 341 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
 342 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
 343 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
 344 DEFINE_UNCORE_FORMAT_ATTR(thresh, thresh, "config:24-31");
 345
 346 static struct attribute *generic_uncore_formats_attr[] = {
 347         &format_attr_event.attr,
 348         &format_attr_umask.attr,
 349         &format_attr_edge.attr,
 350         &format_attr_inv.attr,
 351         &format_attr_thresh.attr,
 352         NULL,
 353 };
 354
 355 static const struct attribute_group generic_uncore_format_group = {
 356         .name = "format",
 357         .attrs = generic_uncore_formats_attr,
 358 };
 359
 360 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box)
 361 {
 362         wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_INT);
 363 }
 364
 365 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box)
 366 {
 367         wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ);
 368 }
 369
 370 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box)
 371 {
 372         wrmsrl(uncore_msr_box_ctl(box), 0);
 373 }
 374
 375 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box *box,
 376                                             struct perf_event *event)
 377 {
 378         struct hw_perf_event *hwc = &event->hw;
 379
 380         wrmsrl(hwc->config_base, hwc->config);
 381 }
 382
 383 static void intel_generic_uncore_msr_disable_event(struct intel_uncore_box *box,
 384                                              struct perf_event *event)
 385 {
 386         struct hw_perf_event *hwc = &event->hw;
 387
 388         wrmsrl(hwc->config_base, 0);
 389 }
 390
 391 static struct intel_uncore_ops generic_uncore_msr_ops = {
 392         .init_box               = intel_generic_uncore_msr_init_box,
 393         .disable_box            = intel_generic_uncore_msr_disable_box,
 394         .enable_box             = intel_generic_uncore_msr_enable_box,
 395         .disable_event          = intel_generic_uncore_msr_disable_event,
 396         .enable_event           = intel_generic_uncore_msr_enable_event,
 397         .read_counter           = uncore_msr_read_counter,
 398 };
 399
 400 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
 401 {
 402         struct pci_dev *pdev = box->pci_dev;
 403         int box_ctl = uncore_pci_box_ctl(box);
 404
 405         __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
 406         pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
 407 }
 408
 409 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
 410 {
 411         struct pci_dev *pdev = box->pci_dev;
 412         int box_ctl = uncore_pci_box_ctl(box);
 413
 414         pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
 415 }
 416
 417 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
 418 {
 419         struct pci_dev *pdev = box->pci_dev;
 420         int box_ctl = uncore_pci_box_ctl(box);
 421
 422         pci_write_config_dword(pdev, box_ctl, 0);
 423 }
 424
 425 static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box,
 426                                             struct perf_event *event)
 427 {
 428         struct pci_dev *pdev = box->pci_dev;
 429         struct hw_perf_event *hwc = &event->hw;
 430
 431         pci_write_config_dword(pdev, hwc->config_base, hwc->config);
 432 }
 433
 434 void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
 435                                             struct perf_event *event)
 436 {
 437         struct pci_dev *pdev = box->pci_dev;
 438         struct hw_perf_event *hwc = &event->hw;
 439
 440         pci_write_config_dword(pdev, hwc->config_base, 0);
 441 }
 442
 443 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
 444                                           struct perf_event *event)
 445 {
 446         struct pci_dev *pdev = box->pci_dev;
 447         struct hw_perf_event *hwc = &event->hw;
 448         u64 count = 0;
 449
 450         pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
 451         pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
 452
 453         return count;
 454 }
 455
 456 static struct intel_uncore_ops generic_uncore_pci_ops = {
 457         .init_box       = intel_generic_uncore_pci_init_box,
 458         .disable_box    = intel_generic_uncore_pci_disable_box,
 459         .enable_box     = intel_generic_uncore_pci_enable_box,
 460         .disable_event  = intel_generic_uncore_pci_disable_event,
 461         .enable_event   = intel_generic_uncore_pci_enable_event,
 462         .read_counter   = intel_generic_uncore_pci_read_counter,
 463 };
 464
 465 #define UNCORE_GENERIC_MMIO_SIZE                0x4000
 466
 467 static u64 generic_uncore_mmio_box_ctl(struct intel_uncore_box *box)
 468 {
 469         struct intel_uncore_type *type = box->pmu->type;
 470
 471         if (!type->box_ctls || !type->box_ctls[box->dieid] || !type->mmio_offsets)
 472                 return 0;
 473
 474         return type->box_ctls[box->dieid] + type->mmio_offsets[box->pmu->pmu_idx];
 475 }
 476
 477 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box)
 478 {
 479         u64 box_ctl = generic_uncore_mmio_box_ctl(box);
 480         struct intel_uncore_type *type = box->pmu->type;
 481         resource_size_t addr;
 482
 483         if (!box_ctl) {
 484                 pr_warn("Uncore type %d box %d: Invalid box control address.\n",
 485                         type->type_id, type->box_ids[box->pmu->pmu_idx]);
 486                 return;
 487         }
 488
 489         addr = box_ctl;
 490         box->io_addr = ioremap(addr, UNCORE_GENERIC_MMIO_SIZE);
 491         if (!box->io_addr) {
 492                 pr_warn("Uncore type %d box %d: ioremap error for 0x%llx.\n",
 493                         type->type_id, type->box_ids[box->pmu->pmu_idx],
 494                         (unsigned long long)addr);
 495                 return;
 496         }
 497
 498         writel(GENERIC_PMON_BOX_CTL_INT, box->io_addr);
 499 }
 500
 501 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box)
 502 {
 503         if (!box->io_addr)
 504                 return;
 505
 506         writel(GENERIC_PMON_BOX_CTL_FRZ, box->io_addr);
 507 }
 508
 509 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box)
 510 {
 511         if (!box->io_addr)
 512                 return;
 513
 514         writel(0, box->io_addr);
 515 }
 516
 517 void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box,
 518                                             struct perf_event *event)
 519 {
 520         struct hw_perf_event *hwc = &event->hw;
 521
 522         if (!box->io_addr)
 523                 return;
 524
 525         writel(hwc->config, box->io_addr + hwc->config_base);
 526 }
 527
 528 void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
 529                                              struct perf_event *event)
 530 {
 531         struct hw_perf_event *hwc = &event->hw;
 532
 533         if (!box->io_addr)
 534                 return;
 535
 536         writel(0, box->io_addr + hwc->config_base);
 537 }
 538
 539 static struct intel_uncore_ops generic_uncore_mmio_ops = {
 540         .init_box       = intel_generic_uncore_mmio_init_box,
 541         .exit_box       = uncore_mmio_exit_box,
 542         .disable_box    = intel_generic_uncore_mmio_disable_box,
 543         .enable_box     = intel_generic_uncore_mmio_enable_box,
 544         .disable_event  = intel_generic_uncore_mmio_disable_event,
 545         .enable_event   = intel_generic_uncore_mmio_enable_event,
 546         .read_counter   = uncore_mmio_read_counter,
 547 };
 548
 549 static bool uncore_update_uncore_type(enum uncore_access_type type_id,
 550                                       struct intel_uncore_type *uncore,
 551                                       struct intel_uncore_discovery_type *type)
 552 {
 553         uncore->type_id = type->type;
 554         uncore->num_boxes = type->num_boxes;
 555         uncore->num_counters = type->num_counters;
 556         uncore->perf_ctr_bits = type->counter_width;
 557         uncore->box_ids = type->ids;
 558
 559         switch (type_id) {
 560         case UNCORE_ACCESS_MSR:
 561                 uncore->ops = &generic_uncore_msr_ops;
 562                 uncore->perf_ctr = (unsigned int)type->box_ctrl + type->ctr_offset;
 563                 uncore->event_ctl = (unsigned int)type->box_ctrl + type->ctl_offset;
 564                 uncore->box_ctl = (unsigned int)type->box_ctrl;
 565                 uncore->msr_offsets = type->box_offset;
 566                 break;
 567         case UNCORE_ACCESS_PCI:
 568                 uncore->ops = &generic_uncore_pci_ops;
 569                 uncore->perf_ctr = (unsigned int)UNCORE_DISCOVERY_PCI_BOX_CTRL(type->box_ctrl) + type->ctr_offset;
 570                 uncore->event_ctl = (unsigned int)UNCORE_DISCOVERY_PCI_BOX_CTRL(type->box_ctrl) + type->ctl_offset;
 571                 uncore->box_ctl = (unsigned int)UNCORE_DISCOVERY_PCI_BOX_CTRL(type->box_ctrl);
 572                 uncore->box_ctls = type->box_ctrl_die;
 573                 uncore->pci_offsets = type->box_offset;
 574                 break;
 575         case UNCORE_ACCESS_MMIO:
 576                 uncore->ops = &generic_uncore_mmio_ops;
 577                 uncore->perf_ctr = (unsigned int)type->ctr_offset;
 578                 uncore->event_ctl = (unsigned int)type->ctl_offset;
 579                 uncore->box_ctl = (unsigned int)type->box_ctrl;
 580                 uncore->box_ctls = type->box_ctrl_die;
 581                 uncore->mmio_offsets = type->box_offset;
 582                 uncore->mmio_map_size = UNCORE_GENERIC_MMIO_SIZE;
 583                 break;
 584         default:
 585                 return false;
 586         }
 587
 588         return true;
 589 }
 590
 591 struct intel_uncore_type **
 592 intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra)
 593 {
 594         struct intel_uncore_discovery_type *type;
 595         struct intel_uncore_type **uncores;
 596         struct intel_uncore_type *uncore;
 597         struct rb_node *node;
 598         int i = 0;
 599
 600         uncores = kcalloc(num_discovered_types[type_id] + num_extra + 1,
 601                           sizeof(struct intel_uncore_type *), GFP_KERNEL);
 602         if (!uncores)
 603                 return empty_uncore;
 604
 605         for (node = rb_first(&discovery_tables); node; node = rb_next(node)) {
 606                 type = rb_entry(node, struct intel_uncore_discovery_type, node);
 607                 if (type->access_type != type_id)
 608                         continue;
 609
 610                 uncore = kzalloc(sizeof(struct intel_uncore_type), GFP_KERNEL);
 611                 if (!uncore)
 612                         break;
 613
 614                 uncore->event_mask = GENERIC_PMON_RAW_EVENT_MASK;
 615                 uncore->format_group = &generic_uncore_format_group;
 616
 617                 if (!uncore_update_uncore_type(type_id, uncore, type)) {
 618                         kfree(uncore);
 619                         continue;
 620                 }
 621                 uncores[i++] = uncore;
 622         }
 623
 624         return uncores;
 625 }
 626
 627 void intel_uncore_generic_uncore_cpu_init(void)
 628 {
 629         uncore_msr_uncores = intel_uncore_generic_init_uncores(UNCORE_ACCESS_MSR, 0);
 630 }
 631
 632 int intel_uncore_generic_uncore_pci_init(void)
 633 {
 634         uncore_pci_uncores = intel_uncore_generic_init_uncores(UNCORE_ACCESS_PCI, 0);
 635
 636         return 0;
 637 }
 638
 639 void intel_uncore_generic_uncore_mmio_init(void)
 640 {
 641         uncore_mmio_uncores = intel_uncore_generic_init_uncores(UNCORE_ACCESS_MMIO, 0);
 642 }