1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel(R) Processor Trace PMU driver for perf
4 * Copyright (c) 2013-2014, Intel Corporation.
6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
7 * Programming Reference:
8 * http://software.intel.com/en-us/intel-isa-extensions
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/types.h>
16 #include <linux/bits.h>
17 #include <linux/limits.h>
18 #include <linux/slab.h>
19 #include <linux/device.h>
21 #include <asm/perf_event.h>
24 #include <asm/intel_pt.h>
25 #include <asm/intel-family.h>
27 #include "../perf_event.h"
30 static DEFINE_PER_CPU(struct pt, pt_ctx);
32 static struct pt_pmu pt_pmu;
35 * Capabilities of Intel PT hardware, such as number of address bits or
36 * supported output schemes, are cached and exported to userspace as "caps"
37 * attribute group of pt pmu device
38 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store
39 * relevant bits together with intel_pt traces.
41 * These are necessary for both trace decoding (payloads_lip, contains address
42 * width encoded in IP-related packets), and event configuration (bitmasks with
43 * permitted values for certain bit fields).
45 #define PT_CAP(_n, _l, _r, _m) \
46 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \
47 .reg = _r, .mask = _m }
49 static struct pt_cap_desc {
55 PT_CAP(max_subleaf, 0, CPUID_EAX, 0xffffffff),
56 PT_CAP(cr3_filtering, 0, CPUID_EBX, BIT(0)),
57 PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)),
58 PT_CAP(ip_filtering, 0, CPUID_EBX, BIT(2)),
59 PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
60 PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
61 PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
62 PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)),
63 PT_CAP(tnt_disable, 0, CPUID_EBX, BIT(8)),
64 PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
65 PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
66 PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
67 PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)),
68 PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)),
69 PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x7),
70 PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000),
71 PT_CAP(cycle_thresholds, 1, CPUID_EBX, 0xffff),
72 PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000),
75 u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability)
77 struct pt_cap_desc *cd = &pt_caps[capability];
78 u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
79 unsigned int shift = __ffs(cd->mask);
81 return (c & cd->mask) >> shift;
83 EXPORT_SYMBOL_GPL(intel_pt_validate_cap);
85 u32 intel_pt_validate_hw_cap(enum pt_capabilities cap)
87 return intel_pt_validate_cap(pt_pmu.caps, cap);
89 EXPORT_SYMBOL_GPL(intel_pt_validate_hw_cap);
91 static ssize_t pt_cap_show(struct device *cdev,
92 struct device_attribute *attr,
95 struct dev_ext_attribute *ea =
96 container_of(attr, struct dev_ext_attribute, attr);
97 enum pt_capabilities cap = (long)ea->var;
99 return snprintf(buf, PAGE_SIZE, "%x\n", intel_pt_validate_hw_cap(cap));
102 static struct attribute_group pt_cap_group __ro_after_init = {
106 PMU_FORMAT_ATTR(pt, "config:0" );
107 PMU_FORMAT_ATTR(cyc, "config:1" );
108 PMU_FORMAT_ATTR(pwr_evt, "config:4" );
109 PMU_FORMAT_ATTR(fup_on_ptw, "config:5" );
110 PMU_FORMAT_ATTR(mtc, "config:9" );
111 PMU_FORMAT_ATTR(tsc, "config:10" );
112 PMU_FORMAT_ATTR(noretcomp, "config:11" );
113 PMU_FORMAT_ATTR(ptw, "config:12" );
114 PMU_FORMAT_ATTR(branch, "config:13" );
115 PMU_FORMAT_ATTR(event, "config:31" );
116 PMU_FORMAT_ATTR(notnt, "config:55" );
117 PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
118 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
119 PMU_FORMAT_ATTR(psb_period, "config:24-27" );
121 static struct attribute *pt_formats_attr[] = {
122 &format_attr_pt.attr,
123 &format_attr_cyc.attr,
124 &format_attr_pwr_evt.attr,
125 &format_attr_event.attr,
126 &format_attr_notnt.attr,
127 &format_attr_fup_on_ptw.attr,
128 &format_attr_mtc.attr,
129 &format_attr_tsc.attr,
130 &format_attr_noretcomp.attr,
131 &format_attr_ptw.attr,
132 &format_attr_branch.attr,
133 &format_attr_mtc_period.attr,
134 &format_attr_cyc_thresh.attr,
135 &format_attr_psb_period.attr,
139 static struct attribute_group pt_format_group = {
141 .attrs = pt_formats_attr,
145 pt_timing_attr_show(struct device *dev, struct device_attribute *attr,
148 struct perf_pmu_events_attr *pmu_attr =
149 container_of(attr, struct perf_pmu_events_attr, attr);
151 switch (pmu_attr->id) {
153 return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio);
155 return sprintf(page, "%u:%u\n",
165 PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0,
166 pt_timing_attr_show);
167 PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1,
168 pt_timing_attr_show);
170 static struct attribute *pt_timing_attr[] = {
171 &timing_attr_max_nonturbo_ratio.attr.attr,
172 &timing_attr_tsc_art_ratio.attr.attr,
176 static struct attribute_group pt_timing_group = {
177 .attrs = pt_timing_attr,
180 static const struct attribute_group *pt_attr_groups[] = {
187 static int __init pt_pmu_hw_init(void)
189 struct dev_ext_attribute *de_attrs;
190 struct attribute **attrs;
196 rdmsrl(MSR_PLATFORM_INFO, reg);
197 pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8;
200 * if available, read in TSC to core crystal clock ratio,
201 * otherwise, zero for numerator stands for "not enumerated"
204 if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {
205 u32 eax, ebx, ecx, edx;
207 cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);
209 pt_pmu.tsc_art_num = ebx;
210 pt_pmu.tsc_art_den = eax;
213 /* model-specific quirks */
214 switch (boot_cpu_data.x86_model) {
215 case INTEL_FAM6_BROADWELL:
216 case INTEL_FAM6_BROADWELL_D:
217 case INTEL_FAM6_BROADWELL_G:
218 case INTEL_FAM6_BROADWELL_X:
219 /* not setting BRANCH_EN will #GP, erratum BDM106 */
220 pt_pmu.branch_en_always_on = true;
226 if (boot_cpu_has(X86_FEATURE_VMX)) {
228 * Intel SDM, 36.5 "Tracing post-VMXON" says that
229 * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
232 rdmsrl(MSR_IA32_VMX_MISC, reg);
237 for (i = 0; i < PT_CPUID_LEAVES; i++) {
239 &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
240 &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
241 &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],
242 &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]);
246 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1);
247 attrs = kzalloc(size, GFP_KERNEL);
251 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1);
252 de_attrs = kzalloc(size, GFP_KERNEL);
256 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) {
257 struct dev_ext_attribute *de_attr = de_attrs + i;
259 de_attr->attr.attr.name = pt_caps[i].name;
261 sysfs_attr_init(&de_attr->attr.attr);
263 de_attr->attr.attr.mode = S_IRUGO;
264 de_attr->attr.show = pt_cap_show;
265 de_attr->var = (void *)i;
267 attrs[i] = &de_attr->attr.attr;
270 pt_cap_group.attrs = attrs;
280 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \
281 RTIT_CTL_CYC_THRESH | \
284 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \
287 #define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \
291 * Bit 0 (TraceEn) in the attr.config is meaningless as the
292 * corresponding bit in the RTIT_CTL can only be controlled
293 * by the driver; therefore, repurpose it to mean: pass
294 * through the bit that was previously assumed to be always
295 * on for PT, thereby allowing the user to *not* set it if
296 * they so wish. See also pt_event_valid() and pt_config().
298 #define RTIT_CTL_PASSTHROUGH RTIT_CTL_TRACEEN
300 #define PT_CONFIG_MASK (RTIT_CTL_TRACEEN | \
303 RTIT_CTL_BRANCH_EN | \
306 RTIT_CTL_PWR_EVT_EN | \
307 RTIT_CTL_EVENT_EN | \
309 RTIT_CTL_FUP_ON_PTW | \
312 static bool pt_event_valid(struct perf_event *event)
314 u64 config = event->attr.config;
315 u64 allowed, requested;
317 if ((config & PT_CONFIG_MASK) != config)
320 if (config & RTIT_CTL_CYC_PSB) {
321 if (!intel_pt_validate_hw_cap(PT_CAP_psb_cyc))
324 allowed = intel_pt_validate_hw_cap(PT_CAP_psb_periods);
325 requested = (config & RTIT_CTL_PSB_FREQ) >>
326 RTIT_CTL_PSB_FREQ_OFFSET;
327 if (requested && (!(allowed & BIT(requested))))
330 allowed = intel_pt_validate_hw_cap(PT_CAP_cycle_thresholds);
331 requested = (config & RTIT_CTL_CYC_THRESH) >>
332 RTIT_CTL_CYC_THRESH_OFFSET;
333 if (requested && (!(allowed & BIT(requested))))
337 if (config & RTIT_CTL_MTC) {
339 * In the unlikely case that CPUID lists valid mtc periods,
340 * but not the mtc capability, drop out here.
342 * Spec says that setting mtc period bits while mtc bit in
343 * CPUID is 0 will #GP, so better safe than sorry.
345 if (!intel_pt_validate_hw_cap(PT_CAP_mtc))
348 allowed = intel_pt_validate_hw_cap(PT_CAP_mtc_periods);
352 requested = (config & RTIT_CTL_MTC_RANGE) >>
353 RTIT_CTL_MTC_RANGE_OFFSET;
355 if (!(allowed & BIT(requested)))
359 if (config & RTIT_CTL_PWR_EVT_EN &&
360 !intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
363 if (config & RTIT_CTL_EVENT_EN &&
364 !intel_pt_validate_hw_cap(PT_CAP_event_trace))
367 if (config & RTIT_CTL_NOTNT &&
368 !intel_pt_validate_hw_cap(PT_CAP_tnt_disable))
371 if (config & RTIT_CTL_PTW) {
372 if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
375 /* FUPonPTW without PTW doesn't make sense */
376 if ((config & RTIT_CTL_FUP_ON_PTW) &&
377 !(config & RTIT_CTL_PTW_EN))
382 * Setting bit 0 (TraceEn in RTIT_CTL MSR) in the attr.config
383 * clears the assumption that BranchEn must always be enabled,
384 * as was the case with the first implementation of PT.
385 * If this bit is not set, the legacy behavior is preserved
386 * for compatibility with the older userspace.
388 * Re-using bit 0 for this purpose is fine because it is never
389 * directly set by the user; previous attempts at setting it in
390 * the attr.config resulted in -EINVAL.
392 if (config & RTIT_CTL_PASSTHROUGH) {
394 * Disallow not setting BRANCH_EN where BRANCH_EN is
397 if (pt_pmu.branch_en_always_on &&
398 !(config & RTIT_CTL_BRANCH_EN))
402 * Disallow BRANCH_EN without the PASSTHROUGH.
404 if (config & RTIT_CTL_BRANCH_EN)
412 * PT configuration helpers
413 * These all are cpu affine and operate on a local PT
416 static void pt_config_start(struct perf_event *event)
418 struct pt *pt = this_cpu_ptr(&pt_ctx);
419 u64 ctl = event->hw.config;
421 ctl |= RTIT_CTL_TRACEEN;
422 if (READ_ONCE(pt->vmx_on))
423 perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
425 wrmsrl(MSR_IA32_RTIT_CTL, ctl);
427 WRITE_ONCE(event->hw.config, ctl);
430 /* Address ranges and their corresponding msr configuration registers */
431 static const struct pt_address_range {
434 unsigned int reg_off;
435 } pt_address_ranges[] = {
437 .msr_a = MSR_IA32_RTIT_ADDR0_A,
438 .msr_b = MSR_IA32_RTIT_ADDR0_B,
439 .reg_off = RTIT_CTL_ADDR0_OFFSET,
442 .msr_a = MSR_IA32_RTIT_ADDR1_A,
443 .msr_b = MSR_IA32_RTIT_ADDR1_B,
444 .reg_off = RTIT_CTL_ADDR1_OFFSET,
447 .msr_a = MSR_IA32_RTIT_ADDR2_A,
448 .msr_b = MSR_IA32_RTIT_ADDR2_B,
449 .reg_off = RTIT_CTL_ADDR2_OFFSET,
452 .msr_a = MSR_IA32_RTIT_ADDR3_A,
453 .msr_b = MSR_IA32_RTIT_ADDR3_B,
454 .reg_off = RTIT_CTL_ADDR3_OFFSET,
458 static u64 pt_config_filters(struct perf_event *event)
460 struct pt_filters *filters = event->hw.addr_filters;
461 struct pt *pt = this_cpu_ptr(&pt_ctx);
462 unsigned int range = 0;
468 perf_event_addr_filters_sync(event);
470 for (range = 0; range < filters->nr_filters; range++) {
471 struct pt_filter *filter = &filters->filter[range];
474 * Note, if the range has zero start/end addresses due
475 * to its dynamic object not being loaded yet, we just
476 * go ahead and program zeroed range, which will simply
477 * produce no data. Note^2: if executable code at 0x0
478 * is a concern, we can set up an "invalid" configuration
479 * such as msr_b < msr_a.
482 /* avoid redundant msr writes */
483 if (pt->filters.filter[range].msr_a != filter->msr_a) {
484 wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a);
485 pt->filters.filter[range].msr_a = filter->msr_a;
488 if (pt->filters.filter[range].msr_b != filter->msr_b) {
489 wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b);
490 pt->filters.filter[range].msr_b = filter->msr_b;
493 rtit_ctl |= (u64)filter->config << pt_address_ranges[range].reg_off;
499 static void pt_config(struct perf_event *event)
501 struct pt *pt = this_cpu_ptr(&pt_ctx);
502 struct pt_buffer *buf = perf_get_aux(&pt->handle);
505 /* First round: clear STATUS, in particular the PSB byte counter. */
506 if (!event->hw.config) {
507 perf_event_itrace_started(event);
508 wrmsrl(MSR_IA32_RTIT_STATUS, 0);
511 reg = pt_config_filters(event);
512 reg |= RTIT_CTL_TRACEEN;
514 reg |= RTIT_CTL_TOPA;
517 * Previously, we had BRANCH_EN on by default, but now that PT has
518 * grown features outside of branch tracing, it is useful to allow
519 * the user to disable it. Setting bit 0 in the event's attr.config
520 * allows BRANCH_EN to pass through instead of being always on. See
521 * also the comment in pt_event_valid().
523 if (event->attr.config & BIT(0)) {
524 reg |= event->attr.config & RTIT_CTL_BRANCH_EN;
526 reg |= RTIT_CTL_BRANCH_EN;
529 if (!event->attr.exclude_kernel)
531 if (!event->attr.exclude_user)
534 reg |= (event->attr.config & PT_CONFIG_MASK);
536 event->hw.config = reg;
537 pt_config_start(event);
540 static void pt_config_stop(struct perf_event *event)
542 struct pt *pt = this_cpu_ptr(&pt_ctx);
543 u64 ctl = READ_ONCE(event->hw.config);
545 /* may be already stopped by a PMI */
546 if (!(ctl & RTIT_CTL_TRACEEN))
549 ctl &= ~RTIT_CTL_TRACEEN;
550 if (!READ_ONCE(pt->vmx_on))
551 wrmsrl(MSR_IA32_RTIT_CTL, ctl);
553 WRITE_ONCE(event->hw.config, ctl);
556 * A wrmsr that disables trace generation serializes other PT
557 * registers and causes all data packets to be written to memory,
558 * but a fence is required for the data to become globally visible.
560 * The below WMB, separating data store and aux_head store matches
561 * the consumer's RMB that separates aux_head load and data load.
567 * struct topa - ToPA metadata
568 * @list: linkage to struct pt_buffer's list of tables
569 * @offset: offset of the first entry in this table in the buffer
570 * @size: total size of all entries in this table
571 * @last: index of the last initialized entry in this table
572 * @z_count: how many times the first entry repeats
575 struct list_head list;
579 unsigned int z_count;
583 * Keep ToPA table-related metadata on the same page as the actual table,
584 * taking up a few words from the top
587 #define TENTS_PER_PAGE \
588 ((PAGE_SIZE - sizeof(struct topa)) / sizeof(struct topa_entry))
591 * struct topa_page - page-sized ToPA table with metadata at the top
592 * @table: actual ToPA table entries, as understood by PT hardware
596 struct topa_entry table[TENTS_PER_PAGE];
600 static inline struct topa_page *topa_to_page(struct topa *topa)
602 return container_of(topa, struct topa_page, topa);
605 static inline struct topa_page *topa_entry_to_page(struct topa_entry *te)
607 return (struct topa_page *)((unsigned long)te & PAGE_MASK);
610 static inline phys_addr_t topa_pfn(struct topa *topa)
612 return PFN_DOWN(virt_to_phys(topa_to_page(topa)));
615 /* make -1 stand for the last table entry */
616 #define TOPA_ENTRY(t, i) \
618 ? &topa_to_page(t)->table[(t)->last] \
619 : &topa_to_page(t)->table[(i)])
620 #define TOPA_ENTRY_SIZE(t, i) (sizes(TOPA_ENTRY((t), (i))->size))
621 #define TOPA_ENTRY_PAGES(t, i) (1 << TOPA_ENTRY((t), (i))->size)
623 static void pt_config_buffer(struct pt_buffer *buf)
625 struct pt *pt = this_cpu_ptr(&pt_ctx);
630 base = buf->data_pages[0];
631 mask = (buf->nr_pages * PAGE_SIZE - 1) >> 7;
633 base = topa_to_page(buf->cur)->table;
634 mask = (u64)buf->cur_idx;
637 reg = virt_to_phys(base);
638 if (pt->output_base != reg) {
639 pt->output_base = reg;
640 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, reg);
643 reg = 0x7f | (mask << 7) | ((u64)buf->output_off << 32);
644 if (pt->output_mask != reg) {
645 pt->output_mask = reg;
646 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg);
651 * topa_alloc() - allocate page-sized ToPA table
652 * @cpu: CPU on which to allocate.
653 * @gfp: Allocation flags.
655 * Return: On success, return the pointer to ToPA table page.
657 static struct topa *topa_alloc(int cpu, gfp_t gfp)
659 int node = cpu_to_node(cpu);
660 struct topa_page *tp;
663 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0);
667 tp = page_address(p);
671 * In case of singe-entry ToPA, always put the self-referencing END
672 * link as the 2nd entry in the table
674 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
675 TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p) >> TOPA_SHIFT;
676 TOPA_ENTRY(&tp->topa, 1)->end = 1;
683 * topa_free() - free a page-sized ToPA table
684 * @topa: Table to deallocate.
686 static void topa_free(struct topa *topa)
688 free_page((unsigned long)topa);
692 * topa_insert_table() - insert a ToPA table into a buffer
693 * @buf: PT buffer that's being extended.
694 * @topa: New topa table to be inserted.
696 * If it's the first table in this buffer, set up buffer's pointers
697 * accordingly; otherwise, add a END=1 link entry to @topa to the current
698 * "last" table and adjust the last table pointer to @topa.
700 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa)
702 struct topa *last = buf->last;
704 list_add_tail(&topa->list, &buf->tables);
707 buf->first = buf->last = buf->cur = topa;
711 topa->offset = last->offset + last->size;
714 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
717 BUG_ON(last->last != TENTS_PER_PAGE - 1);
719 TOPA_ENTRY(last, -1)->base = topa_pfn(topa);
720 TOPA_ENTRY(last, -1)->end = 1;
724 * topa_table_full() - check if a ToPA table is filled up
727 static bool topa_table_full(struct topa *topa)
729 /* single-entry ToPA is a special case */
730 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
733 return topa->last == TENTS_PER_PAGE - 1;
737 * topa_insert_pages() - create a list of ToPA tables
738 * @buf: PT buffer being initialized.
739 * @gfp: Allocation flags.
741 * This initializes a list of ToPA tables with entries from
742 * the data_pages provided by rb_alloc_aux().
744 * Return: 0 on success or error code.
746 static int topa_insert_pages(struct pt_buffer *buf, int cpu, gfp_t gfp)
748 struct topa *topa = buf->last;
752 p = virt_to_page(buf->data_pages[buf->nr_pages]);
754 order = page_private(p);
756 if (topa_table_full(topa)) {
757 topa = topa_alloc(cpu, gfp);
761 topa_insert_table(buf, topa);
764 if (topa->z_count == topa->last - 1) {
765 if (order == TOPA_ENTRY(topa, topa->last - 1)->size)
769 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT;
770 TOPA_ENTRY(topa, -1)->size = order;
771 if (!buf->snapshot &&
772 !intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
773 TOPA_ENTRY(topa, -1)->intr = 1;
774 TOPA_ENTRY(topa, -1)->stop = 1;
778 topa->size += sizes(order);
780 buf->nr_pages += 1ul << order;
786 * pt_topa_dump() - print ToPA tables and their entries
789 static void pt_topa_dump(struct pt_buffer *buf)
793 list_for_each_entry(topa, &buf->tables, list) {
794 struct topa_page *tp = topa_to_page(topa);
797 pr_debug("# table @%p, off %llx size %zx\n", tp->table,
798 topa->offset, topa->size);
799 for (i = 0; i < TENTS_PER_PAGE; i++) {
800 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n",
802 (unsigned long)tp->table[i].base << TOPA_SHIFT,
803 sizes(tp->table[i].size),
804 tp->table[i].end ? 'E' : ' ',
805 tp->table[i].intr ? 'I' : ' ',
806 tp->table[i].stop ? 'S' : ' ',
807 *(u64 *)&tp->table[i]);
808 if ((intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
809 tp->table[i].stop) ||
812 if (!i && topa->z_count)
819 * pt_buffer_advance() - advance to the next output region
822 * Advance the current pointers in the buffer to the next ToPA entry.
824 static void pt_buffer_advance(struct pt_buffer *buf)
829 if (buf->cur_idx == buf->cur->last) {
830 if (buf->cur == buf->last)
831 buf->cur = buf->first;
833 buf->cur = list_entry(buf->cur->list.next, struct topa,
840 * pt_update_head() - calculate current offsets and sizes
841 * @pt: Per-cpu pt context.
843 * Update buffer's current write pointer position and data size.
845 static void pt_update_head(struct pt *pt)
847 struct pt_buffer *buf = perf_get_aux(&pt->handle);
848 u64 topa_idx, base, old;
851 local_set(&buf->data_size, buf->output_off);
855 /* offset of the first region in this table from the beginning of buf */
856 base = buf->cur->offset + buf->output_off;
858 /* offset of the current output region within this table */
859 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++)
860 base += TOPA_ENTRY_SIZE(buf->cur, topa_idx);
863 local_set(&buf->data_size, base);
865 old = (local64_xchg(&buf->head, base) &
866 ((buf->nr_pages << PAGE_SHIFT) - 1));
868 base += buf->nr_pages << PAGE_SHIFT;
870 local_add(base - old, &buf->data_size);
875 * pt_buffer_region() - obtain current output region's address
878 static void *pt_buffer_region(struct pt_buffer *buf)
880 return phys_to_virt(TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT);
884 * pt_buffer_region_size() - obtain current output region's size
887 static size_t pt_buffer_region_size(struct pt_buffer *buf)
889 return TOPA_ENTRY_SIZE(buf->cur, buf->cur_idx);
893 * pt_handle_status() - take care of possible status conditions
894 * @pt: Per-cpu pt context.
896 static void pt_handle_status(struct pt *pt)
898 struct pt_buffer *buf = perf_get_aux(&pt->handle);
902 rdmsrl(MSR_IA32_RTIT_STATUS, status);
904 if (status & RTIT_STATUS_ERROR) {
905 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
907 status &= ~RTIT_STATUS_ERROR;
910 if (status & RTIT_STATUS_STOPPED) {
911 status &= ~RTIT_STATUS_STOPPED;
914 * On systems that only do single-entry ToPA, hitting STOP
915 * means we are already losing data; need to let the decoder
919 (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) ||
920 buf->output_off == pt_buffer_region_size(buf))) {
921 perf_aux_output_flag(&pt->handle,
922 PERF_AUX_FLAG_TRUNCATED);
928 * Also on single-entry ToPA implementations, interrupt will come
929 * before the output reaches its output region's boundary.
931 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
933 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) {
934 void *head = pt_buffer_region(buf);
936 /* everything within this margin needs to be zeroed out */
937 memset(head + buf->output_off, 0,
938 pt_buffer_region_size(buf) -
944 pt_buffer_advance(buf);
946 wrmsrl(MSR_IA32_RTIT_STATUS, status);
950 * pt_read_offset() - translate registers into buffer pointers
953 * Set buffer's output pointers from MSR values.
955 static void pt_read_offset(struct pt_buffer *buf)
957 struct pt *pt = this_cpu_ptr(&pt_ctx);
958 struct topa_page *tp;
961 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base);
962 tp = phys_to_virt(pt->output_base);
963 buf->cur = &tp->topa;
966 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask);
967 /* offset within current output region */
968 buf->output_off = pt->output_mask >> 32;
969 /* index of current output region within this table */
971 buf->cur_idx = (pt->output_mask & 0xffffff80) >> 7;
974 static struct topa_entry *
975 pt_topa_entry_for_page(struct pt_buffer *buf, unsigned int pg)
977 struct topa_page *tp;
979 unsigned int idx, cur_pg = 0, z_pg = 0, start_idx = 0;
982 * Indicates a bug in the caller.
984 if (WARN_ON_ONCE(pg >= buf->nr_pages))
988 * First, find the ToPA table where @pg fits. With high
989 * order allocations, there shouldn't be many of these.
991 list_for_each_entry(topa, &buf->tables, list) {
992 if (topa->offset + topa->size > pg << PAGE_SHIFT)
997 * Hitting this means we have a problem in the ToPA
1006 * Indicates a problem in the ToPA allocation code.
1008 if (WARN_ON_ONCE(topa->last == -1))
1011 tp = topa_to_page(topa);
1012 cur_pg = PFN_DOWN(topa->offset);
1013 if (topa->z_count) {
1014 z_pg = TOPA_ENTRY_PAGES(topa, 0) * (topa->z_count + 1);
1015 start_idx = topa->z_count + 1;
1019 * Multiple entries at the beginning of the table have the same size,
1020 * ideally all of them; if @pg falls there, the search is done.
1022 if (pg >= cur_pg && pg < cur_pg + z_pg) {
1023 idx = (pg - cur_pg) / TOPA_ENTRY_PAGES(topa, 0);
1024 return &tp->table[idx];
1028 * Otherwise, slow path: iterate through the remaining entries.
1030 for (idx = start_idx, cur_pg += z_pg; idx < topa->last; idx++) {
1031 if (cur_pg + TOPA_ENTRY_PAGES(topa, idx) > pg)
1032 return &tp->table[idx];
1034 cur_pg += TOPA_ENTRY_PAGES(topa, idx);
1038 * Means we couldn't find a ToPA entry in the table that does match.
1045 static struct topa_entry *
1046 pt_topa_prev_entry(struct pt_buffer *buf, struct topa_entry *te)
1048 unsigned long table = (unsigned long)te & ~(PAGE_SIZE - 1);
1049 struct topa_page *tp;
1052 tp = (struct topa_page *)table;
1053 if (tp->table != te)
1057 if (topa == buf->first)
1060 topa = list_prev_entry(topa, list);
1062 tp = topa_to_page(topa);
1064 return &tp->table[topa->last - 1];
1068 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer
1070 * @handle: Current output handle.
1072 * Place INT and STOP marks to prevent overwriting old data that the consumer
1073 * hasn't yet collected and waking up the consumer after a certain fraction of
1074 * the buffer has filled up. Only needed and sensible for non-snapshot counters.
1076 * This obviously relies on buf::head to figure out buffer markers, so it has
1077 * to be called after pt_buffer_reset_offsets() and before the hardware tracing
1080 static int pt_buffer_reset_markers(struct pt_buffer *buf,
1081 struct perf_output_handle *handle)
1084 unsigned long head = local64_read(&buf->head);
1085 unsigned long idx, npages, wakeup;
1090 /* can't stop in the middle of an output region */
1091 if (buf->output_off + handle->size + 1 < pt_buffer_region_size(buf)) {
1092 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
1097 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */
1098 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
1101 /* clear STOP and INT from current entry */
1103 buf->stop_te->stop = 0;
1104 buf->stop_te->intr = 0;
1108 buf->intr_te->intr = 0;
1110 /* how many pages till the STOP marker */
1111 npages = handle->size >> PAGE_SHIFT;
1113 /* if it's on a page boundary, fill up one more page */
1114 if (!offset_in_page(head + handle->size + 1))
1117 idx = (head >> PAGE_SHIFT) + npages;
1118 idx &= buf->nr_pages - 1;
1120 if (idx != buf->stop_pos) {
1121 buf->stop_pos = idx;
1122 buf->stop_te = pt_topa_entry_for_page(buf, idx);
1123 buf->stop_te = pt_topa_prev_entry(buf, buf->stop_te);
1126 wakeup = handle->wakeup >> PAGE_SHIFT;
1128 /* in the worst case, wake up the consumer one page before hard stop */
1129 idx = (head >> PAGE_SHIFT) + npages - 1;
1133 idx &= buf->nr_pages - 1;
1134 if (idx != buf->intr_pos) {
1135 buf->intr_pos = idx;
1136 buf->intr_te = pt_topa_entry_for_page(buf, idx);
1137 buf->intr_te = pt_topa_prev_entry(buf, buf->intr_te);
1140 buf->stop_te->stop = 1;
1141 buf->stop_te->intr = 1;
1142 buf->intr_te->intr = 1;
1148 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head
1150 * @head: Write pointer (aux_head) from AUX buffer.
1152 * Find the ToPA table and entry corresponding to given @head and set buffer's
1153 * "current" pointers accordingly. This is done after we have obtained the
1154 * current aux_head position from a successful call to perf_aux_output_begin()
1155 * to make sure the hardware is writing to the right place.
1157 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed
1158 * into PT msrs when the tracing is enabled and buf::head and buf::data_size,
1159 * which are used to determine INT and STOP markers' locations by a subsequent
1160 * call to pt_buffer_reset_markers().
1162 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head)
1164 struct topa_page *cur_tp;
1165 struct topa_entry *te;
1169 head &= (buf->nr_pages << PAGE_SHIFT) - 1;
1172 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1);
1173 te = pt_topa_entry_for_page(buf, pg);
1175 cur_tp = topa_entry_to_page(te);
1176 buf->cur = &cur_tp->topa;
1177 buf->cur_idx = te - TOPA_ENTRY(buf->cur, 0);
1178 buf->output_off = head & (pt_buffer_region_size(buf) - 1);
1180 buf->output_off = head;
1183 local64_set(&buf->head, head);
1184 local_set(&buf->data_size, 0);
1188 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer
1191 static void pt_buffer_fini_topa(struct pt_buffer *buf)
1193 struct topa *topa, *iter;
1198 list_for_each_entry_safe(topa, iter, &buf->tables, list) {
1200 * right now, this is in free_aux() path only, so
1201 * no need to unlink this table from the list
1208 * pt_buffer_init_topa() - initialize ToPA table for pt buffer
1210 * @size: Total size of all regions within this ToPA.
1211 * @gfp: Allocation flags.
1213 static int pt_buffer_init_topa(struct pt_buffer *buf, int cpu,
1214 unsigned long nr_pages, gfp_t gfp)
1219 topa = topa_alloc(cpu, gfp);
1223 topa_insert_table(buf, topa);
1225 while (buf->nr_pages < nr_pages) {
1226 err = topa_insert_pages(buf, cpu, gfp);
1228 pt_buffer_fini_topa(buf);
1233 /* link last table to the first one, unless we're double buffering */
1234 if (intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
1235 TOPA_ENTRY(buf->last, -1)->base = topa_pfn(buf->first);
1236 TOPA_ENTRY(buf->last, -1)->end = 1;
1243 static int pt_buffer_try_single(struct pt_buffer *buf, int nr_pages)
1245 struct page *p = virt_to_page(buf->data_pages[0]);
1246 int ret = -ENOTSUPP, order = 0;
1249 * We can use single range output mode
1250 * + in snapshot mode, where we don't need interrupts;
1251 * + if the hardware supports it;
1252 * + if the entire buffer is one contiguous allocation.
1257 if (!intel_pt_validate_hw_cap(PT_CAP_single_range_output))
1261 order = page_private(p);
1263 if (1 << order != nr_pages)
1267 * Some processors cannot always support single range for more than
1268 * 4KB - refer errata TGL052, ADL037 and RPL017. Future processors might
1269 * also be affected, so for now rather than trying to keep track of
1270 * which ones, just disable it for all.
1276 buf->nr_pages = nr_pages;
1283 * pt_buffer_setup_aux() - set up topa tables for a PT buffer
1284 * @cpu: Cpu on which to allocate, -1 means current.
1285 * @pages: Array of pointers to buffer pages passed from perf core.
1286 * @nr_pages: Number of pages in the buffer.
1287 * @snapshot: If this is a snapshot/overwrite counter.
1289 * This is a pmu::setup_aux callback that sets up ToPA tables and all the
1290 * bookkeeping for an AUX buffer.
1292 * Return: Our private PT buffer structure.
1295 pt_buffer_setup_aux(struct perf_event *event, void **pages,
1296 int nr_pages, bool snapshot)
1298 struct pt_buffer *buf;
1299 int node, ret, cpu = event->cpu;
1305 * Only support AUX sampling in snapshot mode, where we don't
1308 if (event->attr.aux_sample_size && !snapshot)
1312 cpu = raw_smp_processor_id();
1313 node = cpu_to_node(cpu);
1315 buf = kzalloc_node(sizeof(struct pt_buffer), GFP_KERNEL, node);
1319 buf->snapshot = snapshot;
1320 buf->data_pages = pages;
1324 INIT_LIST_HEAD(&buf->tables);
1326 ret = pt_buffer_try_single(buf, nr_pages);
1330 ret = pt_buffer_init_topa(buf, cpu, nr_pages, GFP_KERNEL);
1340 * pt_buffer_free_aux() - perf AUX deallocation path callback
1343 static void pt_buffer_free_aux(void *data)
1345 struct pt_buffer *buf = data;
1347 pt_buffer_fini_topa(buf);
1351 static int pt_addr_filters_init(struct perf_event *event)
1353 struct pt_filters *filters;
1354 int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu);
1356 if (!intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
1359 filters = kzalloc_node(sizeof(struct pt_filters), GFP_KERNEL, node);
1364 memcpy(filters, event->parent->hw.addr_filters,
1367 event->hw.addr_filters = filters;
1372 static void pt_addr_filters_fini(struct perf_event *event)
1374 kfree(event->hw.addr_filters);
1375 event->hw.addr_filters = NULL;
1378 #ifdef CONFIG_X86_64
1379 /* Clamp to a canonical address greater-than-or-equal-to the address given */
1380 static u64 clamp_to_ge_canonical_addr(u64 vaddr, u8 vaddr_bits)
1382 return __is_canonical_address(vaddr, vaddr_bits) ?
1384 -BIT_ULL(vaddr_bits - 1);
1387 /* Clamp to a canonical address less-than-or-equal-to the address given */
1388 static u64 clamp_to_le_canonical_addr(u64 vaddr, u8 vaddr_bits)
1390 return __is_canonical_address(vaddr, vaddr_bits) ?
1392 BIT_ULL(vaddr_bits - 1) - 1;
1395 #define clamp_to_ge_canonical_addr(x, y) (x)
1396 #define clamp_to_le_canonical_addr(x, y) (x)
1399 static int pt_event_addr_filters_validate(struct list_head *filters)
1401 struct perf_addr_filter *filter;
1404 list_for_each_entry(filter, filters, entry) {
1406 * PT doesn't support single address triggers and
1409 if (!filter->size ||
1410 filter->action == PERF_ADDR_FILTER_ACTION_START)
1413 if (++range > intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
1420 static void pt_event_addr_filters_sync(struct perf_event *event)
1422 struct perf_addr_filters_head *head = perf_event_addr_filters(event);
1423 unsigned long msr_a, msr_b;
1424 struct perf_addr_filter_range *fr = event->addr_filter_ranges;
1425 struct pt_filters *filters = event->hw.addr_filters;
1426 struct perf_addr_filter *filter;
1432 list_for_each_entry(filter, &head->list, entry) {
1433 if (filter->path.dentry && !fr[range].start) {
1436 unsigned long n = fr[range].size - 1;
1437 unsigned long a = fr[range].start;
1440 if (a > ULONG_MAX - n)
1445 * Apply the offset. 64-bit addresses written to the
1446 * MSRs must be canonical, but the range can encompass
1447 * non-canonical addresses. Since software cannot
1448 * execute at non-canonical addresses, adjusting to
1449 * canonical addresses does not affect the result of the
1452 msr_a = clamp_to_ge_canonical_addr(a, boot_cpu_data.x86_virt_bits);
1453 msr_b = clamp_to_le_canonical_addr(b, boot_cpu_data.x86_virt_bits);
1458 filters->filter[range].msr_a = msr_a;
1459 filters->filter[range].msr_b = msr_b;
1460 if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER)
1461 filters->filter[range].config = 1;
1463 filters->filter[range].config = 2;
1467 filters->nr_filters = range;
1471 * intel_pt_interrupt() - PT PMI handler
1473 void intel_pt_interrupt(void)
1475 struct pt *pt = this_cpu_ptr(&pt_ctx);
1476 struct pt_buffer *buf;
1477 struct perf_event *event = pt->handle.event;
1480 * There may be a dangling PT bit in the interrupt status register
1481 * after PT has been disabled by pt_event_stop(). Make sure we don't
1482 * do anything (particularly, re-enable) for this event here.
1484 if (!READ_ONCE(pt->handle_nmi))
1490 pt_config_stop(event);
1492 buf = perf_get_aux(&pt->handle);
1496 pt_read_offset(buf);
1498 pt_handle_status(pt);
1502 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
1504 if (!event->hw.state) {
1507 buf = perf_aux_output_begin(&pt->handle, event);
1509 event->hw.state = PERF_HES_STOPPED;
1513 pt_buffer_reset_offsets(buf, pt->handle.head);
1514 /* snapshot counters don't use PMI, so it's safe */
1515 ret = pt_buffer_reset_markers(buf, &pt->handle);
1517 perf_aux_output_end(&pt->handle, 0);
1521 pt_config_buffer(buf);
1522 pt_config_start(event);
1526 void intel_pt_handle_vmx(int on)
1528 struct pt *pt = this_cpu_ptr(&pt_ctx);
1529 struct perf_event *event;
1530 unsigned long flags;
1532 /* PT plays nice with VMX, do nothing */
1537 * VMXON will clear RTIT_CTL.TraceEn; we need to make
1538 * sure to not try to set it while VMX is on. Disable
1539 * interrupts to avoid racing with pmu callbacks;
1540 * concurrent PMI should be handled fine.
1542 local_irq_save(flags);
1543 WRITE_ONCE(pt->vmx_on, on);
1546 * If an AUX transaction is in progress, it will contain
1547 * gap(s), so flag it PARTIAL to inform the user.
1549 event = pt->handle.event;
1551 perf_aux_output_flag(&pt->handle,
1552 PERF_AUX_FLAG_PARTIAL);
1554 /* Turn PTs back on */
1556 wrmsrl(MSR_IA32_RTIT_CTL, event->hw.config);
1558 local_irq_restore(flags);
1560 EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
1566 static void pt_event_start(struct perf_event *event, int mode)
1568 struct hw_perf_event *hwc = &event->hw;
1569 struct pt *pt = this_cpu_ptr(&pt_ctx);
1570 struct pt_buffer *buf;
1572 buf = perf_aux_output_begin(&pt->handle, event);
1576 pt_buffer_reset_offsets(buf, pt->handle.head);
1577 if (!buf->snapshot) {
1578 if (pt_buffer_reset_markers(buf, &pt->handle))
1582 WRITE_ONCE(pt->handle_nmi, 1);
1585 pt_config_buffer(buf);
1591 perf_aux_output_end(&pt->handle, 0);
1593 hwc->state = PERF_HES_STOPPED;
1596 static void pt_event_stop(struct perf_event *event, int mode)
1598 struct pt *pt = this_cpu_ptr(&pt_ctx);
1601 * Protect against the PMI racing with disabling wrmsr,
1602 * see comment in intel_pt_interrupt().
1604 WRITE_ONCE(pt->handle_nmi, 0);
1606 pt_config_stop(event);
1608 if (event->hw.state == PERF_HES_STOPPED)
1611 event->hw.state = PERF_HES_STOPPED;
1613 if (mode & PERF_EF_UPDATE) {
1614 struct pt_buffer *buf = perf_get_aux(&pt->handle);
1619 if (WARN_ON_ONCE(pt->handle.event != event))
1622 pt_read_offset(buf);
1624 pt_handle_status(pt);
1630 local_xchg(&buf->data_size,
1631 buf->nr_pages << PAGE_SHIFT);
1632 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
1636 static long pt_event_snapshot_aux(struct perf_event *event,
1637 struct perf_output_handle *handle,
1640 struct pt *pt = this_cpu_ptr(&pt_ctx);
1641 struct pt_buffer *buf = perf_get_aux(&pt->handle);
1642 unsigned long from = 0, to;
1645 if (WARN_ON_ONCE(!buf))
1649 * Sampling is only allowed on snapshot events;
1650 * see pt_buffer_setup_aux().
1652 if (WARN_ON_ONCE(!buf->snapshot))
1656 * Here, handle_nmi tells us if the tracing is on
1658 if (READ_ONCE(pt->handle_nmi))
1659 pt_config_stop(event);
1661 pt_read_offset(buf);
1664 to = local_read(&buf->data_size);
1666 from = buf->nr_pages << PAGE_SHIFT;
1669 ret = perf_output_copy_aux(&pt->handle, handle, from, to);
1672 * If the tracing was on when we turned up, restart it.
1673 * Compiler barrier not needed as we couldn't have been
1674 * preempted by anything that touches pt->handle_nmi.
1677 pt_config_start(event);
1682 static void pt_event_del(struct perf_event *event, int mode)
1684 pt_event_stop(event, PERF_EF_UPDATE);
1687 static int pt_event_add(struct perf_event *event, int mode)
1689 struct pt *pt = this_cpu_ptr(&pt_ctx);
1690 struct hw_perf_event *hwc = &event->hw;
1693 if (pt->handle.event)
1696 if (mode & PERF_EF_START) {
1697 pt_event_start(event, 0);
1699 if (hwc->state == PERF_HES_STOPPED)
1702 hwc->state = PERF_HES_STOPPED;
1711 static void pt_event_read(struct perf_event *event)
1715 static void pt_event_destroy(struct perf_event *event)
1717 pt_addr_filters_fini(event);
1718 x86_del_exclusive(x86_lbr_exclusive_pt);
1721 static int pt_event_init(struct perf_event *event)
1723 if (event->attr.type != pt_pmu.pmu.type)
1726 if (!pt_event_valid(event))
1729 if (x86_add_exclusive(x86_lbr_exclusive_pt))
1732 if (pt_addr_filters_init(event)) {
1733 x86_del_exclusive(x86_lbr_exclusive_pt);
1737 event->destroy = pt_event_destroy;
1742 void cpu_emergency_stop_pt(void)
1744 struct pt *pt = this_cpu_ptr(&pt_ctx);
1746 if (pt->handle.event)
1747 pt_event_stop(pt->handle.event, PERF_EF_UPDATE);
1750 int is_intel_pt_event(struct perf_event *event)
1752 return event->pmu == &pt_pmu.pmu;
1755 static __init int pt_init(void)
1757 int ret, cpu, prior_warn = 0;
1759 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE);
1761 if (!boot_cpu_has(X86_FEATURE_INTEL_PT))
1765 for_each_online_cpu(cpu) {
1768 ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl);
1769 if (!ret && (ctl & RTIT_CTL_TRACEEN))
1775 x86_add_exclusive(x86_lbr_exclusive_pt);
1776 pr_warn("PT is enabled at boot time, doing nothing\n");
1781 ret = pt_pmu_hw_init();
1785 if (!intel_pt_validate_hw_cap(PT_CAP_topa_output)) {
1786 pr_warn("ToPA output is not supported on this CPU\n");
1790 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
1791 pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG;
1793 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;
1794 pt_pmu.pmu.attr_groups = pt_attr_groups;
1795 pt_pmu.pmu.task_ctx_nr = perf_sw_context;
1796 pt_pmu.pmu.event_init = pt_event_init;
1797 pt_pmu.pmu.add = pt_event_add;
1798 pt_pmu.pmu.del = pt_event_del;
1799 pt_pmu.pmu.start = pt_event_start;
1800 pt_pmu.pmu.stop = pt_event_stop;
1801 pt_pmu.pmu.snapshot_aux = pt_event_snapshot_aux;
1802 pt_pmu.pmu.read = pt_event_read;
1803 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux;
1804 pt_pmu.pmu.free_aux = pt_buffer_free_aux;
1805 pt_pmu.pmu.addr_filters_sync = pt_event_addr_filters_sync;
1806 pt_pmu.pmu.addr_filters_validate = pt_event_addr_filters_validate;
1807 pt_pmu.pmu.nr_addr_filters =
1808 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges);
1810 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1);
1814 arch_initcall(pt_init);