2 * Atheros AR9170 driver
4 * Hardware-specific definitions
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
22 * This file incorporates work covered by the following copyright and
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
39 #ifndef __CARL9170_SHARED_WLAN_H
40 #define __CARL9170_SHARED_WLAN_H
44 #define AR9170_RX_PHY_RATE_CCK_1M 0x0a
45 #define AR9170_RX_PHY_RATE_CCK_2M 0x14
46 #define AR9170_RX_PHY_RATE_CCK_5M 0x37
47 #define AR9170_RX_PHY_RATE_CCK_11M 0x6e
49 #define AR9170_ENC_ALG_NONE 0x0
50 #define AR9170_ENC_ALG_WEP64 0x1
51 #define AR9170_ENC_ALG_TKIP 0x2
52 #define AR9170_ENC_ALG_AESCCMP 0x4
53 #define AR9170_ENC_ALG_WEP128 0x5
54 #define AR9170_ENC_ALG_WEP256 0x6
55 #define AR9170_ENC_ALG_CENC 0x7
57 #define AR9170_RX_ENC_SOFTWARE 0x8
59 #define AR9170_RX_STATUS_MODULATION 0x03
60 #define AR9170_RX_STATUS_MODULATION_S 0
61 #define AR9170_RX_STATUS_MODULATION_CCK 0x00
62 #define AR9170_RX_STATUS_MODULATION_OFDM 0x01
63 #define AR9170_RX_STATUS_MODULATION_HT 0x02
64 #define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
66 /* depends on modulation */
67 #define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
68 #define AR9170_RX_STATUS_GREENFIELD 0x08
70 #define AR9170_RX_STATUS_MPDU 0x30
71 #define AR9170_RX_STATUS_MPDU_S 4
72 #define AR9170_RX_STATUS_MPDU_SINGLE 0x00
73 #define AR9170_RX_STATUS_MPDU_FIRST 0x20
74 #define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
75 #define AR9170_RX_STATUS_MPDU_LAST 0x10
77 #define AR9170_RX_ERROR_RXTO 0x01
78 #define AR9170_RX_ERROR_OVERRUN 0x02
79 #define AR9170_RX_ERROR_DECRYPT 0x04
80 #define AR9170_RX_ERROR_FCS 0x08
81 #define AR9170_RX_ERROR_WRONG_RA 0x10
82 #define AR9170_RX_ERROR_PLCP 0x20
83 #define AR9170_RX_ERROR_MMIC 0x40
84 #define AR9170_RX_ERROR_FATAL 0x80
86 /* these are either-or */
87 #define AR9170_TX_MAC_PROT_RTS 0x0001
88 #define AR9170_TX_MAC_PROT_CTS 0x0002
89 #define AR9170_TX_MAC_PROT 0x0003
91 #define AR9170_TX_MAC_NO_ACK 0x0004
92 /* if unset, MAC will only do SIFS space before frame */
93 #define AR9170_TX_MAC_BACKOFF 0x0008
94 #define AR9170_TX_MAC_BURST 0x0010
95 #define AR9170_TX_MAC_AGGR 0x0020
97 /* encryption is a two-bit field */
98 #define AR9170_TX_MAC_ENCR_NONE 0x0000
99 #define AR9170_TX_MAC_ENCR_RC4 0x0040
100 #define AR9170_TX_MAC_ENCR_CENC 0x0080
101 #define AR9170_TX_MAC_ENCR_AES 0x00c0
103 #define AR9170_TX_MAC_MMIC 0x0100
104 #define AR9170_TX_MAC_HW_DURATION 0x0200
105 #define AR9170_TX_MAC_QOS_S 10
106 #define AR9170_TX_MAC_QOS 0x0c00
107 #define AR9170_TX_MAC_DISABLE_TXOP 0x1000
108 #define AR9170_TX_MAC_TXOP_RIFS 0x2000
109 #define AR9170_TX_MAC_IMM_BA 0x4000
112 #define AR9170_TX_PHY_MOD_CCK 0x00000000
113 #define AR9170_TX_PHY_MOD_OFDM 0x00000001
114 #define AR9170_TX_PHY_MOD_HT 0x00000002
116 /* depends on modulation */
117 #define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
118 #define AR9170_TX_PHY_GREENFIELD 0x00000004
120 #define AR9170_TX_PHY_BW_S 3
121 #define AR9170_TX_PHY_BW (3 << AR9170_TX_PHY_BW_SHIFT)
122 #define AR9170_TX_PHY_BW_20MHZ 0
123 #define AR9170_TX_PHY_BW_40MHZ 2
124 #define AR9170_TX_PHY_BW_40MHZ_DUP 3
126 #define AR9170_TX_PHY_TX_HEAVY_CLIP_S 6
127 #define AR9170_TX_PHY_TX_HEAVY_CLIP (7 << \
128 AR9170_TX_PHY_TX_HEAVY_CLIP_S)
130 #define AR9170_TX_PHY_TX_PWR_S 9
131 #define AR9170_TX_PHY_TX_PWR (0x3f << \
132 AR9170_TX_PHY_TX_PWR_S)
134 #define AR9170_TX_PHY_TXCHAIN_S 15
135 #define AR9170_TX_PHY_TXCHAIN (7 << \
136 AR9170_TX_PHY_TXCHAIN_S)
137 #define AR9170_TX_PHY_TXCHAIN_1 1
138 /* use for cck, ofdm 6/9/12/18/24 and HT if capable */
139 #define AR9170_TX_PHY_TXCHAIN_2 5
141 #define AR9170_TX_PHY_MCS_S 18
142 #define AR9170_TX_PHY_MCS (0x7f << \
145 #define AR9170_TX_PHY_RATE_CCK_1M 0x0
146 #define AR9170_TX_PHY_RATE_CCK_2M 0x1
147 #define AR9170_TX_PHY_RATE_CCK_5M 0x2
148 #define AR9170_TX_PHY_RATE_CCK_11M 0x3
150 /* same as AR9170_RX_PHY_RATE */
151 #define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb
152 #define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf
153 #define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa
154 #define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe
155 #define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9
156 #define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd
157 #define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8
158 #define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc
160 #define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0
161 #define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1
162 #define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2
163 #define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3
164 #define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4
165 #define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5
166 #define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6
167 #define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7
168 #define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8
169 #define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9
170 #define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa
171 #define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb
172 #define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc
173 #define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd
174 #define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe
175 #define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf
177 #define AR9170_TX_PHY_SHORT_GI 0x80000000
179 #ifdef __CARL9170FW__
180 struct ar9170_tx_hw_mac_control {
184 * Beware of compiler bugs in all gcc pre 4.4!
211 struct ar9170_tx_hw_phy_control {
215 * Beware of compiler bugs in all gcc pre 4.4!
234 struct ar9170_tx_rate_info {
237 u8 free:3; /* free for use (e.g.:RIFS/TXOP/AMPDU) */
240 struct carl9170_tx_superdesc {
247 u8 ampdu_commit_density:1;
248 u8 ampdu_commit_factor:1;
249 u8 ampdu_unused_bit:1;
255 struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES];
256 struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES];
259 struct ar9170_tx_hwdesc {
261 struct ar9170_tx_hw_mac_control mac;
262 struct ar9170_tx_hw_phy_control phy;
265 struct ar9170_tx_frame {
266 struct ar9170_tx_hwdesc hdr;
269 struct ieee80211_hdr i3e;
274 struct carl9170_tx_superframe {
275 struct carl9170_tx_superdesc s;
276 struct ar9170_tx_frame f;
279 #endif /* __CARL9170FW__ */
281 struct _ar9170_tx_hwdesc {
287 #define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0
288 #define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7
289 #define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18
290 #define CARL9170_TX_SUPER_AMPDU_FACTOR_S 3
291 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20
292 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S 5
293 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40
294 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6
296 #define CARL9170_TX_SUPER_MISC_QUEUE 0x7
297 #define CARL9170_TX_SUPER_MISC_QUEUE_S 0
298 #define CARL9170_TX_SUPER_MISC_VIF_ID 0x38
299 #define CARL9170_TX_SUPER_MISC_VIF_ID_S 3
300 #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40
301 #define CARL9170_TX_SUPER_MISC_CAB 0x80
303 #define CARL9170_TX_SUPER_RI_TRIES 0x7
304 #define CARL9170_TX_SUPER_RI_TRIES_S 0
305 #define CARL9170_TX_SUPER_RI_ERP_PROT 0x18
306 #define CARL9170_TX_SUPER_RI_ERP_PROT_S 3
308 struct _carl9170_tx_superdesc {
316 u8 ri[CARL9170_TX_MAX_RATES];
317 __le32 rr[CARL9170_TX_MAX_RETRY_RATES];
320 struct _carl9170_tx_superframe {
321 struct _carl9170_tx_superdesc s;
322 struct _ar9170_tx_hwdesc f;
326 #define CARL9170_TX_SUPERDESC_LEN 24
327 #define AR9170_TX_HWDESC_LEN 8
328 #define AR9170_TX_SUPERFRAME_LEN (CARL9170_TX_HWDESC_LEN + \
329 AR9170_TX_SUPERDESC_LEN)
331 struct ar9170_rx_head {
335 struct ar9170_rx_phystatus {
338 u8 rssi_ant0, rssi_ant1, rssi_ant2,
339 rssi_ant0x, rssi_ant1x, rssi_ant2x,
345 u8 evm_stream0[6], evm_stream1[6];
349 struct ar9170_rx_macstatus {
355 struct ar9170_rx_frame_single {
356 struct ar9170_rx_head phy_head;
357 struct ieee80211_hdr i3e;
358 struct ar9170_rx_phystatus phy_tail;
359 struct ar9170_rx_macstatus macstatus;
362 struct ar9170_rx_frame_head {
363 struct ar9170_rx_head phy_head;
364 struct ieee80211_hdr i3e;
365 struct ar9170_rx_macstatus macstatus;
368 struct ar9170_rx_frame_middle {
369 struct ieee80211_hdr i3e;
370 struct ar9170_rx_macstatus macstatus;
373 struct ar9170_rx_frame_tail {
374 struct ieee80211_hdr i3e;
375 struct ar9170_rx_phystatus phy_tail;
376 struct ar9170_rx_macstatus macstatus;
379 struct ar9170_rx_frame {
381 struct ar9170_rx_frame_single single;
382 struct ar9170_rx_frame_head head;
383 struct ar9170_rx_frame_middle middle;
384 struct ar9170_rx_frame_tail tail;
388 static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
390 return (t->SAidx & 0xc0) >> 4 |
391 (t->DAidx & 0xc0) >> 6;
406 static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 };
408 #define AR9170_TXQ_DEPTH 32
410 #endif /* __CARL9170_SHARED_WLAN_H */