1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Freescale QUICC Engine HDLC Device Driver
4 * Copyright 2014 Freescale Semiconductor Inc.
10 #include <linux/kernel.h>
11 #include <linux/list.h>
13 #include <soc/fsl/qe/immap_qe.h>
14 #include <soc/fsl/qe/qe.h>
16 #include <soc/fsl/qe/ucc.h>
17 #include <soc/fsl/qe/ucc_fast.h>
19 /* UCC HDLC event register */
20 #define UCCE_HDLC_RX_EVENTS \
21 (UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)
22 #define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)
24 struct ucc_hdlc_param {
65 struct ucc_hdlc_private {
67 struct ucc_tdm_info *ut_info;
68 struct ucc_fast_private *uccf;
70 struct net_device *ndev;
71 struct napi_struct napi;
72 struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
73 struct ucc_hdlc_param __iomem *ucc_pram;
81 dma_addr_t dma_tx_addr;
82 dma_addr_t dma_rx_addr;
84 struct qe_bd *tx_bd_base;
85 struct qe_bd *rx_bd_base;
88 struct qe_bd *curtx_bd;
89 struct qe_bd *currx_bd;
90 struct qe_bd *dirty_tx;
93 struct sk_buff **tx_skbuff;
94 struct sk_buff **rx_skbuff;
97 unsigned short skb_dirtytx;
99 unsigned short tx_ring_size;
100 unsigned short rx_ring_size;
103 unsigned short encoding;
104 unsigned short parity;
105 unsigned short hmask;
107 spinlock_t lock; /* lock for Tx BD and Tx buffer */
109 struct ucc_hdlc_param *ucc_pram_bak;
112 u32 cmxsi1cr_l, cmxsi1cr_h;
118 #define TX_BD_RING_LEN 0x10
119 #define RX_BD_RING_LEN 0x20
120 #define RX_CLEAN_MAX 0x10
122 #define MAX_RX_BUF_LENGTH (48 * 0x20)
123 #define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8)
124 #define ALIGNMENT_OF_UCC_HDLC_PRAM 64
125 #define SI_BANK_SIZE 128
126 #define MAX_HDLC_NUM 4
127 #define HDLC_HEAD_LEN 2
128 #define HDLC_CRC_SIZE 2
129 #define TX_RING_MOD_MASK(size) (size - 1)
130 #define RX_RING_MOD_MASK(size) (size - 1)
132 #define HDLC_HEAD_MASK 0x0000
133 #define DEFAULT_HDLC_HEAD 0xff44
134 #define DEFAULT_ADDR_MASK 0x00ff
135 #define DEFAULT_HDLC_ADDR 0x00ff
137 #define BMR_GBL 0x20000000
138 #define BMR_BIG_ENDIAN 0x10000000
139 #define CRC_16BIT_MASK 0x0000F0B8
140 #define CRC_16BIT_PRES 0x0000FFFF
141 #define DEFAULT_RFTHR 1
143 #define DEFAULT_PPP_HEAD 0xff03