1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Freescale QUICC Engine HDLC Device Driver
4 * Copyright 2016 Freescale Semiconductor Inc.
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/hdlc.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/skbuff.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/stddef.h>
26 #include <soc/fsl/qe/qe_tdm.h>
27 #include <uapi/linux/if_arp.h>
29 #include "fsl_ucc_hdlc.h"
31 #define DRV_DESC "Freescale QE UCC HDLC Driver"
32 #define DRV_NAME "ucc_hdlc"
34 #define TDM_PPPOHT_SLIC_MAXIN
35 #define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S)
37 static struct ucc_tdm_info utdm_primary_info = {
52 .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
53 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
54 .tenc = UCC_FAST_TX_ENCODING_NRZ,
55 .renc = UCC_FAST_RX_ENCODING_NRZ,
56 .tcrc = UCC_FAST_16_BIT_CRC,
57 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
61 #ifdef TDM_PPPOHT_SLIC_MAXIN
76 static struct ucc_tdm_info utdm_info[UCC_MAX_NUM];
78 static int uhdlc_init(struct ucc_hdlc_private *priv)
80 struct ucc_tdm_info *ut_info;
81 struct ucc_fast_info *uf_info;
86 dma_addr_t bd_dma_addr;
91 ut_info = priv->ut_info;
92 uf_info = &ut_info->uf_info;
105 /* This sets HPM register in CMXUCR register which configures a
106 * open drain connected HDLC bus
109 uf_info->brkpt_support = 1;
111 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
112 UCC_HDLC_UCCE_TXB) << 16);
114 ret = ucc_fast_init(uf_info, &priv->uccf);
116 dev_err(priv->dev, "Failed to init uccf.");
120 priv->uf_regs = priv->uccf->uf_regs;
121 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
124 if (priv->loopback) {
125 dev_info(priv->dev, "Loopback Mode\n");
126 /* use the same clock when work in loopback */
127 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
129 gumr = ioread32be(&priv->uf_regs->gumr);
130 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
132 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
133 iowrite32be(gumr, &priv->uf_regs->gumr);
138 ucc_tdm_init(priv->utdm, priv->ut_info);
140 /* Write to QE CECR, UCCx channel to Stop Transmission */
141 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
142 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
143 QE_CR_PROTOCOL_UNSPECIFIED, 0);
145 /* Set UPSMR normal mode (need fixed)*/
146 iowrite32be(0, &priv->uf_regs->upsmr);
149 if (priv->hdlc_bus) {
152 dev_info(priv->dev, "HDLC bus Mode\n");
153 upsmr = ioread32be(&priv->uf_regs->upsmr);
155 /* bus mode and retransmit enable, with collision window
158 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
160 iowrite32be(upsmr, &priv->uf_regs->upsmr);
162 /* explicitly disable CDS & CTSP */
163 gumr = ioread32be(&priv->uf_regs->gumr);
164 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
165 /* set automatic sync to explicitly ignore CD signal */
166 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
167 iowrite32be(gumr, &priv->uf_regs->gumr);
170 priv->rx_ring_size = RX_BD_RING_LEN;
171 priv->tx_ring_size = TX_BD_RING_LEN;
173 priv->rx_bd_base = dma_alloc_coherent(priv->dev,
174 RX_BD_RING_LEN * sizeof(struct qe_bd),
175 &priv->dma_rx_bd, GFP_KERNEL);
177 if (!priv->rx_bd_base) {
178 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
184 priv->tx_bd_base = dma_alloc_coherent(priv->dev,
185 TX_BD_RING_LEN * sizeof(struct qe_bd),
186 &priv->dma_tx_bd, GFP_KERNEL);
188 if (!priv->tx_bd_base) {
189 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
194 /* Alloc parameter ram for ucc hdlc */
195 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
196 ALIGNMENT_OF_UCC_HDLC_PRAM);
198 if (priv->ucc_pram_offset < 0) {
199 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
204 priv->rx_skbuff = kcalloc(priv->rx_ring_size,
205 sizeof(*priv->rx_skbuff),
207 if (!priv->rx_skbuff) {
212 priv->tx_skbuff = kcalloc(priv->tx_ring_size,
213 sizeof(*priv->tx_skbuff),
215 if (!priv->tx_skbuff) {
221 priv->skb_dirtytx = 0;
222 priv->curtx_bd = priv->tx_bd_base;
223 priv->dirty_tx = priv->tx_bd_base;
224 priv->currx_bd = priv->rx_bd_base;
225 priv->currx_bdnum = 0;
227 /* init parameter base */
228 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
229 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
230 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
232 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
233 qe_muram_addr(priv->ucc_pram_offset);
235 /* Zero out parameter ram */
236 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
238 /* Alloc riptr, tiptr */
239 riptr = qe_muram_alloc(32, 32);
241 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
246 tiptr = qe_muram_alloc(32, 32);
248 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
252 if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
253 dev_err(priv->dev, "MURAM allocation out of addressable range\n");
258 /* Set RIPTR, TIPTR */
259 iowrite16be(riptr, &priv->ucc_pram->riptr);
260 iowrite16be(tiptr, &priv->ucc_pram->tiptr);
263 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
265 /* Set RBASE, TBASE */
266 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
267 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
269 /* Set RSTATE, TSTATE */
270 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
271 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
273 /* Set C_MASK, C_PRES for 16bit CRC */
274 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
275 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
277 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
278 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
279 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
280 iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
281 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
282 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
283 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
284 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
287 bd_buffer = dma_alloc_coherent(priv->dev,
288 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
289 &bd_dma_addr, GFP_KERNEL);
292 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
297 priv->rx_buffer = bd_buffer;
298 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
300 priv->dma_rx_addr = bd_dma_addr;
301 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
303 for (i = 0; i < RX_BD_RING_LEN; i++) {
304 if (i < (RX_BD_RING_LEN - 1))
305 bd_status = R_E_S | R_I_S;
307 bd_status = R_E_S | R_I_S | R_W_S;
309 priv->rx_bd_base[i].status = cpu_to_be16(bd_status);
310 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH);
313 for (i = 0; i < TX_BD_RING_LEN; i++) {
314 if (i < (TX_BD_RING_LEN - 1))
315 bd_status = T_I_S | T_TC_S;
317 bd_status = T_I_S | T_TC_S | T_W_S;
319 priv->tx_bd_base[i].status = cpu_to_be16(bd_status);
320 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH);
327 qe_muram_free(tiptr);
329 qe_muram_free(riptr);
331 kfree(priv->tx_skbuff);
333 kfree(priv->rx_skbuff);
335 qe_muram_free(priv->ucc_pram_offset);
337 dma_free_coherent(priv->dev,
338 TX_BD_RING_LEN * sizeof(struct qe_bd),
339 priv->tx_bd_base, priv->dma_tx_bd);
341 dma_free_coherent(priv->dev,
342 RX_BD_RING_LEN * sizeof(struct qe_bd),
343 priv->rx_bd_base, priv->dma_rx_bd);
345 ucc_fast_free(priv->uccf);
350 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
352 hdlc_device *hdlc = dev_to_hdlc(dev);
353 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
361 if (skb_headroom(skb) < HDLC_HEAD_LEN) {
362 dev->stats.tx_dropped++;
364 netdev_err(dev, "No enough space for hdlc head\n");
368 skb_push(skb, HDLC_HEAD_LEN);
370 proto_head = (__be16 *)skb->data;
371 *proto_head = htons(DEFAULT_HDLC_HEAD);
373 dev->stats.tx_bytes += skb->len;
377 proto_head = (__be16 *)skb->data;
378 if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
379 dev->stats.tx_dropped++;
381 netdev_err(dev, "Wrong ppp header\n");
385 dev->stats.tx_bytes += skb->len;
389 dev->stats.tx_bytes += skb->len;
393 dev->stats.tx_dropped++;
397 netdev_sent_queue(dev, skb->len);
398 spin_lock_irqsave(&priv->lock, flags);
401 /* Start from the next BD that should be filled */
403 bd_status = be16_to_cpu(bd->status);
404 /* Save the skb pointer so we can free it later */
405 priv->tx_skbuff[priv->skb_curtx] = skb;
407 /* Update the current skb pointer (wrapping if this was the last) */
409 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
411 /* copy skb data to tx buffer for sdma processing */
412 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
413 skb->data, skb->len);
415 /* set bd status and length */
416 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
418 bd->length = cpu_to_be16(skb->len);
419 bd->status = cpu_to_be16(bd_status);
421 /* Move to next BD in the ring */
422 if (!(bd_status & T_W_S))
425 bd = priv->tx_bd_base;
427 if (bd == priv->dirty_tx) {
428 if (!netif_queue_stopped(dev))
429 netif_stop_queue(dev);
434 spin_unlock_irqrestore(&priv->lock, flags);
439 static int hdlc_tx_restart(struct ucc_hdlc_private *priv)
444 ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num);
446 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
447 QE_CR_PROTOCOL_UNSPECIFIED, 0);
451 static int hdlc_tx_done(struct ucc_hdlc_private *priv)
453 /* Start from the next BD that should be filled */
454 struct net_device *dev = priv->ndev;
455 unsigned int bytes_sent = 0;
457 struct qe_bd *bd; /* BD pointer */
463 bd_status = be16_to_cpu(bd->status);
465 /* Normal processing. */
466 while ((bd_status & T_R_S) == 0) {
469 if (bd_status & T_UN_S) { /* Underrun */
470 dev->stats.tx_fifo_errors++;
473 if (bd_status & T_CT_S) { /* Carrier lost */
474 dev->stats.tx_carrier_errors++;
478 /* BD contains already transmitted buffer. */
479 /* Handle the transmitted buffer and release */
480 /* the BD to be used with the current frame */
482 skb = priv->tx_skbuff[priv->skb_dirtytx];
486 bytes_sent += skb->len;
487 dev->stats.tx_packets++;
488 memset(priv->tx_buffer +
489 (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
491 dev_consume_skb_irq(skb);
493 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
496 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
498 /* We freed a buffer, so now we can restart transmission */
499 if (netif_queue_stopped(dev))
500 netif_wake_queue(dev);
502 /* Advance the confirmation BD pointer */
503 if (!(bd_status & T_W_S))
506 bd = priv->tx_bd_base;
507 bd_status = be16_to_cpu(bd->status);
512 hdlc_tx_restart(priv);
514 netdev_completed_queue(dev, howmany, bytes_sent);
518 static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
520 struct net_device *dev = priv->ndev;
521 struct sk_buff *skb = NULL;
522 hdlc_device *hdlc = dev_to_hdlc(dev);
525 u16 length, howmany = 0;
530 bd_status = be16_to_cpu(bd->status);
532 /* while there are received buffers and BD is full (~R_E) */
533 while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
534 if (bd_status & (RX_BD_ERRORS)) {
535 dev->stats.rx_errors++;
537 if (bd_status & R_CD_S)
538 dev->stats.collisions++;
539 if (bd_status & R_OV_S)
540 dev->stats.rx_fifo_errors++;
541 if (bd_status & R_CR_S)
542 dev->stats.rx_crc_errors++;
543 if (bd_status & R_AB_S)
544 dev->stats.rx_over_errors++;
545 if (bd_status & R_NO_S)
546 dev->stats.rx_frame_errors++;
547 if (bd_status & R_LG_S)
548 dev->stats.rx_length_errors++;
552 bdbuffer = priv->rx_buffer +
553 (priv->currx_bdnum * MAX_RX_BUF_LENGTH);
554 length = be16_to_cpu(bd->length);
558 bdbuffer += HDLC_HEAD_LEN;
559 length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
561 skb = dev_alloc_skb(length);
563 dev->stats.rx_dropped++;
567 skb_put(skb, length);
570 memcpy(skb->data, bdbuffer, length);
575 length -= HDLC_CRC_SIZE;
577 skb = dev_alloc_skb(length);
579 dev->stats.rx_dropped++;
583 skb_put(skb, length);
586 memcpy(skb->data, bdbuffer, length);
590 dev->stats.rx_packets++;
591 dev->stats.rx_bytes += skb->len;
594 skb->protocol = hdlc_type_trans(skb, dev);
595 netif_receive_skb(skb);
598 bd->status = cpu_to_be16((bd_status & R_W_S) | R_E_S | R_I_S);
600 /* update to point at the next bd */
601 if (bd_status & R_W_S) {
602 priv->currx_bdnum = 0;
603 bd = priv->rx_bd_base;
605 if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
606 priv->currx_bdnum += 1;
608 priv->currx_bdnum = RX_BD_RING_LEN - 1;
613 bd_status = be16_to_cpu(bd->status);
621 static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
623 struct ucc_hdlc_private *priv = container_of(napi,
624 struct ucc_hdlc_private,
628 /* Tx event processing */
629 spin_lock(&priv->lock);
631 spin_unlock(&priv->lock);
634 howmany += hdlc_rx_done(priv, budget - howmany);
636 if (howmany < budget) {
637 napi_complete_done(napi, howmany);
638 qe_setbits_be32(priv->uccf->p_uccm,
639 (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
645 static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
647 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
648 struct net_device *dev = priv->ndev;
649 struct ucc_fast_private *uccf;
655 ucce = ioread32be(uccf->p_ucce);
656 uccm = ioread32be(uccf->p_uccm);
658 iowrite32be(ucce, uccf->p_ucce);
662 if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
663 if (napi_schedule_prep(&priv->napi)) {
664 uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
666 iowrite32be(uccm, uccf->p_uccm);
667 __napi_schedule(&priv->napi);
671 /* Errors and other events */
672 if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
673 dev->stats.rx_missed_errors++;
674 if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
675 dev->stats.tx_errors++;
680 static int uhdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
682 const size_t size = sizeof(te1_settings);
684 struct ucc_hdlc_private *priv = netdev_priv(dev);
688 ifs->type = IF_IFACE_E1;
689 if (ifs->size < size) {
690 ifs->size = size; /* data size wanted */
693 memset(&line, 0, sizeof(line));
694 line.clock_type = priv->clocking;
696 if (copy_to_user(ifs->ifs_ifsu.sync, &line, size))
701 return hdlc_ioctl(dev, ifs);
705 static int uhdlc_open(struct net_device *dev)
708 hdlc_device *hdlc = dev_to_hdlc(dev);
709 struct ucc_hdlc_private *priv = hdlc->priv;
710 struct ucc_tdm *utdm = priv->utdm;
712 if (priv->hdlc_busy != 1) {
713 if (request_irq(priv->ut_info->uf_info.irq,
714 ucc_hdlc_irq_handler, 0, "hdlc", priv))
717 cecr_subblock = ucc_fast_get_qe_cr_subblock(
718 priv->ut_info->uf_info.ucc_num);
720 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
721 QE_CR_PROTOCOL_UNSPECIFIED, 0);
723 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
725 /* Enable the TDM port */
727 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
730 netif_device_attach(priv->ndev);
731 napi_enable(&priv->napi);
732 netdev_reset_queue(dev);
733 netif_start_queue(dev);
740 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
742 qe_muram_free(ioread16be(&priv->ucc_pram->riptr));
743 qe_muram_free(ioread16be(&priv->ucc_pram->tiptr));
745 if (priv->rx_bd_base) {
746 dma_free_coherent(priv->dev,
747 RX_BD_RING_LEN * sizeof(struct qe_bd),
748 priv->rx_bd_base, priv->dma_rx_bd);
750 priv->rx_bd_base = NULL;
754 if (priv->tx_bd_base) {
755 dma_free_coherent(priv->dev,
756 TX_BD_RING_LEN * sizeof(struct qe_bd),
757 priv->tx_bd_base, priv->dma_tx_bd);
759 priv->tx_bd_base = NULL;
763 if (priv->ucc_pram) {
764 qe_muram_free(priv->ucc_pram_offset);
765 priv->ucc_pram = NULL;
766 priv->ucc_pram_offset = 0;
769 kfree(priv->rx_skbuff);
770 priv->rx_skbuff = NULL;
772 kfree(priv->tx_skbuff);
773 priv->tx_skbuff = NULL;
776 iounmap(priv->uf_regs);
777 priv->uf_regs = NULL;
781 ucc_fast_free(priv->uccf);
785 if (priv->rx_buffer) {
786 dma_free_coherent(priv->dev,
787 RX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
788 priv->rx_buffer, priv->dma_rx_addr);
789 priv->rx_buffer = NULL;
790 priv->dma_rx_addr = 0;
793 if (priv->tx_buffer) {
794 dma_free_coherent(priv->dev,
795 TX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
796 priv->tx_buffer, priv->dma_tx_addr);
797 priv->tx_buffer = NULL;
798 priv->dma_tx_addr = 0;
802 static int uhdlc_close(struct net_device *dev)
804 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
805 struct ucc_tdm *utdm = priv->utdm;
808 napi_disable(&priv->napi);
809 cecr_subblock = ucc_fast_get_qe_cr_subblock(
810 priv->ut_info->uf_info.ucc_num);
812 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
813 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
814 qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
815 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
818 qe_clrbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
820 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
822 free_irq(priv->ut_info->uf_info.irq, priv);
823 netif_stop_queue(dev);
824 netdev_reset_queue(dev);
830 static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
831 unsigned short parity)
833 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
835 if (encoding != ENCODING_NRZ &&
836 encoding != ENCODING_NRZI)
839 if (parity != PARITY_NONE &&
840 parity != PARITY_CRC32_PR1_CCITT &&
841 parity != PARITY_CRC16_PR0_CCITT &&
842 parity != PARITY_CRC16_PR1_CCITT)
845 priv->encoding = encoding;
846 priv->parity = parity;
852 static void store_clk_config(struct ucc_hdlc_private *priv)
854 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx;
857 priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
858 priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
861 priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
864 memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
867 static void resume_clk_config(struct ucc_hdlc_private *priv)
869 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx;
871 memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
873 iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
874 iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
876 iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
879 static int uhdlc_suspend(struct device *dev)
881 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
882 struct ucc_fast __iomem *uf_regs;
887 if (!netif_running(priv->ndev))
890 netif_device_detach(priv->ndev);
891 napi_disable(&priv->napi);
893 uf_regs = priv->uf_regs;
895 /* backup gumr guemr*/
896 priv->gumr = ioread32be(&uf_regs->gumr);
897 priv->guemr = ioread8(&uf_regs->guemr);
899 priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak),
901 if (!priv->ucc_pram_bak)
904 /* backup HDLC parameter */
905 memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
906 sizeof(struct ucc_hdlc_param));
908 /* store the clk configuration */
909 store_clk_config(priv);
912 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
917 static int uhdlc_resume(struct device *dev)
919 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
920 struct ucc_tdm *utdm;
921 struct ucc_tdm_info *ut_info;
922 struct ucc_fast __iomem *uf_regs;
923 struct ucc_fast_private *uccf;
924 struct ucc_fast_info *uf_info;
932 if (!netif_running(priv->ndev))
936 ut_info = priv->ut_info;
937 uf_info = &ut_info->uf_info;
938 uf_regs = priv->uf_regs;
941 /* restore gumr guemr */
942 iowrite8(priv->guemr, &uf_regs->guemr);
943 iowrite32be(priv->gumr, &uf_regs->gumr);
945 /* Set Virtual Fifo registers */
946 iowrite16be(uf_info->urfs, &uf_regs->urfs);
947 iowrite16be(uf_info->urfet, &uf_regs->urfet);
948 iowrite16be(uf_info->urfset, &uf_regs->urfset);
949 iowrite16be(uf_info->utfs, &uf_regs->utfs);
950 iowrite16be(uf_info->utfet, &uf_regs->utfet);
951 iowrite16be(uf_info->utftt, &uf_regs->utftt);
952 /* utfb, urfb are offsets from MURAM base */
953 iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
954 iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
956 /* Rx Tx and sync clock routing */
957 resume_clk_config(priv);
959 iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
960 iowrite32be(0xffffffff, &uf_regs->ucce);
962 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
966 ucc_tdm_init(priv->utdm, priv->ut_info);
968 /* Write to QE CECR, UCCx channel to Stop Transmission */
969 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
970 qe_issue_cmd(QE_STOP_TX, cecr_subblock,
971 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
973 /* Set UPSMR normal mode */
974 iowrite32be(0, &uf_regs->upsmr);
976 /* init parameter base */
977 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
978 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
979 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
981 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
982 qe_muram_addr(priv->ucc_pram_offset);
984 /* restore ucc parameter */
985 memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
986 sizeof(struct ucc_hdlc_param));
987 kfree(priv->ucc_pram_bak);
989 /* rebuild BD entry */
990 for (i = 0; i < RX_BD_RING_LEN; i++) {
991 if (i < (RX_BD_RING_LEN - 1))
992 bd_status = R_E_S | R_I_S;
994 bd_status = R_E_S | R_I_S | R_W_S;
996 priv->rx_bd_base[i].status = cpu_to_be16(bd_status);
997 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH);
1000 for (i = 0; i < TX_BD_RING_LEN; i++) {
1001 if (i < (TX_BD_RING_LEN - 1))
1002 bd_status = T_I_S | T_TC_S;
1004 bd_status = T_I_S | T_TC_S | T_W_S;
1006 priv->tx_bd_base[i].status = cpu_to_be16(bd_status);
1007 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH);
1011 /* if hdlc is busy enable TX and RX */
1012 if (priv->hdlc_busy == 1) {
1013 cecr_subblock = ucc_fast_get_qe_cr_subblock(
1014 priv->ut_info->uf_info.ucc_num);
1016 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
1017 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
1019 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
1021 /* Enable the TDM port */
1023 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
1026 napi_enable(&priv->napi);
1027 netif_device_attach(priv->ndev);
1032 static const struct dev_pm_ops uhdlc_pm_ops = {
1033 .suspend = uhdlc_suspend,
1034 .resume = uhdlc_resume,
1035 .freeze = uhdlc_suspend,
1036 .thaw = uhdlc_resume,
1039 #define HDLC_PM_OPS (&uhdlc_pm_ops)
1043 #define HDLC_PM_OPS NULL
1046 static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1048 netdev_err(ndev, "%s\n", __func__);
1051 static const struct net_device_ops uhdlc_ops = {
1052 .ndo_open = uhdlc_open,
1053 .ndo_stop = uhdlc_close,
1054 .ndo_start_xmit = hdlc_start_xmit,
1055 .ndo_siocwandev = uhdlc_ioctl,
1056 .ndo_tx_timeout = uhdlc_tx_timeout,
1059 static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr)
1061 struct device_node *np;
1062 struct platform_device *pdev;
1063 struct resource *res;
1064 static int siram_init_flag;
1067 np = of_find_compatible_node(NULL, NULL, name);
1071 pdev = of_find_device_by_node(np);
1073 pr_err("%pOFn: failed to lookup pdev\n", np);
1079 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 goto error_put_device;
1084 *ptr = ioremap(res->start, resource_size(res));
1087 goto error_put_device;
1090 /* We've remapped the addresses, and we don't need the device any
1091 * more, so we should release it.
1093 put_device(&pdev->dev);
1095 if (init_flag && siram_init_flag == 0) {
1096 memset_io(*ptr, 0, resource_size(res));
1097 siram_init_flag = 1;
1102 put_device(&pdev->dev);
1107 static int ucc_hdlc_probe(struct platform_device *pdev)
1109 struct device_node *np = pdev->dev.of_node;
1110 struct ucc_hdlc_private *uhdlc_priv = NULL;
1111 struct ucc_tdm_info *ut_info;
1112 struct ucc_tdm *utdm = NULL;
1113 struct resource res;
1114 struct net_device *dev;
1121 ret = of_property_read_u32_index(np, "cell-index", 0, &val);
1123 dev_err(&pdev->dev, "Invalid ucc property\n");
1128 if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) {
1129 dev_err(&pdev->dev, ": Invalid UCC num\n");
1133 memcpy(&utdm_info[ucc_num], &utdm_primary_info,
1134 sizeof(utdm_primary_info));
1136 ut_info = &utdm_info[ucc_num];
1137 ut_info->uf_info.ucc_num = ucc_num;
1139 sprop = of_get_property(np, "rx-clock-name", NULL);
1141 ut_info->uf_info.rx_clock = qe_clock_source(sprop);
1142 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
1143 (ut_info->uf_info.rx_clock > QE_CLK24)) {
1144 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1148 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1152 sprop = of_get_property(np, "tx-clock-name", NULL);
1154 ut_info->uf_info.tx_clock = qe_clock_source(sprop);
1155 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
1156 (ut_info->uf_info.tx_clock > QE_CLK24)) {
1157 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1161 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1165 ret = of_address_to_resource(np, 0, &res);
1169 ut_info->uf_info.regs = res.start;
1170 ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
1172 uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL);
1176 dev_set_drvdata(&pdev->dev, uhdlc_priv);
1177 uhdlc_priv->dev = &pdev->dev;
1178 uhdlc_priv->ut_info = ut_info;
1180 if (of_get_property(np, "fsl,tdm-interface", NULL))
1181 uhdlc_priv->tsa = 1;
1183 if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
1184 uhdlc_priv->loopback = 1;
1186 if (of_get_property(np, "fsl,hdlc-bus", NULL))
1187 uhdlc_priv->hdlc_bus = 1;
1189 if (uhdlc_priv->tsa == 1) {
1190 utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
1193 dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
1194 goto free_uhdlc_priv;
1196 uhdlc_priv->utdm = utdm;
1197 ret = ucc_of_parse_tdm(np, utdm, ut_info);
1201 ret = hdlc_map_iomem("fsl,t1040-qe-si", 0,
1202 (void __iomem **)&utdm->si_regs);
1205 ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1,
1206 (void __iomem **)&utdm->siram);
1211 if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask))
1212 uhdlc_priv->hmask = DEFAULT_ADDR_MASK;
1214 ret = uhdlc_init(uhdlc_priv);
1216 dev_err(&pdev->dev, "Failed to init uhdlc\n");
1217 goto undo_uhdlc_init;
1220 dev = alloc_hdlcdev(uhdlc_priv);
1223 pr_err("ucc_hdlc: unable to allocate memory\n");
1224 goto undo_uhdlc_init;
1227 uhdlc_priv->ndev = dev;
1228 hdlc = dev_to_hdlc(dev);
1229 dev->tx_queue_len = 16;
1230 dev->netdev_ops = &uhdlc_ops;
1231 dev->watchdog_timeo = 2 * HZ;
1232 hdlc->attach = ucc_hdlc_attach;
1233 hdlc->xmit = ucc_hdlc_tx;
1234 netif_napi_add_weight(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
1235 if (register_hdlc_device(dev)) {
1237 pr_err("ucc_hdlc: unable to register hdlc device\n");
1246 iounmap(utdm->siram);
1248 iounmap(utdm->si_regs);
1250 if (uhdlc_priv->tsa)
1257 static int ucc_hdlc_remove(struct platform_device *pdev)
1259 struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
1261 uhdlc_memclean(priv);
1263 if (priv->utdm->si_regs) {
1264 iounmap(priv->utdm->si_regs);
1265 priv->utdm->si_regs = NULL;
1268 if (priv->utdm->siram) {
1269 iounmap(priv->utdm->siram);
1270 priv->utdm->siram = NULL;
1274 dev_info(&pdev->dev, "UCC based hdlc module removed\n");
1279 static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
1281 .compatible = "fsl,ucc-hdlc",
1286 MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
1288 static struct platform_driver ucc_hdlc_driver = {
1289 .probe = ucc_hdlc_probe,
1290 .remove = ucc_hdlc_remove,
1294 .of_match_table = fsl_ucc_hdlc_of_match,
1298 module_platform_driver(ucc_hdlc_driver);
1299 MODULE_LICENSE("GPL");
1300 MODULE_DESCRIPTION(DRV_DESC);