2 * Copyright (C) 2015 Red Hat, Inc.
6 * Dave Airlie <airlied@redhat.com>
7 * Gerd Hoffmann <kraxel@redhat.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
30 #include "virtgpu_drv.h"
31 #include <linux/virtio.h>
32 #include <linux/virtio_config.h>
33 #include <linux/virtio_ring.h>
35 #define MAX_INLINE_CMD_SIZE 96
36 #define MAX_INLINE_RESP_SIZE 24
37 #define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \
38 + MAX_INLINE_CMD_SIZE \
39 + MAX_INLINE_RESP_SIZE)
41 void virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
46 idr_preload(GFP_KERNEL);
47 spin_lock(&vgdev->resource_idr_lock);
48 handle = idr_alloc(&vgdev->resource_idr, NULL, 1, 0, GFP_NOWAIT);
49 spin_unlock(&vgdev->resource_idr_lock);
54 void virtio_gpu_resource_id_put(struct virtio_gpu_device *vgdev, uint32_t id)
56 spin_lock(&vgdev->resource_idr_lock);
57 idr_remove(&vgdev->resource_idr, id);
58 spin_unlock(&vgdev->resource_idr_lock);
61 void virtio_gpu_ctrl_ack(struct virtqueue *vq)
63 struct drm_device *dev = vq->vdev->priv;
64 struct virtio_gpu_device *vgdev = dev->dev_private;
66 schedule_work(&vgdev->ctrlq.dequeue_work);
69 void virtio_gpu_cursor_ack(struct virtqueue *vq)
71 struct drm_device *dev = vq->vdev->priv;
72 struct virtio_gpu_device *vgdev = dev->dev_private;
74 schedule_work(&vgdev->cursorq.dequeue_work);
77 int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev)
79 vgdev->vbufs = kmem_cache_create("virtio-gpu-vbufs",
81 __alignof__(struct virtio_gpu_vbuffer),
88 void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev)
90 kmem_cache_destroy(vgdev->vbufs);
94 static struct virtio_gpu_vbuffer*
95 virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev,
96 int size, int resp_size, void *resp_buf,
97 virtio_gpu_resp_cb resp_cb)
99 struct virtio_gpu_vbuffer *vbuf;
101 vbuf = kmem_cache_alloc(vgdev->vbufs, GFP_KERNEL);
103 return ERR_PTR(-ENOMEM);
104 memset(vbuf, 0, VBUFFER_SIZE);
106 BUG_ON(size > MAX_INLINE_CMD_SIZE);
107 vbuf->buf = (void *)vbuf + sizeof(*vbuf);
110 vbuf->resp_cb = resp_cb;
111 vbuf->resp_size = resp_size;
112 if (resp_size <= MAX_INLINE_RESP_SIZE)
113 vbuf->resp_buf = (void *)vbuf->buf + size;
115 vbuf->resp_buf = resp_buf;
116 BUG_ON(!vbuf->resp_buf);
120 static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev,
121 struct virtio_gpu_vbuffer **vbuffer_p,
124 struct virtio_gpu_vbuffer *vbuf;
126 vbuf = virtio_gpu_get_vbuf(vgdev, size,
127 sizeof(struct virtio_gpu_ctrl_hdr),
131 return ERR_CAST(vbuf);
137 static struct virtio_gpu_update_cursor*
138 virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev,
139 struct virtio_gpu_vbuffer **vbuffer_p)
141 struct virtio_gpu_vbuffer *vbuf;
143 vbuf = virtio_gpu_get_vbuf
144 (vgdev, sizeof(struct virtio_gpu_update_cursor),
148 return ERR_CAST(vbuf);
151 return (struct virtio_gpu_update_cursor *)vbuf->buf;
154 static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
155 virtio_gpu_resp_cb cb,
156 struct virtio_gpu_vbuffer **vbuffer_p,
157 int cmd_size, int resp_size,
160 struct virtio_gpu_vbuffer *vbuf;
162 vbuf = virtio_gpu_get_vbuf(vgdev, cmd_size,
163 resp_size, resp_buf, cb);
166 return ERR_CAST(vbuf);
169 return (struct virtio_gpu_command *)vbuf->buf;
172 static void free_vbuf(struct virtio_gpu_device *vgdev,
173 struct virtio_gpu_vbuffer *vbuf)
175 if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
176 kfree(vbuf->resp_buf);
177 kfree(vbuf->data_buf);
178 kmem_cache_free(vgdev->vbufs, vbuf);
181 static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
183 struct virtio_gpu_vbuffer *vbuf;
187 while ((vbuf = virtqueue_get_buf(vq, &len))) {
188 list_add_tail(&vbuf->list, reclaim_list);
192 DRM_DEBUG("Huh? zero vbufs reclaimed");
195 void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
197 struct virtio_gpu_device *vgdev =
198 container_of(work, struct virtio_gpu_device,
200 struct list_head reclaim_list;
201 struct virtio_gpu_vbuffer *entry, *tmp;
202 struct virtio_gpu_ctrl_hdr *resp;
205 INIT_LIST_HEAD(&reclaim_list);
206 spin_lock(&vgdev->ctrlq.qlock);
208 virtqueue_disable_cb(vgdev->ctrlq.vq);
209 reclaim_vbufs(vgdev->ctrlq.vq, &reclaim_list);
211 } while (!virtqueue_enable_cb(vgdev->ctrlq.vq));
212 spin_unlock(&vgdev->ctrlq.qlock);
214 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
215 resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
216 if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA))
217 DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type));
218 if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) {
219 u64 f = le64_to_cpu(resp->fence_id);
222 DRM_ERROR("%s: Oops: fence %llx -> %llx\n",
223 __func__, fence_id, f);
229 entry->resp_cb(vgdev, entry);
231 list_del(&entry->list);
232 free_vbuf(vgdev, entry);
234 wake_up(&vgdev->ctrlq.ack_queue);
237 virtio_gpu_fence_event_process(vgdev, fence_id);
240 void virtio_gpu_dequeue_cursor_func(struct work_struct *work)
242 struct virtio_gpu_device *vgdev =
243 container_of(work, struct virtio_gpu_device,
244 cursorq.dequeue_work);
245 struct list_head reclaim_list;
246 struct virtio_gpu_vbuffer *entry, *tmp;
248 INIT_LIST_HEAD(&reclaim_list);
249 spin_lock(&vgdev->cursorq.qlock);
251 virtqueue_disable_cb(vgdev->cursorq.vq);
252 reclaim_vbufs(vgdev->cursorq.vq, &reclaim_list);
253 } while (!virtqueue_enable_cb(vgdev->cursorq.vq));
254 spin_unlock(&vgdev->cursorq.qlock);
256 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
257 list_del(&entry->list);
258 free_vbuf(vgdev, entry);
260 wake_up(&vgdev->cursorq.ack_queue);
263 static int virtio_gpu_queue_ctrl_buffer_locked(struct virtio_gpu_device *vgdev,
264 struct virtio_gpu_vbuffer *vbuf)
265 __releases(&vgdev->ctrlq.qlock)
266 __acquires(&vgdev->ctrlq.qlock)
268 struct virtqueue *vq = vgdev->ctrlq.vq;
269 struct scatterlist *sgs[3], vcmd, vout, vresp;
270 int outcnt = 0, incnt = 0;
273 if (!vgdev->vqs_ready)
276 sg_init_one(&vcmd, vbuf->buf, vbuf->size);
277 sgs[outcnt + incnt] = &vcmd;
280 if (vbuf->data_size) {
281 sg_init_one(&vout, vbuf->data_buf, vbuf->data_size);
282 sgs[outcnt + incnt] = &vout;
286 if (vbuf->resp_size) {
287 sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
288 sgs[outcnt + incnt] = &vresp;
293 ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
294 if (ret == -ENOSPC) {
295 spin_unlock(&vgdev->ctrlq.qlock);
296 wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= outcnt + incnt);
297 spin_lock(&vgdev->ctrlq.qlock);
308 static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
309 struct virtio_gpu_vbuffer *vbuf)
313 spin_lock(&vgdev->ctrlq.qlock);
314 rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
315 spin_unlock(&vgdev->ctrlq.qlock);
319 static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev,
320 struct virtio_gpu_vbuffer *vbuf,
321 struct virtio_gpu_ctrl_hdr *hdr,
322 struct virtio_gpu_fence **fence)
324 struct virtqueue *vq = vgdev->ctrlq.vq;
328 spin_lock(&vgdev->ctrlq.qlock);
331 * Make sure we have enouth space in the virtqueue. If not
332 * wait here until we have.
334 * Without that virtio_gpu_queue_ctrl_buffer_nolock might have
335 * to wait for free space, which can result in fence ids being
336 * submitted out-of-order.
338 if (vq->num_free < 3) {
339 spin_unlock(&vgdev->ctrlq.qlock);
340 wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= 3);
345 virtio_gpu_fence_emit(vgdev, hdr, fence);
346 rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
347 spin_unlock(&vgdev->ctrlq.qlock);
351 static int virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
352 struct virtio_gpu_vbuffer *vbuf)
354 struct virtqueue *vq = vgdev->cursorq.vq;
355 struct scatterlist *sgs[1], ccmd;
359 if (!vgdev->vqs_ready)
362 sg_init_one(&ccmd, vbuf->buf, vbuf->size);
366 spin_lock(&vgdev->cursorq.qlock);
368 ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
369 if (ret == -ENOSPC) {
370 spin_unlock(&vgdev->cursorq.qlock);
371 wait_event(vgdev->cursorq.ack_queue, vq->num_free >= outcnt);
372 spin_lock(&vgdev->cursorq.qlock);
378 spin_unlock(&vgdev->cursorq.qlock);
385 /* just create gem objects for userspace and long lived objects,
386 * just use dma_alloced pages for the queue objects?
389 /* create a basic resource */
390 void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
391 uint32_t resource_id,
396 struct virtio_gpu_resource_create_2d *cmd_p;
397 struct virtio_gpu_vbuffer *vbuf;
399 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
400 memset(cmd_p, 0, sizeof(*cmd_p));
402 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D);
403 cmd_p->resource_id = cpu_to_le32(resource_id);
404 cmd_p->format = cpu_to_le32(format);
405 cmd_p->width = cpu_to_le32(width);
406 cmd_p->height = cpu_to_le32(height);
408 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
411 void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
412 uint32_t resource_id)
414 struct virtio_gpu_resource_unref *cmd_p;
415 struct virtio_gpu_vbuffer *vbuf;
417 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
418 memset(cmd_p, 0, sizeof(*cmd_p));
420 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF);
421 cmd_p->resource_id = cpu_to_le32(resource_id);
423 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
426 void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev,
427 uint32_t resource_id)
429 struct virtio_gpu_resource_detach_backing *cmd_p;
430 struct virtio_gpu_vbuffer *vbuf;
432 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
433 memset(cmd_p, 0, sizeof(*cmd_p));
435 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING);
436 cmd_p->resource_id = cpu_to_le32(resource_id);
438 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
441 void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
442 uint32_t scanout_id, uint32_t resource_id,
443 uint32_t width, uint32_t height,
444 uint32_t x, uint32_t y)
446 struct virtio_gpu_set_scanout *cmd_p;
447 struct virtio_gpu_vbuffer *vbuf;
449 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
450 memset(cmd_p, 0, sizeof(*cmd_p));
452 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT);
453 cmd_p->resource_id = cpu_to_le32(resource_id);
454 cmd_p->scanout_id = cpu_to_le32(scanout_id);
455 cmd_p->r.width = cpu_to_le32(width);
456 cmd_p->r.height = cpu_to_le32(height);
457 cmd_p->r.x = cpu_to_le32(x);
458 cmd_p->r.y = cpu_to_le32(y);
460 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
463 void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
464 uint32_t resource_id,
465 uint32_t x, uint32_t y,
466 uint32_t width, uint32_t height)
468 struct virtio_gpu_resource_flush *cmd_p;
469 struct virtio_gpu_vbuffer *vbuf;
471 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
472 memset(cmd_p, 0, sizeof(*cmd_p));
474 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
475 cmd_p->resource_id = cpu_to_le32(resource_id);
476 cmd_p->r.width = cpu_to_le32(width);
477 cmd_p->r.height = cpu_to_le32(height);
478 cmd_p->r.x = cpu_to_le32(x);
479 cmd_p->r.y = cpu_to_le32(y);
481 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
484 void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
485 uint32_t resource_id, uint64_t offset,
486 __le32 width, __le32 height,
488 struct virtio_gpu_fence **fence)
490 struct virtio_gpu_transfer_to_host_2d *cmd_p;
491 struct virtio_gpu_vbuffer *vbuf;
493 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
494 memset(cmd_p, 0, sizeof(*cmd_p));
496 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
497 cmd_p->resource_id = cpu_to_le32(resource_id);
498 cmd_p->offset = cpu_to_le64(offset);
499 cmd_p->r.width = width;
500 cmd_p->r.height = height;
504 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
508 virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev,
509 uint32_t resource_id,
510 struct virtio_gpu_mem_entry *ents,
512 struct virtio_gpu_fence **fence)
514 struct virtio_gpu_resource_attach_backing *cmd_p;
515 struct virtio_gpu_vbuffer *vbuf;
517 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
518 memset(cmd_p, 0, sizeof(*cmd_p));
520 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING);
521 cmd_p->resource_id = cpu_to_le32(resource_id);
522 cmd_p->nr_entries = cpu_to_le32(nents);
524 vbuf->data_buf = ents;
525 vbuf->data_size = sizeof(*ents) * nents;
527 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
530 static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev,
531 struct virtio_gpu_vbuffer *vbuf)
533 struct virtio_gpu_resp_display_info *resp =
534 (struct virtio_gpu_resp_display_info *)vbuf->resp_buf;
537 spin_lock(&vgdev->display_info_lock);
538 for (i = 0; i < vgdev->num_scanouts; i++) {
539 vgdev->outputs[i].info = resp->pmodes[i];
540 if (resp->pmodes[i].enabled) {
541 DRM_DEBUG("output %d: %dx%d+%d+%d", i,
542 le32_to_cpu(resp->pmodes[i].r.width),
543 le32_to_cpu(resp->pmodes[i].r.height),
544 le32_to_cpu(resp->pmodes[i].r.x),
545 le32_to_cpu(resp->pmodes[i].r.y));
547 DRM_DEBUG("output %d: disabled", i);
551 vgdev->display_info_pending = false;
552 spin_unlock(&vgdev->display_info_lock);
553 wake_up(&vgdev->resp_wq);
555 if (!drm_helper_hpd_irq_event(vgdev->ddev))
556 drm_kms_helper_hotplug_event(vgdev->ddev);
559 static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev,
560 struct virtio_gpu_vbuffer *vbuf)
562 struct virtio_gpu_get_capset_info *cmd =
563 (struct virtio_gpu_get_capset_info *)vbuf->buf;
564 struct virtio_gpu_resp_capset_info *resp =
565 (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf;
566 int i = le32_to_cpu(cmd->capset_index);
568 spin_lock(&vgdev->display_info_lock);
569 if (vgdev->capsets) {
570 vgdev->capsets[i].id = le32_to_cpu(resp->capset_id);
571 vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version);
572 vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size);
574 DRM_ERROR("invalid capset memory.");
576 spin_unlock(&vgdev->display_info_lock);
577 wake_up(&vgdev->resp_wq);
580 static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev,
581 struct virtio_gpu_vbuffer *vbuf)
583 struct virtio_gpu_get_capset *cmd =
584 (struct virtio_gpu_get_capset *)vbuf->buf;
585 struct virtio_gpu_resp_capset *resp =
586 (struct virtio_gpu_resp_capset *)vbuf->resp_buf;
587 struct virtio_gpu_drv_cap_cache *cache_ent;
589 spin_lock(&vgdev->display_info_lock);
590 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
591 if (cache_ent->version == le32_to_cpu(cmd->capset_version) &&
592 cache_ent->id == le32_to_cpu(cmd->capset_id)) {
593 memcpy(cache_ent->caps_cache, resp->capset_data,
595 /* Copy must occur before is_valid is signalled. */
597 atomic_set(&cache_ent->is_valid, 1);
601 spin_unlock(&vgdev->display_info_lock);
602 wake_up(&vgdev->resp_wq);
605 int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev)
607 struct virtio_gpu_ctrl_hdr *cmd_p;
608 struct virtio_gpu_vbuffer *vbuf;
611 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_display_info),
616 cmd_p = virtio_gpu_alloc_cmd_resp
617 (vgdev, &virtio_gpu_cmd_get_display_info_cb, &vbuf,
618 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_display_info),
620 memset(cmd_p, 0, sizeof(*cmd_p));
622 vgdev->display_info_pending = true;
623 cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
624 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
628 int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx)
630 struct virtio_gpu_get_capset_info *cmd_p;
631 struct virtio_gpu_vbuffer *vbuf;
634 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset_info),
639 cmd_p = virtio_gpu_alloc_cmd_resp
640 (vgdev, &virtio_gpu_cmd_get_capset_info_cb, &vbuf,
641 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_capset_info),
643 memset(cmd_p, 0, sizeof(*cmd_p));
645 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
646 cmd_p->capset_index = cpu_to_le32(idx);
647 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
651 int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
652 int idx, int version,
653 struct virtio_gpu_drv_cap_cache **cache_p)
655 struct virtio_gpu_get_capset *cmd_p;
656 struct virtio_gpu_vbuffer *vbuf;
658 struct virtio_gpu_drv_cap_cache *cache_ent;
661 if (idx >= vgdev->num_capsets)
664 if (version > vgdev->capsets[idx].max_version)
667 cache_ent = kzalloc(sizeof(*cache_ent), GFP_KERNEL);
671 max_size = vgdev->capsets[idx].max_size;
672 cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL);
673 if (!cache_ent->caps_cache) {
678 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size,
681 kfree(cache_ent->caps_cache);
686 cache_ent->version = version;
687 cache_ent->id = vgdev->capsets[idx].id;
688 atomic_set(&cache_ent->is_valid, 0);
689 cache_ent->size = max_size;
690 spin_lock(&vgdev->display_info_lock);
691 list_add_tail(&cache_ent->head, &vgdev->cap_cache);
692 spin_unlock(&vgdev->display_info_lock);
694 cmd_p = virtio_gpu_alloc_cmd_resp
695 (vgdev, &virtio_gpu_cmd_capset_cb, &vbuf, sizeof(*cmd_p),
696 sizeof(struct virtio_gpu_resp_capset) + max_size,
698 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET);
699 cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id);
700 cmd_p->capset_version = cpu_to_le32(version);
701 *cache_p = cache_ent;
702 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
707 void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
708 uint32_t nlen, const char *name)
710 struct virtio_gpu_ctx_create *cmd_p;
711 struct virtio_gpu_vbuffer *vbuf;
713 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
714 memset(cmd_p, 0, sizeof(*cmd_p));
716 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE);
717 cmd_p->hdr.ctx_id = cpu_to_le32(id);
718 cmd_p->nlen = cpu_to_le32(nlen);
719 strncpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name) - 1);
720 cmd_p->debug_name[sizeof(cmd_p->debug_name) - 1] = 0;
721 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
724 void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
727 struct virtio_gpu_ctx_destroy *cmd_p;
728 struct virtio_gpu_vbuffer *vbuf;
730 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
731 memset(cmd_p, 0, sizeof(*cmd_p));
733 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY);
734 cmd_p->hdr.ctx_id = cpu_to_le32(id);
735 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
738 void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
740 uint32_t resource_id)
742 struct virtio_gpu_ctx_resource *cmd_p;
743 struct virtio_gpu_vbuffer *vbuf;
745 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
746 memset(cmd_p, 0, sizeof(*cmd_p));
748 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE);
749 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
750 cmd_p->resource_id = cpu_to_le32(resource_id);
751 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
755 void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
757 uint32_t resource_id)
759 struct virtio_gpu_ctx_resource *cmd_p;
760 struct virtio_gpu_vbuffer *vbuf;
762 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
763 memset(cmd_p, 0, sizeof(*cmd_p));
765 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE);
766 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
767 cmd_p->resource_id = cpu_to_le32(resource_id);
768 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
772 virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
773 struct virtio_gpu_resource_create_3d *rc_3d,
774 struct virtio_gpu_fence **fence)
776 struct virtio_gpu_resource_create_3d *cmd_p;
777 struct virtio_gpu_vbuffer *vbuf;
779 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
780 memset(cmd_p, 0, sizeof(*cmd_p));
783 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D);
784 cmd_p->hdr.flags = 0;
786 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
789 void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
790 uint32_t resource_id, uint32_t ctx_id,
791 uint64_t offset, uint32_t level,
792 struct virtio_gpu_box *box,
793 struct virtio_gpu_fence **fence)
795 struct virtio_gpu_transfer_host_3d *cmd_p;
796 struct virtio_gpu_vbuffer *vbuf;
798 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
799 memset(cmd_p, 0, sizeof(*cmd_p));
801 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
802 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
803 cmd_p->resource_id = cpu_to_le32(resource_id);
805 cmd_p->offset = cpu_to_le64(offset);
806 cmd_p->level = cpu_to_le32(level);
808 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
811 void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
812 uint32_t resource_id, uint32_t ctx_id,
813 uint64_t offset, uint32_t level,
814 struct virtio_gpu_box *box,
815 struct virtio_gpu_fence **fence)
817 struct virtio_gpu_transfer_host_3d *cmd_p;
818 struct virtio_gpu_vbuffer *vbuf;
820 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
821 memset(cmd_p, 0, sizeof(*cmd_p));
823 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D);
824 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
825 cmd_p->resource_id = cpu_to_le32(resource_id);
827 cmd_p->offset = cpu_to_le64(offset);
828 cmd_p->level = cpu_to_le32(level);
830 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
833 void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
834 void *data, uint32_t data_size,
835 uint32_t ctx_id, struct virtio_gpu_fence **fence)
837 struct virtio_gpu_cmd_submit *cmd_p;
838 struct virtio_gpu_vbuffer *vbuf;
840 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
841 memset(cmd_p, 0, sizeof(*cmd_p));
843 vbuf->data_buf = data;
844 vbuf->data_size = data_size;
846 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D);
847 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
848 cmd_p->size = cpu_to_le32(data_size);
850 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
853 int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
854 struct virtio_gpu_object *obj,
855 uint32_t resource_id,
856 struct virtio_gpu_fence **fence)
858 struct virtio_gpu_mem_entry *ents;
859 struct scatterlist *sg;
865 ret = virtio_gpu_object_get_sg_table(vgdev, obj);
870 /* gets freed when the ring has consumed it */
871 ents = kvmalloc_array(obj->pages->nents,
872 sizeof(struct virtio_gpu_mem_entry),
875 DRM_ERROR("failed to allocate ent list\n");
879 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, si) {
880 ents[si].addr = cpu_to_le64(sg_phys(sg));
881 ents[si].length = cpu_to_le32(sg->length);
882 ents[si].padding = 0;
885 virtio_gpu_cmd_resource_attach_backing(vgdev, resource_id,
886 ents, obj->pages->nents,
888 obj->hw_res_handle = resource_id;
892 void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
893 struct virtio_gpu_output *output)
895 struct virtio_gpu_vbuffer *vbuf;
896 struct virtio_gpu_update_cursor *cur_p;
898 output->cursor.pos.scanout_id = cpu_to_le32(output->index);
899 cur_p = virtio_gpu_alloc_cursor(vgdev, &vbuf);
900 memcpy(cur_p, &output->cursor, sizeof(output->cursor));
901 virtio_gpu_queue_cursor(vgdev, vbuf);