virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 static bool group0_trap;
  25 static bool group1_trap;
  26 static bool common_trap;
  27
  28 void vgic_v3_set_npie(struct kvm_vcpu *vcpu)
  29 {
  30         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  31
  32         cpuif->vgic_hcr |= ICH_HCR_NPIE;
  33 }
  34
  35 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  36 {
  37         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  38
  39         cpuif->vgic_hcr |= ICH_HCR_UIE;
  40 }
  41
  42 static bool lr_signals_eoi_mi(u64 lr_val)
  43 {
  44         return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
  45                !(lr_val & ICH_LR_HW);
  46 }
  47
  48 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  49 {
  50         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  51         struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
  52         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  53         int lr;
  54
  55         cpuif->vgic_hcr &= ~(ICH_HCR_UIE | ICH_HCR_NPIE);
  56
  57         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  58                 u64 val = cpuif->vgic_lr[lr];
  59                 u32 intid;
  60                 struct vgic_irq *irq;
  61
  62                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  63                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  64                 else
  65                         intid = val & GICH_LR_VIRTUALID;
  66
  67                 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
  68                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  69                         kvm_notify_acked_irq(vcpu->kvm, 0,
  70                                              intid - VGIC_NR_PRIVATE_IRQS);
  71
  72                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  73                 if (!irq)       /* An LPI could have been unmapped. */
  74                         continue;
  75
  76                 spin_lock(&irq->irq_lock);
  77
  78                 /* Always preserve the active bit */
  79                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  80
  81                 /* Edge is the only case where we preserve the pending bit */
  82                 if (irq->config == VGIC_CONFIG_EDGE &&
  83                     (val & ICH_LR_PENDING_BIT)) {
  84                         irq->pending_latch = true;
  85
  86                         if (vgic_irq_is_sgi(intid) &&
  87                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
  88                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  89
  90                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  91                                 irq->source |= (1 << cpuid);
  92                         }
  93                 }
  94
  95                 /*
  96                  * Clear soft pending state when level irqs have been acked.
  97                  * Always regenerate the pending state.
  98                  */
  99                 if (irq->config == VGIC_CONFIG_LEVEL) {
 100                         if (!(val & ICH_LR_PENDING_BIT))
 101                                 irq->pending_latch = false;
 102                 }
 103
 104                 spin_unlock(&irq->irq_lock);
 105                 vgic_put_irq(vcpu->kvm, irq);
 106         }
 107
 108         vgic_cpu->used_lrs = 0;
 109 }
 110
 111 /* Requires the irq to be locked already */
 112 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 113 {
 114         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 115         u64 val = irq->intid;
 116
 117         if (irq_is_pending(irq)) {
 118                 val |= ICH_LR_PENDING_BIT;
 119
 120                 if (irq->config == VGIC_CONFIG_EDGE)
 121                         irq->pending_latch = false;
 122
 123                 if (vgic_irq_is_sgi(irq->intid) &&
 124                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 125                         u32 src = ffs(irq->source);
 126
 127                         if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
 128                                            irq->intid))
 129                                 return;
 130
 131                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 132                         irq->source &= ~(1 << (src - 1));
 133                         if (irq->source)
 134                                 irq->pending_latch = true;
 135                 }
 136         }
 137
 138         if (irq->active)
 139                 val |= ICH_LR_ACTIVE_BIT;
 140
 141         if (irq->hw) {
 142                 val |= ICH_LR_HW;
 143                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 144                 /*
 145                  * Never set pending+active on a HW interrupt, as the
 146                  * pending state is kept at the physical distributor
 147                  * level.
 148                  */
 149                 if (irq->active && irq_is_pending(irq))
 150                         val &= ~ICH_LR_PENDING_BIT;
 151         } else {
 152                 if (irq->config == VGIC_CONFIG_LEVEL)
 153                         val |= ICH_LR_EOI;
 154         }
 155
 156         /*
 157          * We currently only support Group1 interrupts, which is a
 158          * known defect. This needs to be addressed at some point.
 159          */
 160         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 161                 val |= ICH_LR_GROUP;
 162
 163         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 164
 165         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 166 }
 167
 168 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 169 {
 170         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 171 }
 172
 173 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 174 {
 175         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 176         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 177         u32 vmcr;
 178
 179         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 180                 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
 181                         ICH_VMCR_ACK_CTL_MASK;
 182                 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
 183                         ICH_VMCR_FIQ_EN_MASK;
 184         } else {
 185                 /*
 186                  * When emulating GICv3 on GICv3 with SRE=1 on the
 187                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 188                  */
 189                 vmcr = ICH_VMCR_FIQ_EN_MASK;
 190         }
 191
 192         vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 193         vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
 194         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 195         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 196         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 197         vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
 198         vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 199
 200         cpu_if->vgic_vmcr = vmcr;
 201 }
 202
 203 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 204 {
 205         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 206         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 207         u32 vmcr;
 208
 209         vmcr = cpu_if->vgic_vmcr;
 210
 211         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 212                 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
 213                         ICH_VMCR_ACK_CTL_SHIFT;
 214                 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
 215                         ICH_VMCR_FIQ_EN_SHIFT;
 216         } else {
 217                 /*
 218                  * When emulating GICv3 on GICv3 with SRE=1 on the
 219                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 220                  */
 221                 vmcrp->fiqen = 1;
 222                 vmcrp->ackctl = 0;
 223         }
 224
 225         vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 226         vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
 227         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 228         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 229         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 230         vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
 231         vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 232 }
 233
 234 #define INITIAL_PENDBASER_VALUE                                           \
 235         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
 236         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
 237         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
 238
 239 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 240 {
 241         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 242
 243         /*
 244          * By forcing VMCR to zero, the GIC will restore the binary
 245          * points to their reset values. Anything else resets to zero
 246          * anyway.
 247          */
 248         vgic_v3->vgic_vmcr = 0;
 249         vgic_v3->vgic_elrsr = ~0;
 250
 251         /*
 252          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 253          * way, so we force SRE to 1 to demonstrate this to the guest.
 254          * Also, we don't support any form of IRQ/FIQ bypass.
 255          * This goes with the spec allowing the value to be RAO/WI.
 256          */
 257         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
 258                 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
 259                                      ICC_SRE_EL1_DFB |
 260                                      ICC_SRE_EL1_SRE);
 261                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
 262         } else {
 263                 vgic_v3->vgic_sre = 0;
 264         }
 265
 266         vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
 267                                            ICH_VTR_ID_BITS_MASK) >>
 268                                            ICH_VTR_ID_BITS_SHIFT;
 269         vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
 270                                             ICH_VTR_PRI_BITS_MASK) >>
 271                                             ICH_VTR_PRI_BITS_SHIFT) + 1;
 272
 273         /* Get the show on the road... */
 274         vgic_v3->vgic_hcr = ICH_HCR_EN;
 275         if (group0_trap)
 276                 vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
 277         if (group1_trap)
 278                 vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
 279         if (common_trap)
 280                 vgic_v3->vgic_hcr |= ICH_HCR_TC;
 281 }
 282
 283 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
 284 {
 285         struct kvm_vcpu *vcpu;
 286         int byte_offset, bit_nr;
 287         gpa_t pendbase, ptr;
 288         bool status;
 289         u8 val;
 290         int ret;
 291
 292 retry:
 293         vcpu = irq->target_vcpu;
 294         if (!vcpu)
 295                 return 0;
 296
 297         pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 298
 299         byte_offset = irq->intid / BITS_PER_BYTE;
 300         bit_nr = irq->intid % BITS_PER_BYTE;
 301         ptr = pendbase + byte_offset;
 302
 303         ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
 304         if (ret)
 305                 return ret;
 306
 307         status = val & (1 << bit_nr);
 308
 309         spin_lock(&irq->irq_lock);
 310         if (irq->target_vcpu != vcpu) {
 311                 spin_unlock(&irq->irq_lock);
 312                 goto retry;
 313         }
 314         irq->pending_latch = status;
 315         vgic_queue_irq_unlock(vcpu->kvm, irq);
 316
 317         if (status) {
 318                 /* clear consumed data */
 319                 val &= ~(1 << bit_nr);
 320                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 321                 if (ret)
 322                         return ret;
 323         }
 324         return 0;
 325 }
 326
 327 /**
 328  * vgic_its_save_pending_tables - Save the pending tables into guest RAM
 329  * kvm lock and all vcpu lock must be held
 330  */
 331 int vgic_v3_save_pending_tables(struct kvm *kvm)
 332 {
 333         struct vgic_dist *dist = &kvm->arch.vgic;
 334         struct vgic_irq *irq;
 335         gpa_t last_ptr = ~(gpa_t)0;
 336         int ret;
 337         u8 val;
 338
 339         list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
 340                 int byte_offset, bit_nr;
 341                 struct kvm_vcpu *vcpu;
 342                 gpa_t pendbase, ptr;
 343                 bool stored;
 344
 345                 vcpu = irq->target_vcpu;
 346                 if (!vcpu)
 347                         continue;
 348
 349                 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 350
 351                 byte_offset = irq->intid / BITS_PER_BYTE;
 352                 bit_nr = irq->intid % BITS_PER_BYTE;
 353                 ptr = pendbase + byte_offset;
 354
 355                 if (ptr != last_ptr) {
 356                         ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
 357                         if (ret)
 358                                 return ret;
 359                         last_ptr = ptr;
 360                 }
 361
 362                 stored = val & (1U << bit_nr);
 363                 if (stored == irq->pending_latch)
 364                         continue;
 365
 366                 if (irq->pending_latch)
 367                         val |= 1 << bit_nr;
 368                 else
 369                         val &= ~(1 << bit_nr);
 370
 371                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 372                 if (ret)
 373                         return ret;
 374         }
 375         return 0;
 376 }
 377
 378 /*
 379  * Check for overlapping regions and for regions crossing the end of memory
 380  * for base addresses which have already been set.
 381  */
 382 bool vgic_v3_check_base(struct kvm *kvm)
 383 {
 384         struct vgic_dist *d = &kvm->arch.vgic;
 385         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 386
 387         redist_size *= atomic_read(&kvm->online_vcpus);
 388
 389         if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 390             d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 391                 return false;
 392
 393         if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
 394             d->vgic_redist_base + redist_size < d->vgic_redist_base)
 395                 return false;
 396
 397         /* Both base addresses must be set to check if they overlap */
 398         if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) ||
 399             IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
 400                 return true;
 401
 402         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 403                 return true;
 404         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 405                 return true;
 406
 407         return false;
 408 }
 409
 410 int vgic_v3_map_resources(struct kvm *kvm)
 411 {
 412         int ret = 0;
 413         struct vgic_dist *dist = &kvm->arch.vgic;
 414
 415         if (vgic_ready(kvm))
 416                 goto out;
 417
 418         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 419             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 420                 kvm_err("Need to set vgic distributor addresses first\n");
 421                 ret = -ENXIO;
 422                 goto out;
 423         }
 424
 425         if (!vgic_v3_check_base(kvm)) {
 426                 kvm_err("VGIC redist and dist frames overlap\n");
 427                 ret = -EINVAL;
 428                 goto out;
 429         }
 430
 431         /*
 432          * For a VGICv3 we require the userland to explicitly initialize
 433          * the VGIC before we need to use it.
 434          */
 435         if (!vgic_initialized(kvm)) {
 436                 ret = -EBUSY;
 437                 goto out;
 438         }
 439
 440         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 441         if (ret) {
 442                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 443                 goto out;
 444         }
 445
 446         dist->ready = true;
 447
 448 out:
 449         return ret;
 450 }
 451
 452 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
 453
 454 static int __init early_group0_trap_cfg(char *buf)
 455 {
 456         return strtobool(buf, &group0_trap);
 457 }
 458 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
 459
 460 static int __init early_group1_trap_cfg(char *buf)
 461 {
 462         return strtobool(buf, &group1_trap);
 463 }
 464 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
 465
 466 static int __init early_common_trap_cfg(char *buf)
 467 {
 468         return strtobool(buf, &common_trap);
 469 }
 470 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
 471
 472 /**
 473  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 474  * @node:       pointer to the DT node
 475  *
 476  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 477  */
 478 int vgic_v3_probe(const struct gic_kvm_info *info)
 479 {
 480         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 481         int ret;
 482
 483         /*
 484          * The ListRegs field is 5 bits, but there is a architectural
 485          * maximum of 16 list registers. Just ignore bit 4...
 486          */
 487         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 488         kvm_vgic_global_state.can_emulate_gicv2 = false;
 489         kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 490
 491         if (!info->vcpu.start) {
 492                 kvm_info("GICv3: no GICV resource entry\n");
 493                 kvm_vgic_global_state.vcpu_base = 0;
 494         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 495                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 496                         (unsigned long long)info->vcpu.start);
 497                 kvm_vgic_global_state.vcpu_base = 0;
 498         } else {
 499                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 500                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 501                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 502                 if (ret) {
 503                         kvm_err("Cannot register GICv2 KVM device.\n");
 504                         return ret;
 505                 }
 506                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 507         }
 508         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 509         if (ret) {
 510                 kvm_err("Cannot register GICv3 KVM device.\n");
 511                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 512                 return ret;
 513         }
 514
 515         if (kvm_vgic_global_state.vcpu_base == 0)
 516                 kvm_info("disabling GICv2 emulation\n");
 517
 518 #ifdef CONFIG_ARM64
 519         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
 520                 group0_trap = true;
 521                 group1_trap = true;
 522         }
 523 #endif
 524
 525         if (group0_trap || group1_trap || common_trap) {
 526                 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n",
 527                          group0_trap ? "G0" : "",
 528                          group1_trap ? "G1" : "",
 529                          common_trap ? "C"  : "");
 530                 static_branch_enable(&vgic_v3_cpuif_trap);
 531         }
 532
 533         kvm_vgic_global_state.vctrl_base = NULL;
 534         kvm_vgic_global_state.type = VGIC_V3;
 535         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 536
 537         return 0;
 538 }
 539
 540 void vgic_v3_load(struct kvm_vcpu *vcpu)
 541 {
 542         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 543
 544         /*
 545          * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
 546          * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
 547          * VMCR_EL2 save/restore in the world switch.
 548          */
 549         if (likely(cpu_if->vgic_sre))
 550                 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
 551 }
 552
 553 void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu)
 554 {
 555         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 556
 557         if (likely(cpu_if->vgic_sre))
 558                 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
 559 }
 560
 561 void vgic_v3_put(struct kvm_vcpu *vcpu)
 562 {
 563         vgic_v3_vmcr_sync(vcpu);
 564 }