2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/irqchip/arm-gic.h>
18 #include <linux/kvm.h>
19 #include <linux/kvm_host.h>
20 #include <kvm/arm_vgic.h>
21 #include <asm/kvm_mmu.h>
25 static inline void vgic_v2_write_lr(int lr, u32 val)
27 void __iomem *base = kvm_vgic_global_state.vctrl_base;
29 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
32 void vgic_v2_init_lrs(void)
36 for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
37 vgic_v2_write_lr(i, 0);
40 void vgic_v2_set_npie(struct kvm_vcpu *vcpu)
42 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
44 cpuif->vgic_hcr |= GICH_HCR_NPIE;
47 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
49 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
51 cpuif->vgic_hcr |= GICH_HCR_UIE;
54 static bool lr_signals_eoi_mi(u32 lr_val)
56 return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
57 !(lr_val & GICH_LR_HW);
61 * transfer the content of the LRs back into the corresponding ap_list:
62 * - active bit is transferred as is
64 * - transferred as is in case of edge sensitive IRQs
65 * - set to the line-level (resample time) for level sensitive IRQs
67 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
69 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
70 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
73 cpuif->vgic_hcr &= ~(GICH_HCR_UIE | GICH_HCR_NPIE);
75 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
76 u32 val = cpuif->vgic_lr[lr];
77 u32 intid = val & GICH_LR_VIRTUALID;
80 /* Notify fds when the guest EOI'ed a level-triggered SPI */
81 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
82 kvm_notify_acked_irq(vcpu->kvm, 0,
83 intid - VGIC_NR_PRIVATE_IRQS);
85 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
87 spin_lock(&irq->irq_lock);
89 /* Always preserve the active bit */
90 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
92 /* Edge is the only case where we preserve the pending bit */
93 if (irq->config == VGIC_CONFIG_EDGE &&
94 (val & GICH_LR_PENDING_BIT)) {
95 irq->pending_latch = true;
97 if (vgic_irq_is_sgi(intid)) {
98 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
100 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
101 irq->source |= (1 << cpuid);
106 * Clear soft pending state when level irqs have been acked.
107 * Always regenerate the pending state.
109 if (irq->config == VGIC_CONFIG_LEVEL) {
110 if (!(val & GICH_LR_PENDING_BIT))
111 irq->pending_latch = false;
114 spin_unlock(&irq->irq_lock);
115 vgic_put_irq(vcpu->kvm, irq);
118 vgic_cpu->used_lrs = 0;
122 * Populates the particular LR with the state of a given IRQ:
123 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
124 * - for a level sensitive IRQ the pending state value is unchanged;
125 * it is dictated directly by the input level
127 * If @irq describes an SGI with multiple sources, we choose the
128 * lowest-numbered source VCPU and clear that bit in the source bitmap.
130 * The irq_lock must be held by the caller.
132 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
134 u32 val = irq->intid;
136 if (irq_is_pending(irq)) {
137 val |= GICH_LR_PENDING_BIT;
139 if (irq->config == VGIC_CONFIG_EDGE)
140 irq->pending_latch = false;
142 if (vgic_irq_is_sgi(irq->intid)) {
143 u32 src = ffs(irq->source);
145 if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
149 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
150 irq->source &= ~(1 << (src - 1));
152 irq->pending_latch = true;
157 val |= GICH_LR_ACTIVE_BIT;
161 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
163 * Never set pending+active on a HW interrupt, as the
164 * pending state is kept at the physical distributor
167 if (irq->active && irq_is_pending(irq))
168 val &= ~GICH_LR_PENDING_BIT;
170 if (irq->config == VGIC_CONFIG_LEVEL)
174 /* The GICv2 LR only holds five bits of priority. */
175 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
177 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
180 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
182 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
185 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
187 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
190 vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
191 GICH_VMCR_ENABLE_GRP0_MASK;
192 vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
193 GICH_VMCR_ENABLE_GRP1_MASK;
194 vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
195 GICH_VMCR_ACK_CTL_MASK;
196 vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
197 GICH_VMCR_FIQ_EN_MASK;
198 vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
200 vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
201 GICH_VMCR_EOI_MODE_MASK;
202 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
203 GICH_VMCR_ALIAS_BINPOINT_MASK;
204 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
205 GICH_VMCR_BINPOINT_MASK;
206 vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
207 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
209 cpu_if->vgic_vmcr = vmcr;
212 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
214 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
217 vmcr = cpu_if->vgic_vmcr;
219 vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
220 GICH_VMCR_ENABLE_GRP0_SHIFT;
221 vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
222 GICH_VMCR_ENABLE_GRP1_SHIFT;
223 vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
224 GICH_VMCR_ACK_CTL_SHIFT;
225 vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
226 GICH_VMCR_FIQ_EN_SHIFT;
227 vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
228 GICH_VMCR_CBPR_SHIFT;
229 vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
230 GICH_VMCR_EOI_MODE_SHIFT;
232 vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
233 GICH_VMCR_ALIAS_BINPOINT_SHIFT;
234 vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
235 GICH_VMCR_BINPOINT_SHIFT;
236 vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
237 GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
240 void vgic_v2_enable(struct kvm_vcpu *vcpu)
243 * By forcing VMCR to zero, the GIC will restore the binary
244 * points to their reset values. Anything else resets to zero
247 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
248 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
250 /* Get the show on the road... */
251 vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
254 /* check for overlapping regions and for regions crossing the end of memory */
255 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
257 if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
259 if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
262 if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
264 if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
270 int vgic_v2_map_resources(struct kvm *kvm)
272 struct vgic_dist *dist = &kvm->arch.vgic;
278 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
279 IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
280 kvm_err("Need to set vgic cpu and dist addresses first\n");
285 if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
286 kvm_err("VGIC CPU and dist frames overlap\n");
292 * Initialize the vgic if this hasn't already been done on demand by
293 * accessing the vgic state from userspace.
295 ret = vgic_init(kvm);
297 kvm_err("Unable to initialize VGIC dynamic data structures\n");
301 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
303 kvm_err("Unable to register VGIC MMIO regions\n");
307 if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
308 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
309 kvm_vgic_global_state.vcpu_base,
310 KVM_VGIC_V2_CPU_SIZE, true);
312 kvm_err("Unable to remap VGIC CPU to VCPU\n");
323 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
326 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
327 * @node: pointer to the DT node
329 * Returns 0 if a GICv2 has been found, returns an error code otherwise
331 int vgic_v2_probe(const struct gic_kvm_info *info)
336 if (!info->vctrl.start) {
337 kvm_err("GICH not present in the firmware table\n");
341 if (!PAGE_ALIGNED(info->vcpu.start) ||
342 !PAGE_ALIGNED(resource_size(&info->vcpu))) {
343 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
344 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
345 resource_size(&info->vcpu));
346 if (!kvm_vgic_global_state.vcpu_base_va) {
347 kvm_err("Cannot ioremap GICV\n");
351 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
352 kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
355 kvm_err("Cannot map GICV into hyp\n");
359 static_branch_enable(&vgic_v2_cpuif_trap);
362 kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
363 resource_size(&info->vctrl));
364 if (!kvm_vgic_global_state.vctrl_base) {
365 kvm_err("Cannot ioremap GICH\n");
370 vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
371 kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
373 ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
374 kvm_vgic_global_state.vctrl_base +
375 resource_size(&info->vctrl),
378 kvm_err("Cannot map VCTRL into hyp\n");
382 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
384 kvm_err("Cannot register GICv2 KVM device\n");
388 kvm_vgic_global_state.can_emulate_gicv2 = true;
389 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
390 kvm_vgic_global_state.type = VGIC_V2;
391 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
393 kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
397 if (kvm_vgic_global_state.vctrl_base)
398 iounmap(kvm_vgic_global_state.vctrl_base);
399 if (kvm_vgic_global_state.vcpu_base_va)
400 iounmap(kvm_vgic_global_state.vcpu_base_va);
405 void vgic_v2_load(struct kvm_vcpu *vcpu)
407 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
408 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
410 writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
413 void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu)
415 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
416 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
418 cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
421 void vgic_v2_put(struct kvm_vcpu *vcpu)
423 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
424 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
426 vgic_v2_vmcr_sync(vcpu);
427 cpu_if->vgic_apr = readl_relaxed(vgic->vctrl_base + GICH_APR);