virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 static inline void vgic_v2_write_lr(int lr, u32 val)
  26 {
  27         void __iomem *base = kvm_vgic_global_state.vctrl_base;
  28
  29         writel_relaxed(val, base + GICH_LR0 + (lr * 4));
  30 }
  31
  32 void vgic_v2_init_lrs(void)
  33 {
  34         int i;
  35
  36         for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
  37                 vgic_v2_write_lr(i, 0);
  38 }
  39
  40 void vgic_v2_set_npie(struct kvm_vcpu *vcpu)
  41 {
  42         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  43
  44         cpuif->vgic_hcr |= GICH_HCR_NPIE;
  45 }
  46
  47 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  48 {
  49         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  50
  51         cpuif->vgic_hcr |= GICH_HCR_UIE;
  52 }
  53
  54 static bool lr_signals_eoi_mi(u32 lr_val)
  55 {
  56         return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
  57                !(lr_val & GICH_LR_HW);
  58 }
  59
  60 /*
  61  * transfer the content of the LRs back into the corresponding ap_list:
  62  * - active bit is transferred as is
  63  * - pending bit is
  64  *   - transferred as is in case of edge sensitive IRQs
  65  *   - set to the line-level (resample time) for level sensitive IRQs
  66  */
  67 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  68 {
  69         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  70         struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
  71         int lr;
  72
  73         cpuif->vgic_hcr &= ~(GICH_HCR_UIE | GICH_HCR_NPIE);
  74
  75         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  76                 u32 val = cpuif->vgic_lr[lr];
  77                 u32 intid = val & GICH_LR_VIRTUALID;
  78                 struct vgic_irq *irq;
  79
  80                 /* Notify fds when the guest EOI'ed a level-triggered SPI */
  81                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  82                         kvm_notify_acked_irq(vcpu->kvm, 0,
  83                                              intid - VGIC_NR_PRIVATE_IRQS);
  84
  85                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  86
  87                 spin_lock(&irq->irq_lock);
  88
  89                 /* Always preserve the active bit */
  90                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
  91
  92                 /* Edge is the only case where we preserve the pending bit */
  93                 if (irq->config == VGIC_CONFIG_EDGE &&
  94                     (val & GICH_LR_PENDING_BIT)) {
  95                         irq->pending_latch = true;
  96
  97                         if (vgic_irq_is_sgi(intid)) {
  98                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  99
 100                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
 101                                 irq->source |= (1 << cpuid);
 102                         }
 103                 }
 104
 105                 /*
 106                  * Clear soft pending state when level irqs have been acked.
 107                  * Always regenerate the pending state.
 108                  */
 109                 if (irq->config == VGIC_CONFIG_LEVEL) {
 110                         if (!(val & GICH_LR_PENDING_BIT))
 111                                 irq->pending_latch = false;
 112                 }
 113
 114                 spin_unlock(&irq->irq_lock);
 115                 vgic_put_irq(vcpu->kvm, irq);
 116         }
 117
 118         vgic_cpu->used_lrs = 0;
 119 }
 120
 121 /*
 122  * Populates the particular LR with the state of a given IRQ:
 123  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 124  * - for a level sensitive IRQ the pending state value is unchanged;
 125  *   it is dictated directly by the input level
 126  *
 127  * If @irq describes an SGI with multiple sources, we choose the
 128  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 129  *
 130  * The irq_lock must be held by the caller.
 131  */
 132 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 133 {
 134         u32 val = irq->intid;
 135
 136         if (irq_is_pending(irq)) {
 137                 val |= GICH_LR_PENDING_BIT;
 138
 139                 if (irq->config == VGIC_CONFIG_EDGE)
 140                         irq->pending_latch = false;
 141
 142                 if (vgic_irq_is_sgi(irq->intid)) {
 143                         u32 src = ffs(irq->source);
 144
 145                         if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
 146                                            irq->intid))
 147                                 return;
 148
 149                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 150                         irq->source &= ~(1 << (src - 1));
 151                         if (irq->source)
 152                                 irq->pending_latch = true;
 153                 }
 154         }
 155
 156         if (irq->active)
 157                 val |= GICH_LR_ACTIVE_BIT;
 158
 159         if (irq->hw) {
 160                 val |= GICH_LR_HW;
 161                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 162                 /*
 163                  * Never set pending+active on a HW interrupt, as the
 164                  * pending state is kept at the physical distributor
 165                  * level.
 166                  */
 167                 if (irq->active && irq_is_pending(irq))
 168                         val &= ~GICH_LR_PENDING_BIT;
 169         } else {
 170                 if (irq->config == VGIC_CONFIG_LEVEL)
 171                         val |= GICH_LR_EOI;
 172         }
 173
 174         /* The GICv2 LR only holds five bits of priority. */
 175         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 176
 177         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 178 }
 179
 180 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 181 {
 182         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 183 }
 184
 185 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 186 {
 187         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 188         u32 vmcr;
 189
 190         vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
 191                 GICH_VMCR_ENABLE_GRP0_MASK;
 192         vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
 193                 GICH_VMCR_ENABLE_GRP1_MASK;
 194         vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
 195                 GICH_VMCR_ACK_CTL_MASK;
 196         vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
 197                 GICH_VMCR_FIQ_EN_MASK;
 198         vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
 199                 GICH_VMCR_CBPR_MASK;
 200         vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
 201                 GICH_VMCR_EOI_MODE_MASK;
 202         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 203                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 204         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 205                 GICH_VMCR_BINPOINT_MASK;
 206         vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
 207                  GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 208
 209         cpu_if->vgic_vmcr = vmcr;
 210 }
 211
 212 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 213 {
 214         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 215         u32 vmcr;
 216
 217         vmcr = cpu_if->vgic_vmcr;
 218
 219         vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
 220                 GICH_VMCR_ENABLE_GRP0_SHIFT;
 221         vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
 222                 GICH_VMCR_ENABLE_GRP1_SHIFT;
 223         vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
 224                 GICH_VMCR_ACK_CTL_SHIFT;
 225         vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
 226                 GICH_VMCR_FIQ_EN_SHIFT;
 227         vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
 228                 GICH_VMCR_CBPR_SHIFT;
 229         vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
 230                 GICH_VMCR_EOI_MODE_SHIFT;
 231
 232         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 233                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 234         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 235                         GICH_VMCR_BINPOINT_SHIFT;
 236         vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
 237                         GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
 238 }
 239
 240 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 241 {
 242         /*
 243          * By forcing VMCR to zero, the GIC will restore the binary
 244          * points to their reset values. Anything else resets to zero
 245          * anyway.
 246          */
 247         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 248         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 249
 250         /* Get the show on the road... */
 251         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 252 }
 253
 254 /* check for overlapping regions and for regions crossing the end of memory */
 255 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 256 {
 257         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 258                 return false;
 259         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 260                 return false;
 261
 262         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 263                 return true;
 264         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 265                 return true;
 266
 267         return false;
 268 }
 269
 270 int vgic_v2_map_resources(struct kvm *kvm)
 271 {
 272         struct vgic_dist *dist = &kvm->arch.vgic;
 273         int ret = 0;
 274
 275         if (vgic_ready(kvm))
 276                 goto out;
 277
 278         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 279             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 280                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 281                 ret = -ENXIO;
 282                 goto out;
 283         }
 284
 285         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 286                 kvm_err("VGIC CPU and dist frames overlap\n");
 287                 ret = -EINVAL;
 288                 goto out;
 289         }
 290
 291         /*
 292          * Initialize the vgic if this hasn't already been done on demand by
 293          * accessing the vgic state from userspace.
 294          */
 295         ret = vgic_init(kvm);
 296         if (ret) {
 297                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 298                 goto out;
 299         }
 300
 301         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 302         if (ret) {
 303                 kvm_err("Unable to register VGIC MMIO regions\n");
 304                 goto out;
 305         }
 306
 307         if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 308                 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 309                                             kvm_vgic_global_state.vcpu_base,
 310                                             KVM_VGIC_V2_CPU_SIZE, true);
 311                 if (ret) {
 312                         kvm_err("Unable to remap VGIC CPU to VCPU\n");
 313                         goto out;
 314                 }
 315         }
 316
 317         dist->ready = true;
 318
 319 out:
 320         return ret;
 321 }
 322
 323 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
 324
 325 /**
 326  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 327  * @node:       pointer to the DT node
 328  *
 329  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 330  */
 331 int vgic_v2_probe(const struct gic_kvm_info *info)
 332 {
 333         int ret;
 334         u32 vtr;
 335
 336         if (!info->vctrl.start) {
 337                 kvm_err("GICH not present in the firmware table\n");
 338                 return -ENXIO;
 339         }
 340
 341         if (!PAGE_ALIGNED(info->vcpu.start) ||
 342             !PAGE_ALIGNED(resource_size(&info->vcpu))) {
 343                 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 344                 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
 345                                                              resource_size(&info->vcpu));
 346                 if (!kvm_vgic_global_state.vcpu_base_va) {
 347                         kvm_err("Cannot ioremap GICV\n");
 348                         return -ENOMEM;
 349                 }
 350
 351                 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
 352                                              kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
 353                                              info->vcpu.start);
 354                 if (ret) {
 355                         kvm_err("Cannot map GICV into hyp\n");
 356                         goto out;
 357                 }
 358
 359                 static_branch_enable(&vgic_v2_cpuif_trap);
 360         }
 361
 362         kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
 363                                                    resource_size(&info->vctrl));
 364         if (!kvm_vgic_global_state.vctrl_base) {
 365                 kvm_err("Cannot ioremap GICH\n");
 366                 ret = -ENOMEM;
 367                 goto out;
 368         }
 369
 370         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 371         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 372
 373         ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
 374                                      kvm_vgic_global_state.vctrl_base +
 375                                          resource_size(&info->vctrl),
 376                                      info->vctrl.start);
 377         if (ret) {
 378                 kvm_err("Cannot map VCTRL into hyp\n");
 379                 goto out;
 380         }
 381
 382         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 383         if (ret) {
 384                 kvm_err("Cannot register GICv2 KVM device\n");
 385                 goto out;
 386         }
 387
 388         kvm_vgic_global_state.can_emulate_gicv2 = true;
 389         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 390         kvm_vgic_global_state.type = VGIC_V2;
 391         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 392
 393         kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
 394
 395         return 0;
 396 out:
 397         if (kvm_vgic_global_state.vctrl_base)
 398                 iounmap(kvm_vgic_global_state.vctrl_base);
 399         if (kvm_vgic_global_state.vcpu_base_va)
 400                 iounmap(kvm_vgic_global_state.vcpu_base_va);
 401
 402         return ret;
 403 }
 404
 405 void vgic_v2_load(struct kvm_vcpu *vcpu)
 406 {
 407         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 408         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 409
 410         writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
 411 }
 412
 413 void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu)
 414 {
 415         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 416         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 417
 418         cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
 419 }
 420
 421 void vgic_v2_put(struct kvm_vcpu *vcpu)
 422 {
 423         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 424         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 425
 426         vgic_v2_vmcr_sync(vcpu);
 427         cpu_if->vgic_apr = readl_relaxed(vgic->vctrl_base + GICH_APR);
 428 }