2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_vgic.h>
22 #include "vgic-mmio.h"
24 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
25 gpa_t addr, unsigned int len)
30 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
31 gpa_t addr, unsigned int len)
36 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
37 unsigned int len, unsigned long val)
43 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
44 * of the enabled bit, so there is only one function for both here.
46 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
47 gpa_t addr, unsigned int len)
49 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
53 /* Loop over all IRQs affected by this read */
54 for (i = 0; i < len * 8; i++) {
55 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
60 vgic_put_irq(vcpu->kvm, irq);
66 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
67 gpa_t addr, unsigned int len,
70 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
73 for_each_set_bit(i, &val, len * 8) {
74 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
76 spin_lock(&irq->irq_lock);
78 vgic_queue_irq_unlock(vcpu->kvm, irq);
80 vgic_put_irq(vcpu->kvm, irq);
84 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
85 gpa_t addr, unsigned int len,
88 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
91 for_each_set_bit(i, &val, len * 8) {
92 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
94 spin_lock(&irq->irq_lock);
98 spin_unlock(&irq->irq_lock);
99 vgic_put_irq(vcpu->kvm, irq);
103 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
104 gpa_t addr, unsigned int len)
106 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
110 /* Loop over all IRQs affected by this read */
111 for (i = 0; i < len * 8; i++) {
112 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
117 vgic_put_irq(vcpu->kvm, irq);
123 static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
125 return (vgic_irq_is_sgi(irq->intid) &&
126 vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2);
129 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
130 gpa_t addr, unsigned int len,
133 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
136 for_each_set_bit(i, &val, len * 8) {
137 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
139 /* GICD_ISPENDR0 SGI bits are WI */
140 if (is_vgic_v2_sgi(vcpu, irq)) {
141 vgic_put_irq(vcpu->kvm, irq);
145 spin_lock(&irq->irq_lock);
147 if (irq->config == VGIC_CONFIG_LEVEL)
148 irq->soft_pending = true;
150 vgic_queue_irq_unlock(vcpu->kvm, irq);
151 vgic_put_irq(vcpu->kvm, irq);
155 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
156 gpa_t addr, unsigned int len,
159 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
162 for_each_set_bit(i, &val, len * 8) {
163 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
165 /* GICD_ICPENDR0 SGI bits are WI */
166 if (is_vgic_v2_sgi(vcpu, irq)) {
167 vgic_put_irq(vcpu->kvm, irq);
171 spin_lock(&irq->irq_lock);
173 if (irq->config == VGIC_CONFIG_LEVEL) {
174 irq->soft_pending = false;
175 irq->pending = irq->line_level;
177 irq->pending = false;
180 spin_unlock(&irq->irq_lock);
181 vgic_put_irq(vcpu->kvm, irq);
185 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
186 gpa_t addr, unsigned int len)
188 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
192 /* Loop over all IRQs affected by this read */
193 for (i = 0; i < len * 8; i++) {
194 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
199 vgic_put_irq(vcpu->kvm, irq);
205 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
206 bool new_active_state)
208 struct kvm_vcpu *requester_vcpu;
209 spin_lock(&irq->irq_lock);
212 * The vcpu parameter here can mean multiple things depending on how
213 * this function is called; when handling a trap from the kernel it
214 * depends on the GIC version, and these functions are also called as
215 * part of save/restore from userspace.
217 * Therefore, we have to figure out the requester in a reliable way.
219 * When accessing VGIC state from user space, the requester_vcpu is
220 * NULL, which is fine, because we guarantee that no VCPUs are running
221 * when accessing VGIC state from user space so irq->vcpu->cpu is
224 requester_vcpu = kvm_arm_get_running_vcpu();
227 * If this virtual IRQ was written into a list register, we
228 * have to make sure the CPU that runs the VCPU thread has
229 * synced back the LR state to the struct vgic_irq.
231 * As long as the conditions below are true, we know the VCPU thread
232 * may be on its way back from the guest (we kicked the VCPU thread in
233 * vgic_change_active_prepare) and still has to sync back this IRQ,
234 * so we release and re-acquire the spin_lock to let the other thread
237 while (irq->vcpu && /* IRQ may have state in an LR somewhere */
238 irq->vcpu != requester_vcpu && /* Current thread is not the VCPU thread */
239 irq->vcpu->cpu != -1) /* VCPU thread is running */
240 cond_resched_lock(&irq->irq_lock);
242 irq->active = new_active_state;
243 if (new_active_state)
244 vgic_queue_irq_unlock(vcpu->kvm, irq);
246 spin_unlock(&irq->irq_lock);
250 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
251 * is not queued on some running VCPU's LRs, because then the change to the
252 * active state can be overwritten when the VCPU's state is synced coming back
255 * For shared interrupts, we have to stop all the VCPUs because interrupts can
256 * be migrated while we don't hold the IRQ locks and we don't want to be
257 * chasing moving targets.
259 * For private interrupts, we only have to make sure the single and only VCPU
260 * that can potentially queue the IRQ is stopped.
262 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
264 if (intid < VGIC_NR_PRIVATE_IRQS)
265 kvm_arm_halt_vcpu(vcpu);
267 kvm_arm_halt_guest(vcpu->kvm);
270 /* See vgic_change_active_prepare */
271 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
273 if (intid < VGIC_NR_PRIVATE_IRQS)
274 kvm_arm_resume_vcpu(vcpu);
276 kvm_arm_resume_guest(vcpu->kvm);
279 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
280 gpa_t addr, unsigned int len,
283 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
286 vgic_change_active_prepare(vcpu, intid);
287 for_each_set_bit(i, &val, len * 8) {
288 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
289 vgic_mmio_change_active(vcpu, irq, false);
290 vgic_put_irq(vcpu->kvm, irq);
292 vgic_change_active_finish(vcpu, intid);
295 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
296 gpa_t addr, unsigned int len,
299 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
302 vgic_change_active_prepare(vcpu, intid);
303 for_each_set_bit(i, &val, len * 8) {
304 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
305 vgic_mmio_change_active(vcpu, irq, true);
306 vgic_put_irq(vcpu->kvm, irq);
308 vgic_change_active_finish(vcpu, intid);
311 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
312 gpa_t addr, unsigned int len)
314 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
318 for (i = 0; i < len; i++) {
319 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
321 val |= (u64)irq->priority << (i * 8);
323 vgic_put_irq(vcpu->kvm, irq);
330 * We currently don't handle changing the priority of an interrupt that
331 * is already pending on a VCPU. If there is a need for this, we would
332 * need to make this VCPU exit and re-evaluate the priorities, potentially
333 * leading to this interrupt getting presented now to the guest (if it has
334 * been masked by the priority mask before).
336 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
337 gpa_t addr, unsigned int len,
340 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
343 for (i = 0; i < len; i++) {
344 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
346 spin_lock(&irq->irq_lock);
347 /* Narrow the priority range to what we actually support */
348 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
349 spin_unlock(&irq->irq_lock);
351 vgic_put_irq(vcpu->kvm, irq);
355 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
356 gpa_t addr, unsigned int len)
358 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
362 for (i = 0; i < len * 4; i++) {
363 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
365 if (irq->config == VGIC_CONFIG_EDGE)
366 value |= (2U << (i * 2));
368 vgic_put_irq(vcpu->kvm, irq);
374 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
375 gpa_t addr, unsigned int len,
378 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
381 for (i = 0; i < len * 4; i++) {
382 struct vgic_irq *irq;
385 * The configuration cannot be changed for SGIs in general,
386 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
387 * code relies on PPIs being level triggered, so we also
388 * make them read-only here.
390 if (intid + i < VGIC_NR_PRIVATE_IRQS)
393 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
394 spin_lock(&irq->irq_lock);
396 if (test_bit(i * 2 + 1, &val)) {
397 irq->config = VGIC_CONFIG_EDGE;
399 irq->config = VGIC_CONFIG_LEVEL;
400 irq->pending = irq->line_level | irq->soft_pending;
403 spin_unlock(&irq->irq_lock);
404 vgic_put_irq(vcpu->kvm, irq);
408 static int match_region(const void *key, const void *elt)
410 const unsigned int offset = (unsigned long)key;
411 const struct vgic_register_region *region = elt;
413 if (offset < region->reg_offset)
416 if (offset >= region->reg_offset + region->len)
422 /* Find the proper register handler entry given a certain address offset. */
423 static const struct vgic_register_region *
424 vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
427 return bsearch((void *)(uintptr_t)offset, region, nr_regions,
428 sizeof(region[0]), match_region);
432 * kvm_mmio_read_buf() returns a value in a format where it can be converted
433 * to a byte array and be directly observed as the guest wanted it to appear
434 * in memory if it had done the store itself, which is LE for the GIC, as the
435 * guest knows the GIC is always LE.
437 * We convert this value to the CPUs native format to deal with it as a data
440 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
442 unsigned long data = kvm_mmio_read_buf(val, len);
448 return le16_to_cpu(data);
450 return le32_to_cpu(data);
452 return le64_to_cpu(data);
457 * kvm_mmio_write_buf() expects a value in a format such that if converted to
458 * a byte array it is observed as the guest would see it if it could perform
459 * the load directly. Since the GIC is LE, and the guest knows this, the
460 * guest expects a value in little endian format.
462 * We convert the data value from the CPUs native format to LE so that the
463 * value is returned in the proper format.
465 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
472 data = cpu_to_le16(data);
475 data = cpu_to_le32(data);
478 data = cpu_to_le64(data);
481 kvm_mmio_write_buf(buf, len, data);
485 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
487 return container_of(dev, struct vgic_io_device, dev);
490 static bool check_region(const struct kvm *kvm,
491 const struct vgic_register_region *region,
494 int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
498 flags = VGIC_ACCESS_8bit;
501 flags = VGIC_ACCESS_32bit;
504 flags = VGIC_ACCESS_64bit;
510 if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
511 if (!region->bits_per_irq)
514 /* Do we access a non-allocated IRQ? */
515 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
521 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
522 gpa_t addr, int len, void *val)
524 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
525 const struct vgic_register_region *region;
526 unsigned long data = 0;
528 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
529 addr - iodev->base_addr);
530 if (!region || !check_region(vcpu->kvm, region, addr, len)) {
535 switch (iodev->iodev_type) {
537 data = region->read(vcpu, addr, len);
540 data = region->read(vcpu, addr, len);
543 data = region->read(iodev->redist_vcpu, addr, len);
546 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
550 vgic_data_host_to_mmio_bus(val, len, data);
554 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
555 gpa_t addr, int len, const void *val)
557 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
558 const struct vgic_register_region *region;
559 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
561 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
562 addr - iodev->base_addr);
563 if (!region || !check_region(vcpu->kvm, region, addr, len))
566 switch (iodev->iodev_type) {
568 region->write(vcpu, addr, len, data);
571 region->write(vcpu, addr, len, data);
574 region->write(iodev->redist_vcpu, addr, len, data);
577 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
584 struct kvm_io_device_ops kvm_io_gic_ops = {
585 .read = dispatch_mmio_read,
586 .write = dispatch_mmio_write,
589 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
592 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
598 len = vgic_v2_init_dist_iodev(io_device);
601 len = vgic_v3_init_dist_iodev(io_device);
607 io_device->base_addr = dist_base_address;
608 io_device->iodev_type = IODEV_DIST;
609 io_device->redist_vcpu = NULL;
611 mutex_lock(&kvm->slots_lock);
612 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
613 len, &io_device->dev);
614 mutex_unlock(&kvm->slots_lock);