virt/kvm/arm/vgic/vgic-mmio-v3.c

   1 /*
   2  * VGICv3 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic-v3.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include <asm/kvm_emulate.h>
  21 #include <asm/kvm_arm.h>
  22 #include <asm/kvm_mmu.h>
  23
  24 #include "vgic.h"
  25 #include "vgic-mmio.h"
  26
  27 /* extract @num bytes at @offset bytes offset in data */
  28 unsigned long extract_bytes(u64 data, unsigned int offset,
  29                             unsigned int num)
  30 {
  31         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
  32 }
  33
  34 /* allows updates of any half of a 64-bit register (or the whole thing) */
  35 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
  36                      unsigned long val)
  37 {
  38         int lower = (offset & 4) * 8;
  39         int upper = lower + 8 * len - 1;
  40
  41         reg &= ~GENMASK_ULL(upper, lower);
  42         val &= GENMASK_ULL(len * 8 - 1, 0);
  43
  44         return reg | ((u64)val << lower);
  45 }
  46
  47 bool vgic_has_its(struct kvm *kvm)
  48 {
  49         struct vgic_dist *dist = &kvm->arch.vgic;
  50
  51         if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
  52                 return false;
  53
  54         return dist->has_its;
  55 }
  56
  57 bool vgic_supports_direct_msis(struct kvm *kvm)
  58 {
  59         return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
  60 }
  61
  62 /*
  63  * The Revision field in the IIDR have the following meanings:
  64  *
  65  * Revision 2: Interrupt groups are guest-configurable and signaled using
  66  *             their configured groups.
  67  */
  68
  69 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
  70                                             gpa_t addr, unsigned int len)
  71 {
  72         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
  73         u32 value = 0;
  74
  75         switch (addr & 0x0c) {
  76         case GICD_CTLR:
  77                 if (vgic->enabled)
  78                         value |= GICD_CTLR_ENABLE_SS_G1;
  79                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
  80                 break;
  81         case GICD_TYPER:
  82                 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
  83                 value = (value >> 5) - 1;
  84                 if (vgic_has_its(vcpu->kvm)) {
  85                         value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
  86                         value |= GICD_TYPER_LPIS;
  87                 } else {
  88                         value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
  89                 }
  90                 break;
  91         case GICD_IIDR:
  92                 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
  93                         (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
  94                         (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
  95                 break;
  96         default:
  97                 return 0;
  98         }
  99
 100         return value;
 101 }
 102
 103 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 104                                     gpa_t addr, unsigned int len,
 105                                     unsigned long val)
 106 {
 107         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 108         bool was_enabled = dist->enabled;
 109
 110         switch (addr & 0x0c) {
 111         case GICD_CTLR:
 112                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 113
 114                 if (!was_enabled && dist->enabled)
 115                         vgic_kick_vcpus(vcpu->kvm);
 116                 break;
 117         case GICD_TYPER:
 118         case GICD_IIDR:
 119                 return;
 120         }
 121 }
 122
 123 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 124                                            gpa_t addr, unsigned int len,
 125                                            unsigned long val)
 126 {
 127         switch (addr & 0x0c) {
 128         case GICD_IIDR:
 129                 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
 130                         return -EINVAL;
 131         }
 132
 133         vgic_mmio_write_v3_misc(vcpu, addr, len, val);
 134         return 0;
 135 }
 136
 137 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
 138                                             gpa_t addr, unsigned int len)
 139 {
 140         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 141         struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 142         unsigned long ret = 0;
 143
 144         if (!irq)
 145                 return 0;
 146
 147         /* The upper word is RAZ for us. */
 148         if (!(addr & 4))
 149                 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
 150
 151         vgic_put_irq(vcpu->kvm, irq);
 152         return ret;
 153 }
 154
 155 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
 156                                     gpa_t addr, unsigned int len,
 157                                     unsigned long val)
 158 {
 159         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 160         struct vgic_irq *irq;
 161         unsigned long flags;
 162
 163         /* The upper word is WI for us since we don't implement Aff3. */
 164         if (addr & 4)
 165                 return;
 166
 167         irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 168
 169         if (!irq)
 170                 return;
 171
 172         spin_lock_irqsave(&irq->irq_lock, flags);
 173
 174         /* We only care about and preserve Aff0, Aff1 and Aff2. */
 175         irq->mpidr = val & GENMASK(23, 0);
 176         irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
 177
 178         spin_unlock_irqrestore(&irq->irq_lock, flags);
 179         vgic_put_irq(vcpu->kvm, irq);
 180 }
 181
 182 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
 183                                              gpa_t addr, unsigned int len)
 184 {
 185         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 186
 187         return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
 188 }
 189
 190
 191 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
 192                                      gpa_t addr, unsigned int len,
 193                                      unsigned long val)
 194 {
 195         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 196         bool was_enabled = vgic_cpu->lpis_enabled;
 197
 198         if (!vgic_has_its(vcpu->kvm))
 199                 return;
 200
 201         vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
 202
 203         if (!was_enabled && vgic_cpu->lpis_enabled)
 204                 vgic_enable_lpis(vcpu);
 205 }
 206
 207 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
 208                                               gpa_t addr, unsigned int len)
 209 {
 210         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
 211         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 212         struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
 213         int target_vcpu_id = vcpu->vcpu_id;
 214         gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
 215                         (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
 216         u64 value;
 217
 218         value = (u64)(mpidr & GENMASK(23, 0)) << 32;
 219         value |= ((target_vcpu_id & 0xffff) << 8);
 220
 221         if (addr == last_rdist_typer)
 222                 value |= GICR_TYPER_LAST;
 223         if (vgic_has_its(vcpu->kvm))
 224                 value |= GICR_TYPER_PLPIS;
 225
 226         return extract_bytes(value, addr & 7, len);
 227 }
 228
 229 static unsigned long vgic_uaccess_read_v3r_typer(struct kvm_vcpu *vcpu,
 230                                                  gpa_t addr, unsigned int len)
 231 {
 232         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
 233         int target_vcpu_id = vcpu->vcpu_id;
 234         u64 value;
 235
 236         value = (u64)(mpidr & GENMASK(23, 0)) << 32;
 237         value |= ((target_vcpu_id & 0xffff) << 8);
 238
 239         if (vgic_has_its(vcpu->kvm))
 240                 value |= GICR_TYPER_PLPIS;
 241
 242         /* reporting of the Last bit is not supported for userspace */
 243         return extract_bytes(value, addr & 7, len);
 244 }
 245
 246 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
 247                                              gpa_t addr, unsigned int len)
 248 {
 249         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 250 }
 251
 252 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
 253                                               gpa_t addr, unsigned int len)
 254 {
 255         switch (addr & 0xffff) {
 256         case GICD_PIDR2:
 257                 /* report a GICv3 compliant implementation */
 258                 return 0x3b;
 259         }
 260
 261         return 0;
 262 }
 263
 264 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
 265                                                   gpa_t addr, unsigned int len)
 266 {
 267         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 268         u32 value = 0;
 269         int i;
 270
 271         /*
 272          * pending state of interrupt is latched in pending_latch variable.
 273          * Userspace will save and restore pending state and line_level
 274          * separately.
 275          * Refer to Documentation/virtual/kvm/devices/arm-vgic-v3.txt
 276          * for handling of ISPENDR and ICPENDR.
 277          */
 278         for (i = 0; i < len * 8; i++) {
 279                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 280
 281                 if (irq->pending_latch)
 282                         value |= (1U << i);
 283
 284                 vgic_put_irq(vcpu->kvm, irq);
 285         }
 286
 287         return value;
 288 }
 289
 290 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
 291                                          gpa_t addr, unsigned int len,
 292                                          unsigned long val)
 293 {
 294         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 295         int i;
 296         unsigned long flags;
 297
 298         for (i = 0; i < len * 8; i++) {
 299                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 300
 301                 spin_lock_irqsave(&irq->irq_lock, flags);
 302                 if (test_bit(i, &val)) {
 303                         /*
 304                          * pending_latch is set irrespective of irq type
 305                          * (level or edge) to avoid dependency that VM should
 306                          * restore irq config before pending info.
 307                          */
 308                         irq->pending_latch = true;
 309                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 310                 } else {
 311                         irq->pending_latch = false;
 312                         spin_unlock_irqrestore(&irq->irq_lock, flags);
 313                 }
 314
 315                 vgic_put_irq(vcpu->kvm, irq);
 316         }
 317
 318         return 0;
 319 }
 320
 321 /* We want to avoid outer shareable. */
 322 u64 vgic_sanitise_shareability(u64 field)
 323 {
 324         switch (field) {
 325         case GIC_BASER_OuterShareable:
 326                 return GIC_BASER_InnerShareable;
 327         default:
 328                 return field;
 329         }
 330 }
 331
 332 /* Avoid any inner non-cacheable mapping. */
 333 u64 vgic_sanitise_inner_cacheability(u64 field)
 334 {
 335         switch (field) {
 336         case GIC_BASER_CACHE_nCnB:
 337         case GIC_BASER_CACHE_nC:
 338                 return GIC_BASER_CACHE_RaWb;
 339         default:
 340                 return field;
 341         }
 342 }
 343
 344 /* Non-cacheable or same-as-inner are OK. */
 345 u64 vgic_sanitise_outer_cacheability(u64 field)
 346 {
 347         switch (field) {
 348         case GIC_BASER_CACHE_SameAsInner:
 349         case GIC_BASER_CACHE_nC:
 350                 return field;
 351         default:
 352                 return GIC_BASER_CACHE_nC;
 353         }
 354 }
 355
 356 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
 357                         u64 (*sanitise_fn)(u64))
 358 {
 359         u64 field = (reg & field_mask) >> field_shift;
 360
 361         field = sanitise_fn(field) << field_shift;
 362         return (reg & ~field_mask) | field;
 363 }
 364
 365 #define PROPBASER_RES0_MASK                                             \
 366         (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
 367 #define PENDBASER_RES0_MASK                                             \
 368         (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) |      \
 369          GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
 370
 371 static u64 vgic_sanitise_pendbaser(u64 reg)
 372 {
 373         reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
 374                                   GICR_PENDBASER_SHAREABILITY_SHIFT,
 375                                   vgic_sanitise_shareability);
 376         reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
 377                                   GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
 378                                   vgic_sanitise_inner_cacheability);
 379         reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
 380                                   GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
 381                                   vgic_sanitise_outer_cacheability);
 382
 383         reg &= ~PENDBASER_RES0_MASK;
 384         reg &= ~GENMASK_ULL(51, 48);
 385
 386         return reg;
 387 }
 388
 389 static u64 vgic_sanitise_propbaser(u64 reg)
 390 {
 391         reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
 392                                   GICR_PROPBASER_SHAREABILITY_SHIFT,
 393                                   vgic_sanitise_shareability);
 394         reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
 395                                   GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
 396                                   vgic_sanitise_inner_cacheability);
 397         reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
 398                                   GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
 399                                   vgic_sanitise_outer_cacheability);
 400
 401         reg &= ~PROPBASER_RES0_MASK;
 402         reg &= ~GENMASK_ULL(51, 48);
 403         return reg;
 404 }
 405
 406 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
 407                                              gpa_t addr, unsigned int len)
 408 {
 409         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 410
 411         return extract_bytes(dist->propbaser, addr & 7, len);
 412 }
 413
 414 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
 415                                      gpa_t addr, unsigned int len,
 416                                      unsigned long val)
 417 {
 418         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 419         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 420         u64 old_propbaser, propbaser;
 421
 422         /* Storing a value with LPIs already enabled is undefined */
 423         if (vgic_cpu->lpis_enabled)
 424                 return;
 425
 426         do {
 427                 old_propbaser = READ_ONCE(dist->propbaser);
 428                 propbaser = old_propbaser;
 429                 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
 430                 propbaser = vgic_sanitise_propbaser(propbaser);
 431         } while (cmpxchg64(&dist->propbaser, old_propbaser,
 432                            propbaser) != old_propbaser);
 433 }
 434
 435 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
 436                                              gpa_t addr, unsigned int len)
 437 {
 438         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 439
 440         return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
 441 }
 442
 443 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
 444                                      gpa_t addr, unsigned int len,
 445                                      unsigned long val)
 446 {
 447         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 448         u64 old_pendbaser, pendbaser;
 449
 450         /* Storing a value with LPIs already enabled is undefined */
 451         if (vgic_cpu->lpis_enabled)
 452                 return;
 453
 454         do {
 455                 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
 456                 pendbaser = old_pendbaser;
 457                 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
 458                 pendbaser = vgic_sanitise_pendbaser(pendbaser);
 459         } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
 460                            pendbaser) != old_pendbaser);
 461 }
 462
 463 /*
 464  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 465  * redistributors, while SPIs are covered by registers in the distributor
 466  * block. Trying to set private IRQs in this block gets ignored.
 467  * We take some special care here to fix the calculation of the register
 468  * offset.
 469  */
 470 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
 471         {                                                               \
 472                 .reg_offset = off,                                      \
 473                 .bits_per_irq = bpi,                                    \
 474                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
 475                 .access_flags = acc,                                    \
 476                 .read = vgic_mmio_read_raz,                             \
 477                 .write = vgic_mmio_write_wi,                            \
 478         }, {                                                            \
 479                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
 480                 .bits_per_irq = bpi,                                    \
 481                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
 482                 .access_flags = acc,                                    \
 483                 .read = rd,                                             \
 484                 .write = wr,                                            \
 485                 .uaccess_read = ur,                                     \
 486                 .uaccess_write = uw,                                    \
 487         }
 488
 489 static const struct vgic_register_region vgic_v3_dist_registers[] = {
 490         REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
 491                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
 492                 NULL, vgic_mmio_uaccess_write_v3_misc,
 493                 16, VGIC_ACCESS_32bit),
 494         REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
 495                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
 496                 VGIC_ACCESS_32bit),
 497         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
 498                 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
 499                 VGIC_ACCESS_32bit),
 500         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
 501                 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
 502                 VGIC_ACCESS_32bit),
 503         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
 504                 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
 505                 VGIC_ACCESS_32bit),
 506         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 507                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 508                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
 509                 VGIC_ACCESS_32bit),
 510         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 511                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 512                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
 513                 VGIC_ACCESS_32bit),
 514         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
 515                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 516                 NULL, vgic_mmio_uaccess_write_sactive, 1,
 517                 VGIC_ACCESS_32bit),
 518         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
 519                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 520                 NULL, vgic_mmio_uaccess_write_cactive,
 521                 1, VGIC_ACCESS_32bit),
 522         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
 523                 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
 524                 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 525         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
 526                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
 527                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 528         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
 529                 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
 530                 VGIC_ACCESS_32bit),
 531         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
 532                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
 533                 VGIC_ACCESS_32bit),
 534         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
 535                 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
 536                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 537         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
 538                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 539                 VGIC_ACCESS_32bit),
 540 };
 541
 542 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
 543         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
 544                 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
 545                 VGIC_ACCESS_32bit),
 546         REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
 547                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 548                 VGIC_ACCESS_32bit),
 549         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
 550                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
 551                 VGIC_ACCESS_32bit),
 552         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER,
 553                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi,
 554                 vgic_uaccess_read_v3r_typer, vgic_mmio_uaccess_write_wi, 8,
 555                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 556         REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
 557                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 558                 VGIC_ACCESS_32bit),
 559         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
 560                 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
 561                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 562         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
 563                 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
 564                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 565         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
 566                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 567                 VGIC_ACCESS_32bit),
 568 };
 569
 570 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
 571         REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
 572                 vgic_mmio_read_group, vgic_mmio_write_group, 4,
 573                 VGIC_ACCESS_32bit),
 574         REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
 575                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
 576                 VGIC_ACCESS_32bit),
 577         REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
 578                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
 579                 VGIC_ACCESS_32bit),
 580         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISPENDR0,
 581                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 582                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
 583                 VGIC_ACCESS_32bit),
 584         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICPENDR0,
 585                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 586                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
 587                 VGIC_ACCESS_32bit),
 588         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ISACTIVER0,
 589                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 590                 NULL, vgic_mmio_uaccess_write_sactive,
 591                 4, VGIC_ACCESS_32bit),
 592         REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_ICACTIVER0,
 593                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 594                 NULL, vgic_mmio_uaccess_write_cactive,
 595                 4, VGIC_ACCESS_32bit),
 596         REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
 597                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
 598                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 599         REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
 600                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
 601                 VGIC_ACCESS_32bit),
 602         REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
 603                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 604                 VGIC_ACCESS_32bit),
 605         REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
 606                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 607                 VGIC_ACCESS_32bit),
 608 };
 609
 610 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
 611 {
 612         dev->regions = vgic_v3_dist_registers;
 613         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 614
 615         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 616
 617         return SZ_64K;
 618 }
 619
 620 /**
 621  * vgic_register_redist_iodev - register a single redist iodev
 622  * @vcpu:    The VCPU to which the redistributor belongs
 623  *
 624  * Register a KVM iodev for this VCPU's redistributor using the address
 625  * provided.
 626  *
 627  * Return 0 on success, -ERRNO otherwise.
 628  */
 629 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
 630 {
 631         struct kvm *kvm = vcpu->kvm;
 632         struct vgic_dist *vgic = &kvm->arch.vgic;
 633         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 634         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 635         struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
 636         struct vgic_redist_region *rdreg;
 637         gpa_t rd_base, sgi_base;
 638         int ret;
 639
 640         if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
 641                 return 0;
 642
 643         /*
 644          * We may be creating VCPUs before having set the base address for the
 645          * redistributor region, in which case we will come back to this
 646          * function for all VCPUs when the base address is set.  Just return
 647          * without doing any work for now.
 648          */
 649         rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
 650         if (!rdreg)
 651                 return 0;
 652
 653         if (!vgic_v3_check_base(kvm))
 654                 return -EINVAL;
 655
 656         vgic_cpu->rdreg = rdreg;
 657
 658         rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
 659         sgi_base = rd_base + SZ_64K;
 660
 661         kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
 662         rd_dev->base_addr = rd_base;
 663         rd_dev->iodev_type = IODEV_REDIST;
 664         rd_dev->regions = vgic_v3_rdbase_registers;
 665         rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
 666         rd_dev->redist_vcpu = vcpu;
 667
 668         mutex_lock(&kvm->slots_lock);
 669         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
 670                                       SZ_64K, &rd_dev->dev);
 671         mutex_unlock(&kvm->slots_lock);
 672
 673         if (ret)
 674                 return ret;
 675
 676         kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
 677         sgi_dev->base_addr = sgi_base;
 678         sgi_dev->iodev_type = IODEV_REDIST;
 679         sgi_dev->regions = vgic_v3_sgibase_registers;
 680         sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
 681         sgi_dev->redist_vcpu = vcpu;
 682
 683         mutex_lock(&kvm->slots_lock);
 684         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
 685                                       SZ_64K, &sgi_dev->dev);
 686         if (ret) {
 687                 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 688                                           &rd_dev->dev);
 689                 goto out;
 690         }
 691
 692         rdreg->free_index++;
 693 out:
 694         mutex_unlock(&kvm->slots_lock);
 695         return ret;
 696 }
 697
 698 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
 699 {
 700         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 701         struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
 702
 703         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
 704         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &sgi_dev->dev);
 705 }
 706
 707 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
 708 {
 709         struct kvm_vcpu *vcpu;
 710         int c, ret = 0;
 711
 712         kvm_for_each_vcpu(c, vcpu, kvm) {
 713                 ret = vgic_register_redist_iodev(vcpu);
 714                 if (ret)
 715                         break;
 716         }
 717
 718         if (ret) {
 719                 /* The current c failed, so we start with the previous one. */
 720                 mutex_lock(&kvm->slots_lock);
 721                 for (c--; c >= 0; c--) {
 722                         vcpu = kvm_get_vcpu(kvm, c);
 723                         vgic_unregister_redist_iodev(vcpu);
 724                 }
 725                 mutex_unlock(&kvm->slots_lock);
 726         }
 727
 728         return ret;
 729 }
 730
 731 /**
 732  * vgic_v3_insert_redist_region - Insert a new redistributor region
 733  *
 734  * Performs various checks before inserting the rdist region in the list.
 735  * Those tests depend on whether the size of the rdist region is known
 736  * (ie. count != 0). The list is sorted by rdist region index.
 737  *
 738  * @kvm: kvm handle
 739  * @index: redist region index
 740  * @base: base of the new rdist region
 741  * @count: number of redistributors the region is made of (0 in the old style
 742  * single region, whose size is induced from the number of vcpus)
 743  *
 744  * Return 0 on success, < 0 otherwise
 745  */
 746 static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
 747                                         gpa_t base, uint32_t count)
 748 {
 749         struct vgic_dist *d = &kvm->arch.vgic;
 750         struct vgic_redist_region *rdreg;
 751         struct list_head *rd_regions = &d->rd_regions;
 752         size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
 753         int ret;
 754
 755         /* single rdist region already set ?*/
 756         if (!count && !list_empty(rd_regions))
 757                 return -EINVAL;
 758
 759         /* cross the end of memory ? */
 760         if (base + size < base)
 761                 return -EINVAL;
 762
 763         if (list_empty(rd_regions)) {
 764                 if (index != 0)
 765                         return -EINVAL;
 766         } else {
 767                 rdreg = list_last_entry(rd_regions,
 768                                         struct vgic_redist_region, list);
 769                 if (index != rdreg->index + 1)
 770                         return -EINVAL;
 771
 772                 /* Cannot add an explicitly sized regions after legacy region */
 773                 if (!rdreg->count)
 774                         return -EINVAL;
 775         }
 776
 777         /*
 778          * For legacy single-region redistributor regions (!count),
 779          * check that the redistributor region does not overlap with the
 780          * distributor's address space.
 781          */
 782         if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 783                 vgic_dist_overlap(kvm, base, size))
 784                 return -EINVAL;
 785
 786         /* collision with any other rdist region? */
 787         if (vgic_v3_rdist_overlap(kvm, base, size))
 788                 return -EINVAL;
 789
 790         rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
 791         if (!rdreg)
 792                 return -ENOMEM;
 793
 794         rdreg->base = VGIC_ADDR_UNDEF;
 795
 796         ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
 797         if (ret)
 798                 goto free;
 799
 800         rdreg->base = base;
 801         rdreg->count = count;
 802         rdreg->free_index = 0;
 803         rdreg->index = index;
 804
 805         list_add_tail(&rdreg->list, rd_regions);
 806         return 0;
 807 free:
 808         kfree(rdreg);
 809         return ret;
 810 }
 811
 812 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
 813 {
 814         int ret;
 815
 816         ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
 817         if (ret)
 818                 return ret;
 819
 820         /*
 821          * Register iodevs for each existing VCPU.  Adding more VCPUs
 822          * afterwards will register the iodevs when needed.
 823          */
 824         ret = vgic_register_all_redist_iodevs(kvm);
 825         if (ret)
 826                 return ret;
 827
 828         return 0;
 829 }
 830
 831 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 832 {
 833         const struct vgic_register_region *region;
 834         struct vgic_io_device iodev;
 835         struct vgic_reg_attr reg_attr;
 836         struct kvm_vcpu *vcpu;
 837         gpa_t addr;
 838         int ret;
 839
 840         ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
 841         if (ret)
 842                 return ret;
 843
 844         vcpu = reg_attr.vcpu;
 845         addr = reg_attr.addr;
 846
 847         switch (attr->group) {
 848         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
 849                 iodev.regions = vgic_v3_dist_registers;
 850                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 851                 iodev.base_addr = 0;
 852                 break;
 853         case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
 854                 iodev.regions = vgic_v3_rdbase_registers;
 855                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
 856                 iodev.base_addr = 0;
 857                 break;
 858         }
 859         case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
 860                 u64 reg, id;
 861
 862                 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
 863                 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, &reg);
 864         }
 865         default:
 866                 return -ENXIO;
 867         }
 868
 869         /* We only support aligned 32-bit accesses. */
 870         if (addr & 3)
 871                 return -ENXIO;
 872
 873         region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
 874         if (!region)
 875                 return -ENXIO;
 876
 877         return 0;
 878 }
 879 /*
 880  * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
 881  * generation register ICC_SGI1R_EL1) with a given VCPU.
 882  * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
 883  * return -1.
 884  */
 885 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
 886 {
 887         unsigned long affinity;
 888         int level0;
 889
 890         /*
 891          * Split the current VCPU's MPIDR into affinity level 0 and the
 892          * rest as this is what we have to compare against.
 893          */
 894         affinity = kvm_vcpu_get_mpidr_aff(vcpu);
 895         level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
 896         affinity &= ~MPIDR_LEVEL_MASK;
 897
 898         /* bail out if the upper three levels don't match */
 899         if (sgi_aff != affinity)
 900                 return -1;
 901
 902         /* Is this VCPU's bit set in the mask ? */
 903         if (!(sgi_cpu_mask & BIT(level0)))
 904                 return -1;
 905
 906         return level0;
 907 }
 908
 909 /*
 910  * The ICC_SGI* registers encode the affinity differently from the MPIDR,
 911  * so provide a wrapper to use the existing defines to isolate a certain
 912  * affinity level.
 913  */
 914 #define SGI_AFFINITY_LEVEL(reg, level) \
 915         ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
 916         >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
 917
 918 /**
 919  * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
 920  * @vcpu: The VCPU requesting a SGI
 921  * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
 922  * @allow_group1: Does the sysreg access allow generation of G1 SGIs
 923  *
 924  * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
 925  * This will trap in sys_regs.c and call this function.
 926  * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
 927  * target processors as well as a bitmask of 16 Aff0 CPUs.
 928  * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
 929  * check for matching ones. If this bit is set, we signal all, but not the
 930  * calling VCPU.
 931  */
 932 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
 933 {
 934         struct kvm *kvm = vcpu->kvm;
 935         struct kvm_vcpu *c_vcpu;
 936         u16 target_cpus;
 937         u64 mpidr;
 938         int sgi, c;
 939         int vcpu_id = vcpu->vcpu_id;
 940         bool broadcast;
 941         unsigned long flags;
 942
 943         sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
 944         broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
 945         target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
 946         mpidr = SGI_AFFINITY_LEVEL(reg, 3);
 947         mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
 948         mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
 949
 950         /*
 951          * We iterate over all VCPUs to find the MPIDRs matching the request.
 952          * If we have handled one CPU, we clear its bit to detect early
 953          * if we are already finished. This avoids iterating through all
 954          * VCPUs when most of the times we just signal a single VCPU.
 955          */
 956         kvm_for_each_vcpu(c, c_vcpu, kvm) {
 957                 struct vgic_irq *irq;
 958
 959                 /* Exit early if we have dealt with all requested CPUs */
 960                 if (!broadcast && target_cpus == 0)
 961                         break;
 962
 963                 /* Don't signal the calling VCPU */
 964                 if (broadcast && c == vcpu_id)
 965                         continue;
 966
 967                 if (!broadcast) {
 968                         int level0;
 969
 970                         level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
 971                         if (level0 == -1)
 972                                 continue;
 973
 974                         /* remove this matching VCPU from the mask */
 975                         target_cpus &= ~BIT(level0);
 976                 }
 977
 978                 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
 979
 980                 spin_lock_irqsave(&irq->irq_lock, flags);
 981
 982                 /*
 983                  * An access targetting Group0 SGIs can only generate
 984                  * those, while an access targetting Group1 SGIs can
 985                  * generate interrupts of either group.
 986                  */
 987                 if (!irq->group || allow_group1) {
 988                         irq->pending_latch = true;
 989                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 990                 } else {
 991                         spin_unlock_irqrestore(&irq->irq_lock, flags);
 992                 }
 993
 994                 vgic_put_irq(vcpu->kvm, irq);
 995         }
 996 }
 997
 998 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 999                          int offset, u32 *val)
1000 {
1001         struct vgic_io_device dev = {
1002                 .regions = vgic_v3_dist_registers,
1003                 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
1004         };
1005
1006         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
1007 }
1008
1009 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1010                            int offset, u32 *val)
1011 {
1012         struct vgic_io_device rd_dev = {
1013                 .regions = vgic_v3_rdbase_registers,
1014                 .nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
1015         };
1016
1017         struct vgic_io_device sgi_dev = {
1018                 .regions = vgic_v3_sgibase_registers,
1019                 .nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
1020         };
1021
1022         /* SGI_base is the next 64K frame after RD_base */
1023         if (offset >= SZ_64K)
1024                 return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
1025                                     val);
1026         else
1027                 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
1028 }
1029
1030 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1031                                     u32 intid, u64 *val)
1032 {
1033         if (intid % 32)
1034                 return -EINVAL;
1035
1036         if (is_write)
1037                 vgic_write_irq_line_level_info(vcpu, intid, *val);
1038         else
1039                 *val = vgic_read_irq_line_level_info(vcpu, intid);
1040
1041         return 0;
1042 }