4 * Copyright (C) 2015 ARM Ltd.
5 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 #include <linux/kvm_host.h>
17 #include <kvm/arm_vgic.h>
18 #include <linux/uaccess.h>
19 #include <asm/kvm_mmu.h>
20 #include <asm/cputype.h>
25 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
26 phys_addr_t addr, phys_addr_t alignment)
28 if (addr & ~KVM_PHYS_MASK)
31 if (!IS_ALIGNED(addr, alignment))
34 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
40 static int vgic_check_type(struct kvm *kvm, int type_needed)
42 if (kvm->arch.vgic.vgic_model != type_needed)
49 * kvm_vgic_addr - set or get vgic VM base addresses
50 * @kvm: pointer to the vm struct
51 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
52 * @addr: pointer to address value
53 * @write: if true set the address in the VM address space, if false read the
56 * Set or get the vgic base addresses for the distributor and the virtual CPU
57 * interface in the VM physical address space. These addresses are properties
58 * of the emulated core/SoC and therefore user space initially knows this
60 * Check them for sanity (alignment, double assignment). We can't check for
61 * overlapping regions in case of a virtual GICv3 here, since we don't know
62 * the number of VCPUs yet, so we defer this check to map_resources().
64 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
67 struct vgic_dist *vgic = &kvm->arch.vgic;
68 phys_addr_t *addr_ptr, alignment;
69 u64 undef_value = VGIC_ADDR_UNDEF;
71 mutex_lock(&kvm->lock);
73 case KVM_VGIC_V2_ADDR_TYPE_DIST:
74 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
75 addr_ptr = &vgic->vgic_dist_base;
78 case KVM_VGIC_V2_ADDR_TYPE_CPU:
79 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
80 addr_ptr = &vgic->vgic_cpu_base;
83 case KVM_VGIC_V3_ADDR_TYPE_DIST:
84 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
85 addr_ptr = &vgic->vgic_dist_base;
88 case KVM_VGIC_V3_ADDR_TYPE_REDIST: {
89 struct vgic_redist_region *rdreg;
91 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
95 r = vgic_v3_set_redist_base(kvm, 0, *addr, 0);
98 rdreg = list_first_entry_or_null(&vgic->rd_regions,
99 struct vgic_redist_region, list);
101 addr_ptr = &undef_value;
103 addr_ptr = &rdreg->base;
106 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
108 struct vgic_redist_region *rdreg;
111 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
115 index = *addr & KVM_VGIC_V3_RDIST_INDEX_MASK;
118 gpa_t base = *addr & KVM_VGIC_V3_RDIST_BASE_MASK;
119 u32 count = (*addr & KVM_VGIC_V3_RDIST_COUNT_MASK)
120 >> KVM_VGIC_V3_RDIST_COUNT_SHIFT;
121 u8 flags = (*addr & KVM_VGIC_V3_RDIST_FLAGS_MASK)
122 >> KVM_VGIC_V3_RDIST_FLAGS_SHIFT;
127 r = vgic_v3_set_redist_base(kvm, index,
132 rdreg = vgic_v3_rdist_region_from_index(kvm, index);
139 *addr |= rdreg->base;
140 *addr |= (u64)rdreg->count << KVM_VGIC_V3_RDIST_COUNT_SHIFT;
151 r = vgic_check_ioaddr(kvm, addr_ptr, *addr, alignment);
159 mutex_unlock(&kvm->lock);
163 static int vgic_set_common_attr(struct kvm_device *dev,
164 struct kvm_device_attr *attr)
168 switch (attr->group) {
169 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
170 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
172 unsigned long type = (unsigned long)attr->attr;
174 if (copy_from_user(&addr, uaddr, sizeof(addr)))
177 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
178 return (r == -ENODEV) ? -ENXIO : r;
180 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
181 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
185 if (get_user(val, uaddr))
190 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
191 * - at most 1024 interrupts
192 * - a multiple of 32 interrupts
194 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
195 val > VGIC_MAX_RESERVED ||
199 mutex_lock(&dev->kvm->lock);
201 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_spis)
204 dev->kvm->arch.vgic.nr_spis =
205 val - VGIC_NR_PRIVATE_IRQS;
207 mutex_unlock(&dev->kvm->lock);
211 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
212 switch (attr->attr) {
213 case KVM_DEV_ARM_VGIC_CTRL_INIT:
214 mutex_lock(&dev->kvm->lock);
215 r = vgic_init(dev->kvm);
216 mutex_unlock(&dev->kvm->lock);
226 static int vgic_get_common_attr(struct kvm_device *dev,
227 struct kvm_device_attr *attr)
231 switch (attr->group) {
232 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
233 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
235 unsigned long type = (unsigned long)attr->attr;
237 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
239 return (r == -ENODEV) ? -ENXIO : r;
241 if (copy_to_user(uaddr, &addr, sizeof(addr)))
245 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
246 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
248 r = put_user(dev->kvm->arch.vgic.nr_spis +
249 VGIC_NR_PRIVATE_IRQS, uaddr);
257 static int vgic_create(struct kvm_device *dev, u32 type)
259 return kvm_vgic_create(dev->kvm, type);
262 static void vgic_destroy(struct kvm_device *dev)
267 int kvm_register_vgic_device(unsigned long type)
272 case KVM_DEV_TYPE_ARM_VGIC_V2:
273 ret = kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
274 KVM_DEV_TYPE_ARM_VGIC_V2);
276 case KVM_DEV_TYPE_ARM_VGIC_V3:
277 ret = kvm_register_device_ops(&kvm_arm_vgic_v3_ops,
278 KVM_DEV_TYPE_ARM_VGIC_V3);
282 ret = kvm_vgic_register_its_device();
289 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
290 struct vgic_reg_attr *reg_attr)
294 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
295 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
297 if (cpuid >= atomic_read(&dev->kvm->online_vcpus))
300 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, cpuid);
301 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
306 /* unlocks vcpus from @vcpu_lock_idx and smaller */
307 static void unlock_vcpus(struct kvm *kvm, int vcpu_lock_idx)
309 struct kvm_vcpu *tmp_vcpu;
311 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
312 tmp_vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
313 mutex_unlock(&tmp_vcpu->mutex);
317 void unlock_all_vcpus(struct kvm *kvm)
319 unlock_vcpus(kvm, atomic_read(&kvm->online_vcpus) - 1);
322 /* Returns true if all vcpus were locked, false otherwise */
323 bool lock_all_vcpus(struct kvm *kvm)
325 struct kvm_vcpu *tmp_vcpu;
329 * Any time a vcpu is run, vcpu_load is called which tries to grab the
330 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
331 * that no other VCPUs are run and fiddle with the vgic state while we
334 kvm_for_each_vcpu(c, tmp_vcpu, kvm) {
335 if (!mutex_trylock(&tmp_vcpu->mutex)) {
336 unlock_vcpus(kvm, c - 1);
345 * vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
347 * @dev: kvm device handle
348 * @attr: kvm device attribute
349 * @reg: address the value is read or written
350 * @is_write: true if userspace is writing a register
352 static int vgic_v2_attr_regs_access(struct kvm_device *dev,
353 struct kvm_device_attr *attr,
354 u32 *reg, bool is_write)
356 struct vgic_reg_attr reg_attr;
358 struct kvm_vcpu *vcpu;
361 ret = vgic_v2_parse_attr(dev, attr, ®_attr);
365 vcpu = reg_attr.vcpu;
366 addr = reg_attr.addr;
368 mutex_lock(&dev->kvm->lock);
370 ret = vgic_init(dev->kvm);
374 if (!lock_all_vcpus(dev->kvm)) {
379 switch (attr->group) {
380 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
381 ret = vgic_v2_cpuif_uaccess(vcpu, is_write, addr, reg);
383 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
384 ret = vgic_v2_dist_uaccess(vcpu, is_write, addr, reg);
391 unlock_all_vcpus(dev->kvm);
393 mutex_unlock(&dev->kvm->lock);
397 static int vgic_v2_set_attr(struct kvm_device *dev,
398 struct kvm_device_attr *attr)
402 ret = vgic_set_common_attr(dev, attr);
406 switch (attr->group) {
407 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
408 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
409 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
412 if (get_user(reg, uaddr))
415 return vgic_v2_attr_regs_access(dev, attr, ®, true);
422 static int vgic_v2_get_attr(struct kvm_device *dev,
423 struct kvm_device_attr *attr)
427 ret = vgic_get_common_attr(dev, attr);
431 switch (attr->group) {
432 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
433 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
434 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
437 ret = vgic_v2_attr_regs_access(dev, attr, ®, false);
440 return put_user(reg, uaddr);
447 static int vgic_v2_has_attr(struct kvm_device *dev,
448 struct kvm_device_attr *attr)
450 switch (attr->group) {
451 case KVM_DEV_ARM_VGIC_GRP_ADDR:
452 switch (attr->attr) {
453 case KVM_VGIC_V2_ADDR_TYPE_DIST:
454 case KVM_VGIC_V2_ADDR_TYPE_CPU:
458 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
459 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
460 return vgic_v2_has_attr_regs(dev, attr);
461 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
463 case KVM_DEV_ARM_VGIC_GRP_CTRL:
464 switch (attr->attr) {
465 case KVM_DEV_ARM_VGIC_CTRL_INIT:
472 struct kvm_device_ops kvm_arm_vgic_v2_ops = {
473 .name = "kvm-arm-vgic-v2",
474 .create = vgic_create,
475 .destroy = vgic_destroy,
476 .set_attr = vgic_v2_set_attr,
477 .get_attr = vgic_v2_get_attr,
478 .has_attr = vgic_v2_has_attr,
481 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
482 struct vgic_reg_attr *reg_attr)
484 unsigned long vgic_mpidr, mpidr_reg;
487 * For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
488 * attr might not hold MPIDR. Hence assume vcpu0.
490 if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
491 vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
492 KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
494 mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
495 reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
497 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
503 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
509 * vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
511 * @dev: kvm device handle
512 * @attr: kvm device attribute
513 * @reg: address the value is read or written
514 * @is_write: true if userspace is writing a register
516 static int vgic_v3_attr_regs_access(struct kvm_device *dev,
517 struct kvm_device_attr *attr,
518 u64 *reg, bool is_write)
520 struct vgic_reg_attr reg_attr;
522 struct kvm_vcpu *vcpu;
526 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
530 vcpu = reg_attr.vcpu;
531 addr = reg_attr.addr;
533 mutex_lock(&dev->kvm->lock);
535 if (unlikely(!vgic_initialized(dev->kvm))) {
540 if (!lock_all_vcpus(dev->kvm)) {
545 switch (attr->group) {
546 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
550 ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &tmp32);
554 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
558 ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &tmp32);
562 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
565 regid = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
566 ret = vgic_v3_cpu_sysregs_uaccess(vcpu, is_write,
570 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
571 unsigned int info, intid;
573 info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
574 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
575 if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
577 KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
578 ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
590 unlock_all_vcpus(dev->kvm);
592 mutex_unlock(&dev->kvm->lock);
596 static int vgic_v3_set_attr(struct kvm_device *dev,
597 struct kvm_device_attr *attr)
601 ret = vgic_set_common_attr(dev, attr);
605 switch (attr->group) {
606 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
607 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
608 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
612 if (get_user(tmp32, uaddr))
616 return vgic_v3_attr_regs_access(dev, attr, ®, true);
618 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
619 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
622 if (get_user(reg, uaddr))
625 return vgic_v3_attr_regs_access(dev, attr, ®, true);
627 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
628 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
632 if (get_user(tmp32, uaddr))
636 return vgic_v3_attr_regs_access(dev, attr, ®, true);
638 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
641 switch (attr->attr) {
642 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
643 mutex_lock(&dev->kvm->lock);
645 if (!lock_all_vcpus(dev->kvm)) {
646 mutex_unlock(&dev->kvm->lock);
649 ret = vgic_v3_save_pending_tables(dev->kvm);
650 unlock_all_vcpus(dev->kvm);
651 mutex_unlock(&dev->kvm->lock);
660 static int vgic_v3_get_attr(struct kvm_device *dev,
661 struct kvm_device_attr *attr)
665 ret = vgic_get_common_attr(dev, attr);
669 switch (attr->group) {
670 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
671 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
672 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
676 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
680 return put_user(tmp32, uaddr);
682 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
683 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
686 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
689 return put_user(reg, uaddr);
691 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
692 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
696 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
700 return put_user(tmp32, uaddr);
706 static int vgic_v3_has_attr(struct kvm_device *dev,
707 struct kvm_device_attr *attr)
709 switch (attr->group) {
710 case KVM_DEV_ARM_VGIC_GRP_ADDR:
711 switch (attr->attr) {
712 case KVM_VGIC_V3_ADDR_TYPE_DIST:
713 case KVM_VGIC_V3_ADDR_TYPE_REDIST:
714 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
718 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
719 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
720 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
721 return vgic_v3_has_attr_regs(dev, attr);
722 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
724 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
725 if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
726 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
727 VGIC_LEVEL_INFO_LINE_LEVEL)
731 case KVM_DEV_ARM_VGIC_GRP_CTRL:
732 switch (attr->attr) {
733 case KVM_DEV_ARM_VGIC_CTRL_INIT:
735 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
742 struct kvm_device_ops kvm_arm_vgic_v3_ops = {
743 .name = "kvm-arm-vgic-v3",
744 .create = vgic_create,
745 .destroy = vgic_destroy,
746 .set_attr = vgic_v3_set_attr,
747 .get_attr = vgic_v3_get_attr,
748 .has_attr = vgic_v3_has_attr,