videocc-sm8150.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10
  11 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
  12
  13 #include "common.h"
  14 #include "clk-alpha-pll.h"
  15 #include "clk-branch.h"
  16 #include "clk-rcg.h"
  17 #include "clk-regmap.h"
  18 #include "reset.h"
  19 #include "gdsc.h"
  20
  21 enum {
  22         P_BI_TCXO,
  23         P_VIDEO_PLL0_OUT_MAIN,
  24 };
  25
  26 static struct pll_vco trion_vco[] = {
  27         { 249600000, 2000000000, 0 },
  28 };
  29
  30 static struct alpha_pll_config video_pll0_config = {
  31         .l = 0x14,
  32         .alpha = 0xD555,
  33         .config_ctl_val = 0x20485699,
  34         .config_ctl_hi_val = 0x00002267,
  35         .config_ctl_hi1_val = 0x00000024,
  36         .test_ctl_hi1_val = 0x00000020,
  37         .user_ctl_val = 0x00000000,
  38         .user_ctl_hi_val = 0x00000805,
  39         .user_ctl_hi1_val = 0x000000D0,
  40 };
  41
  42 static struct clk_alpha_pll video_pll0 = {
  43         .offset = 0x42c,
  44         .vco_table = trion_vco,
  45         .num_vco = ARRAY_SIZE(trion_vco),
  46         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  47         .clkr = {
  48                 .hw.init = &(struct clk_init_data){
  49                         .name = "video_pll0",
  50                         .parent_data = &(const struct clk_parent_data){
  51                                 .fw_name = "bi_tcxo",
  52                         },
  53                         .num_parents = 1,
  54                         .ops = &clk_alpha_pll_trion_ops,
  55                 },
  56         },
  57 };
  58
  59 static const struct parent_map video_cc_parent_map_0[] = {
  60         { P_BI_TCXO, 0 },
  61         { P_VIDEO_PLL0_OUT_MAIN, 1 },
  62 };
  63
  64 static const struct clk_parent_data video_cc_parent_data_0[] = {
  65         { .fw_name = "bi_tcxo" },
  66         { .hw = &video_pll0.clkr.hw },
  67 };
  68
  69 static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
  70         F(19200000, P_BI_TCXO, 1, 0, 0),
  71         F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  72         F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  73         F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  74         F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  75         F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  76         F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
  77         { }
  78 };
  79
  80 static struct clk_rcg2 video_cc_iris_clk_src = {
  81         .cmd_rcgr = 0x7f0,
  82         .mnd_width = 0,
  83         .hid_width = 5,
  84         .parent_map = video_cc_parent_map_0,
  85         .freq_tbl = ftbl_video_cc_iris_clk_src,
  86         .clkr.hw.init = &(struct clk_init_data){
  87                 .name = "video_cc_iris_clk_src",
  88                 .parent_data = video_cc_parent_data_0,
  89                 .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
  90                 .flags = CLK_SET_RATE_PARENT,
  91                 .ops = &clk_rcg2_shared_ops,
  92         },
  93 };
  94
  95 static struct clk_branch video_cc_iris_ahb_clk = {
  96         .halt_reg = 0x8f4,
  97         .halt_check = BRANCH_VOTED,
  98         .clkr = {
  99                 .enable_reg = 0x8f4,
 100                 .enable_mask = BIT(0),
 101                 .hw.init = &(struct clk_init_data){
 102                         .name = "video_cc_iris_ahb_clk",
 103                         .parent_hws = (const struct clk_hw*[]){
 104                                 &video_cc_iris_clk_src.clkr.hw,
 105                         },
 106                         .num_parents = 1,
 107                         .flags = CLK_SET_RATE_PARENT,
 108                         .ops = &clk_branch2_ops,
 109                 },
 110         },
 111 };
 112
 113 static struct clk_branch video_cc_mvs0_core_clk = {
 114         .halt_reg = 0x890,
 115         .halt_check = BRANCH_VOTED,
 116         .clkr = {
 117                 .enable_reg = 0x890,
 118                 .enable_mask = BIT(0),
 119                 .hw.init = &(struct clk_init_data){
 120                         .name = "video_cc_mvs0_core_clk",
 121                         .parent_hws = (const struct clk_hw*[]){
 122                                 &video_cc_iris_clk_src.clkr.hw,
 123                         },
 124                         .num_parents = 1,
 125                         .flags = CLK_SET_RATE_PARENT,
 126                         .ops = &clk_branch2_ops,
 127                 },
 128         },
 129 };
 130
 131 static struct clk_branch video_cc_mvs1_core_clk = {
 132         .halt_reg = 0x8d0,
 133         .halt_check = BRANCH_VOTED,
 134         .clkr = {
 135                 .enable_reg = 0x8d0,
 136                 .enable_mask = BIT(0),
 137                 .hw.init = &(struct clk_init_data){
 138                         .name = "video_cc_mvs1_core_clk",
 139                         .parent_hws = (const struct clk_hw*[]){
 140                                 &video_cc_iris_clk_src.clkr.hw,
 141                         },
 142                         .num_parents = 1,
 143                         .flags = CLK_SET_RATE_PARENT,
 144                         .ops = &clk_branch2_ops,
 145                 },
 146         },
 147 };
 148
 149 static struct clk_branch video_cc_mvsc_core_clk = {
 150         .halt_reg = 0x850,
 151         .halt_check = BRANCH_HALT,
 152         .clkr = {
 153                 .enable_reg = 0x850,
 154                 .enable_mask = BIT(0),
 155                 .hw.init = &(struct clk_init_data){
 156                         .name = "video_cc_mvsc_core_clk",
 157                         .parent_hws = (const struct clk_hw*[]){
 158                                 &video_cc_iris_clk_src.clkr.hw,
 159                         },
 160                         .num_parents = 1,
 161                         .flags = CLK_SET_RATE_PARENT,
 162                         .ops = &clk_branch2_ops,
 163                 },
 164         },
 165 };
 166
 167 static struct gdsc venus_gdsc = {
 168         .gdscr = 0x814,
 169         .pd = {
 170                 .name = "venus_gdsc",
 171         },
 172         .flags = 0,
 173         .pwrsts = PWRSTS_OFF_ON,
 174 };
 175
 176 static struct gdsc vcodec0_gdsc = {
 177         .gdscr = 0x874,
 178         .pd = {
 179                 .name = "vcodec0_gdsc",
 180         },
 181         .flags = HW_CTRL,
 182         .pwrsts = PWRSTS_OFF_ON,
 183 };
 184
 185 static struct gdsc vcodec1_gdsc = {
 186         .gdscr = 0x8b4,
 187         .pd = {
 188                 .name = "vcodec1_gdsc",
 189         },
 190         .flags = HW_CTRL,
 191         .pwrsts = PWRSTS_OFF_ON,
 192 };
 193 static struct clk_regmap *video_cc_sm8150_clocks[] = {
 194         [VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
 195         [VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
 196         [VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
 197         [VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
 198         [VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
 199         [VIDEO_CC_PLL0] = &video_pll0.clkr,
 200 };
 201
 202 static struct gdsc *video_cc_sm8150_gdscs[] = {
 203         [VENUS_GDSC] = &venus_gdsc,
 204         [VCODEC0_GDSC] = &vcodec0_gdsc,
 205         [VCODEC1_GDSC] = &vcodec1_gdsc,
 206 };
 207
 208 static const struct regmap_config video_cc_sm8150_regmap_config = {
 209         .reg_bits       = 32,
 210         .reg_stride     = 4,
 211         .val_bits       = 32,
 212         .max_register   = 0xb94,
 213         .fast_io        = true,
 214 };
 215
 216 static const struct qcom_reset_map video_cc_sm8150_resets[] = {
 217         [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
 218 };
 219
 220 static const struct qcom_cc_desc video_cc_sm8150_desc = {
 221         .config = &video_cc_sm8150_regmap_config,
 222         .clks = video_cc_sm8150_clocks,
 223         .num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
 224         .resets = video_cc_sm8150_resets,
 225         .num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
 226         .gdscs = video_cc_sm8150_gdscs,
 227         .num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs),
 228 };
 229
 230 static const struct of_device_id video_cc_sm8150_match_table[] = {
 231         { .compatible = "qcom,sm8150-videocc" },
 232         { }
 233 };
 234 MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
 235
 236 static int video_cc_sm8150_probe(struct platform_device *pdev)
 237 {
 238         struct regmap *regmap;
 239
 240         regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
 241         if (IS_ERR(regmap))
 242                 return PTR_ERR(regmap);
 243
 244         clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
 245
 246         /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
 247         regmap_update_bits(regmap, 0x984, 0x1, 0x1);
 248
 249         return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
 250 }
 251
 252 static struct platform_driver video_cc_sm8150_driver = {
 253         .probe = video_cc_sm8150_probe,
 254         .driver = {
 255                 .name   = "video_cc-sm8150",
 256                 .of_match_table = video_cc_sm8150_match_table,
 257         },
 258 };
 259
 260 static int __init video_cc_sm8150_init(void)
 261 {
 262         return platform_driver_register(&video_cc_sm8150_driver);
 263 }
 264 subsys_initcall(video_cc_sm8150_init);
 265
 266 static void __exit video_cc_sm8150_exit(void)
 267 {
 268         platform_driver_unregister(&video_cc_sm8150_driver);
 269 }
 270 module_exit(video_cc_sm8150_exit);
 271
 272 MODULE_LICENSE("GPL v2");
 273 MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");