1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/vfp/vfphw.S
5 * Copyright (C) 2004 ARM Limited.
6 * Written by Deep Blue Solutions Limited.
8 * This code is called from the kernel's undefined instruction trap.
9 * r9 holds the return address for successful handling.
10 * lr holds the return address for unrecognised instructions.
11 * r10 points at the start of the private FP workspace in the thread structure
12 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
14 #include <linux/init.h>
15 #include <linux/linkage.h>
16 #include <asm/thread_info.h>
17 #include <asm/vfpmacros.h>
18 #include <linux/kern_levels.h>
19 #include <asm/assembler.h>
20 #include <asm/asm-offsets.h>
24 stmfd sp!, {r0-r3, ip, lr}
27 ldmfd sp!, {r0-r3, ip, lr}
29 .pushsection .rodata, "a"
30 1: .ascii KERN_DEBUG "VFP: \str\n"
36 .macro DBGSTR1, str, arg
38 stmfd sp!, {r0-r3, ip, lr}
42 ldmfd sp!, {r0-r3, ip, lr}
44 .pushsection .rodata, "a"
45 1: .ascii KERN_DEBUG "VFP: \str\n"
51 .macro DBGSTR3, str, arg1, arg2, arg3
53 stmfd sp!, {r0-r3, ip, lr}
59 ldmfd sp!, {r0-r3, ip, lr}
61 .pushsection .rodata, "a"
62 1: .ascii KERN_DEBUG "VFP: \str\n"
69 @ VFP hardware support entry point.
71 @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
72 @ r2 = PC value to resume execution after successful emulation
73 @ r9 = normal "successful" return address
74 @ r10 = vfp_state union
76 @ lr = unrecognised instruction return address
78 ENTRY(vfp_support_entry)
79 DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
81 VFPFMRX r1, FPEXC @ Is the VFP enabled?
82 DBGSTR1 "fpexc %08x", r1
84 bne look_for_VFP_exceptions @ VFP is already enabled
86 DBGSTR1 "enable %x", r10
87 ldr r3, vfp_current_hw_state_address
88 orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
89 ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
90 bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
91 cmp r4, r10 @ this thread owns the hw context?
93 @ For UP, checking that this thread owns the hw context is
94 @ sufficient to determine that the hardware state is valid.
95 beq vfp_hw_state_valid
97 @ On UP, we lazily save the VFP context. As a different
98 @ thread wants ownership of the VFP hardware, save the old
99 @ state if there was a previous (valid) owner.
101 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
102 @ exceptions, so we can get at the
105 DBGSTR1 "save old state %p", r4
106 cmp r4, #0 @ if the vfp_current_hw_state is NULL
107 beq vfp_reload_hw @ then the hw state needs reloading
108 VFPFSTMIA r4, r5 @ save the working registers
109 VFPFMRX r5, FPSCR @ current status
110 #ifndef CONFIG_CPU_FEROCEON
111 tst r1, #FPEXC_EX @ is there additional state to save?
113 VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
114 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
116 VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
119 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
123 @ For SMP, if this thread does not own the hw context, then we
124 @ need to reload it. No need to save the old state as on SMP,
125 @ we always save the state when we switch away from a thread.
128 @ This thread has ownership of the current hardware context.
129 @ However, it may have been migrated to another CPU, in which
130 @ case the saved state is newer than the hardware context.
131 @ Check this by looking at the CPU number which the state was
133 ldr ip, [r10, #VFP_CPU]
135 beq vfp_hw_state_valid
138 @ We're loading this threads state into the VFP hardware. Update
139 @ the CPU number which contains the most up to date VFP context.
140 str r11, [r10, #VFP_CPU]
142 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
143 @ exceptions, so we can get at the
147 DBGSTR1 "load state %p", r10
148 str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer
149 @ Load the saved state back into the VFP
150 VFPFLDMIA r10, r5 @ reload the working registers while
151 @ FPEXC is in a safe state
152 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
153 #ifndef CONFIG_CPU_FEROCEON
154 tst r1, #FPEXC_EX @ is there additional state to restore?
156 VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
157 tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
159 VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
162 VFPFMXR FPSCR, r5 @ restore status
164 @ The context stored in the VFP hardware is up to date with this thread
167 bne process_exception @ might as well handle the pending
168 @ exception before retrying branch
169 @ out before setting an FPEXC that
170 @ stops us reading stuff
171 VFPFMXR FPEXC, r1 @ Restore FPEXC last
172 sub r2, r2, #4 @ Retry current instruction - if Thumb
173 str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
174 @ else it's one 32-bit instruction, so
175 @ always subtract 4 from the following
176 @ instruction address.
177 dec_preempt_count_ti r10, r4
178 ret r9 @ we think we have handled things
181 look_for_VFP_exceptions:
182 @ Check for synchronous or asynchronous exception
183 tst r1, #FPEXC_EX | FPEXC_DEX
184 bne process_exception
185 @ On some implementations of the VFP subarch 1, setting FPSCR.IXE
186 @ causes all the CDP instructions to be bounced synchronously without
187 @ setting the FPEXC.EX bit
190 bne process_exception
192 tst r5, #FPSCR_LENGTH_MASK
194 orr r1, r1, #FPEXC_DEX
198 @ Fall into hand on to next handler - appropriate coproc instr
199 @ not recognised by VFP
202 dec_preempt_count_ti r10, r4
207 mov r2, sp @ nothing stacked - regdump is at TOS
208 mov lr, r9 @ setup for a return to the user code.
210 @ Now call the C code to package up the bounce to the support code
211 @ r0 holds the trigger instruction
212 @ r1 holds the FPEXC value
213 @ r2 pointer to register dump
214 b VFP_bounce @ we have handled this - the support
215 @ code will raise an exception if
216 @ required. If not, the user code will
217 @ retry the faulted instruction
218 ENDPROC(vfp_support_entry)
220 ENTRY(vfp_save_state)
221 @ Save the current VFP state
224 DBGSTR1 "save VFP state %p", r0
225 VFPFSTMIA r0, r2 @ save the working registers
226 VFPFMRX r2, FPSCR @ current status
227 tst r1, #FPEXC_EX @ is there additional state to save?
229 VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
230 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
232 VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
234 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
236 ENDPROC(vfp_save_state)
239 vfp_current_hw_state_address:
240 .word vfp_current_hw_state
242 .macro tbl_branch, base, tmp, shift
243 #ifdef CONFIG_THUMB2_KERNEL
245 add \tmp, \tmp, \base, lsl \shift
248 add pc, pc, \base, lsl \shift
255 tbl_branch r0, r3, #3
257 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
262 .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
267 ENDPROC(vfp_get_float)
270 tbl_branch r1, r3, #3
272 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
277 .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
282 ENDPROC(vfp_put_float)
284 ENTRY(vfp_get_double)
285 tbl_branch r0, r3, #3
287 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
293 @ d16 - d31 registers
295 .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
302 @ virtual register 16 (or 32 if VFPv3) for compare with zero
306 ENDPROC(vfp_get_double)
308 ENTRY(vfp_put_double)
309 tbl_branch r2, r3, #3
311 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
318 @ d16 - d31 registers
319 .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
325 ENDPROC(vfp_put_double)