2 * Copyright(c) 2015 - 2017 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
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48 #include <rdma/ib_mad.h>
49 #include <rdma/ib_user_verbs.h>
51 #include <linux/module.h>
52 #include <linux/utsname.h>
53 #include <linux/rculist.h>
55 #include <linux/vmalloc.h>
62 #include "verbs_txreq.h"
64 static unsigned int hfi1_lkey_table_size = 16;
65 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
67 MODULE_PARM_DESC(lkey_table_size,
68 "LKEY table size in bits (2^n, 1 <= n <= 23)");
70 static unsigned int hfi1_max_pds = 0xFFFF;
71 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
72 MODULE_PARM_DESC(max_pds,
73 "Maximum number of protection domains to support");
75 static unsigned int hfi1_max_ahs = 0xFFFF;
76 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
77 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
79 unsigned int hfi1_max_cqes = 0x2FFFFF;
80 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
81 MODULE_PARM_DESC(max_cqes,
82 "Maximum number of completion queue entries to support");
84 unsigned int hfi1_max_cqs = 0x1FFFF;
85 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
86 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
88 unsigned int hfi1_max_qp_wrs = 0x3FFF;
89 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
90 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
92 unsigned int hfi1_max_qps = 32768;
93 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
94 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
96 unsigned int hfi1_max_sges = 0x60;
97 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
98 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
100 unsigned int hfi1_max_mcast_grps = 16384;
101 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
102 MODULE_PARM_DESC(max_mcast_grps,
103 "Maximum number of multicast groups to support");
105 unsigned int hfi1_max_mcast_qp_attached = 16;
106 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
108 MODULE_PARM_DESC(max_mcast_qp_attached,
109 "Maximum number of attached QPs to support");
111 unsigned int hfi1_max_srqs = 1024;
112 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
113 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
115 unsigned int hfi1_max_srq_sges = 128;
116 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
117 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
119 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
120 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
121 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
123 unsigned short piothreshold = 256;
124 module_param(piothreshold, ushort, S_IRUGO);
125 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
127 #define COPY_CACHELESS 1
128 #define COPY_ADAPTIVE 2
129 static unsigned int sge_copy_mode;
130 module_param(sge_copy_mode, uint, S_IRUGO);
131 MODULE_PARM_DESC(sge_copy_mode,
132 "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
134 static void verbs_sdma_complete(
135 struct sdma_txreq *cookie,
138 static int pio_wait(struct rvt_qp *qp,
139 struct send_context *sc,
140 struct hfi1_pkt_state *ps,
143 /* Length of buffer to create verbs txreq cache name */
144 #define TXREQ_NAME_LEN 24
146 static uint wss_threshold;
147 module_param(wss_threshold, uint, S_IRUGO);
148 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
149 static uint wss_clean_period = 256;
150 module_param(wss_clean_period, uint, S_IRUGO);
151 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
153 /* memory working set size */
155 unsigned long *entries;
156 atomic_t total_count;
157 atomic_t clean_counter;
158 atomic_t clean_entry;
165 static struct hfi1_wss wss;
167 int hfi1_wss_init(void)
174 /* check for a valid percent range - default to 80 if none or invalid */
175 if (wss_threshold < 1 || wss_threshold > 100)
177 /* reject a wildly large period */
178 if (wss_clean_period > 1000000)
179 wss_clean_period = 256;
180 /* reject a zero period */
181 if (wss_clean_period == 0)
182 wss_clean_period = 1;
185 * Calculate the table size - the next power of 2 larger than the
186 * LLC size. LLC size is in KiB.
188 llc_size = wss_llc_size() * 1024;
189 table_size = roundup_pow_of_two(llc_size);
191 /* one bit per page in rounded up table */
192 llc_bits = llc_size / PAGE_SIZE;
193 table_bits = table_size / PAGE_SIZE;
194 wss.pages_mask = table_bits - 1;
195 wss.num_entries = table_bits / BITS_PER_LONG;
197 wss.threshold = (llc_bits * wss_threshold) / 100;
198 if (wss.threshold == 0)
201 atomic_set(&wss.clean_counter, wss_clean_period);
203 wss.entries = kcalloc(wss.num_entries, sizeof(*wss.entries),
213 void hfi1_wss_exit(void)
215 /* coded to handle partially initialized and repeat callers */
221 * Advance the clean counter. When the clean period has expired,
224 * This is implemented in atomics to avoid locking. Because multiple
225 * variables are involved, it can be racy which can lead to slightly
226 * inaccurate information. Since this is only a heuristic, this is
227 * OK. Any innaccuracies will clean themselves out as the counter
228 * advances. That said, it is unlikely the entry clean operation will
229 * race - the next possible racer will not start until the next clean
232 * The clean counter is implemented as a decrement to zero. When zero
233 * is reached an entry is cleaned.
235 static void wss_advance_clean_counter(void)
241 /* become the cleaner if we decrement the counter to zero */
242 if (atomic_dec_and_test(&wss.clean_counter)) {
244 * Set, not add, the clean period. This avoids an issue
245 * where the counter could decrement below the clean period.
246 * Doing a set can result in lost decrements, slowing the
247 * clean advance. Since this a heuristic, this possible
250 * An alternative is to loop, advancing the counter by a
251 * clean period until the result is > 0. However, this could
252 * lead to several threads keeping another in the clean loop.
253 * This could be mitigated by limiting the number of times
254 * we stay in the loop.
256 atomic_set(&wss.clean_counter, wss_clean_period);
259 * Uniquely grab the entry to clean and move to next.
260 * The current entry is always the lower bits of
261 * wss.clean_entry. The table size, wss.num_entries,
262 * is always a power-of-2.
264 entry = (atomic_inc_return(&wss.clean_entry) - 1)
265 & (wss.num_entries - 1);
267 /* clear the entry and count the bits */
268 bits = xchg(&wss.entries[entry], 0);
269 weight = hweight64((u64)bits);
270 /* only adjust the contended total count if needed */
272 atomic_sub(weight, &wss.total_count);
277 * Insert the given address into the working set array.
279 static void wss_insert(void *address)
281 u32 page = ((unsigned long)address >> PAGE_SHIFT) & wss.pages_mask;
282 u32 entry = page / BITS_PER_LONG; /* assumes this ends up a shift */
283 u32 nr = page & (BITS_PER_LONG - 1);
285 if (!test_and_set_bit(nr, &wss.entries[entry]))
286 atomic_inc(&wss.total_count);
288 wss_advance_clean_counter();
292 * Is the working set larger than the threshold?
294 static inline int wss_exceeds_threshold(void)
296 return atomic_read(&wss.total_count) >= wss.threshold;
300 * Translate ib_wr_opcode into ib_wc_opcode.
302 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
303 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
304 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
305 [IB_WR_SEND] = IB_WC_SEND,
306 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
307 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
308 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
309 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
310 [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
311 [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
312 [IB_WR_REG_MR] = IB_WC_REG_MR
316 * Length of header by opcode, 0 --> not supported
318 const u8 hdr_len_by_opcode[256] = {
320 [IB_OPCODE_RC_SEND_FIRST] = 12 + 8,
321 [IB_OPCODE_RC_SEND_MIDDLE] = 12 + 8,
322 [IB_OPCODE_RC_SEND_LAST] = 12 + 8,
323 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
324 [IB_OPCODE_RC_SEND_ONLY] = 12 + 8,
325 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
326 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
327 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = 12 + 8,
328 [IB_OPCODE_RC_RDMA_WRITE_LAST] = 12 + 8,
329 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
330 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
331 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
332 [IB_OPCODE_RC_RDMA_READ_REQUEST] = 12 + 8 + 16,
333 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = 12 + 8 + 4,
334 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = 12 + 8,
335 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = 12 + 8 + 4,
336 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = 12 + 8 + 4,
337 [IB_OPCODE_RC_ACKNOWLEDGE] = 12 + 8 + 4,
338 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = 12 + 8 + 4 + 8,
339 [IB_OPCODE_RC_COMPARE_SWAP] = 12 + 8 + 28,
340 [IB_OPCODE_RC_FETCH_ADD] = 12 + 8 + 28,
341 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = 12 + 8 + 4,
342 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = 12 + 8 + 4,
344 [IB_OPCODE_UC_SEND_FIRST] = 12 + 8,
345 [IB_OPCODE_UC_SEND_MIDDLE] = 12 + 8,
346 [IB_OPCODE_UC_SEND_LAST] = 12 + 8,
347 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
348 [IB_OPCODE_UC_SEND_ONLY] = 12 + 8,
349 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 4,
350 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = 12 + 8 + 16,
351 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = 12 + 8,
352 [IB_OPCODE_UC_RDMA_WRITE_LAST] = 12 + 8,
353 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
354 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = 12 + 8 + 16,
355 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
357 [IB_OPCODE_UD_SEND_ONLY] = 12 + 8 + 8,
358 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = 12 + 8 + 12
361 static const opcode_handler opcode_handler_tbl[256] = {
363 [IB_OPCODE_RC_SEND_FIRST] = &hfi1_rc_rcv,
364 [IB_OPCODE_RC_SEND_MIDDLE] = &hfi1_rc_rcv,
365 [IB_OPCODE_RC_SEND_LAST] = &hfi1_rc_rcv,
366 [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
367 [IB_OPCODE_RC_SEND_ONLY] = &hfi1_rc_rcv,
368 [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
369 [IB_OPCODE_RC_RDMA_WRITE_FIRST] = &hfi1_rc_rcv,
370 [IB_OPCODE_RC_RDMA_WRITE_MIDDLE] = &hfi1_rc_rcv,
371 [IB_OPCODE_RC_RDMA_WRITE_LAST] = &hfi1_rc_rcv,
372 [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
373 [IB_OPCODE_RC_RDMA_WRITE_ONLY] = &hfi1_rc_rcv,
374 [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
375 [IB_OPCODE_RC_RDMA_READ_REQUEST] = &hfi1_rc_rcv,
376 [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = &hfi1_rc_rcv,
377 [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE] = &hfi1_rc_rcv,
378 [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = &hfi1_rc_rcv,
379 [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = &hfi1_rc_rcv,
380 [IB_OPCODE_RC_ACKNOWLEDGE] = &hfi1_rc_rcv,
381 [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = &hfi1_rc_rcv,
382 [IB_OPCODE_RC_COMPARE_SWAP] = &hfi1_rc_rcv,
383 [IB_OPCODE_RC_FETCH_ADD] = &hfi1_rc_rcv,
384 [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = &hfi1_rc_rcv,
385 [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = &hfi1_rc_rcv,
387 [IB_OPCODE_UC_SEND_FIRST] = &hfi1_uc_rcv,
388 [IB_OPCODE_UC_SEND_MIDDLE] = &hfi1_uc_rcv,
389 [IB_OPCODE_UC_SEND_LAST] = &hfi1_uc_rcv,
390 [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
391 [IB_OPCODE_UC_SEND_ONLY] = &hfi1_uc_rcv,
392 [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
393 [IB_OPCODE_UC_RDMA_WRITE_FIRST] = &hfi1_uc_rcv,
394 [IB_OPCODE_UC_RDMA_WRITE_MIDDLE] = &hfi1_uc_rcv,
395 [IB_OPCODE_UC_RDMA_WRITE_LAST] = &hfi1_uc_rcv,
396 [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
397 [IB_OPCODE_UC_RDMA_WRITE_ONLY] = &hfi1_uc_rcv,
398 [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
400 [IB_OPCODE_UD_SEND_ONLY] = &hfi1_ud_rcv,
401 [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = &hfi1_ud_rcv,
403 [IB_OPCODE_CNP] = &hfi1_cnp_rcv
408 static const u32 pio_opmask[BIT(3)] = {
410 [IB_OPCODE_RC >> 5] =
411 BIT(RC_OP(SEND_ONLY) & OPMASK) |
412 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
413 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
414 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
415 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
416 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
417 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
418 BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
419 BIT(RC_OP(FETCH_ADD) & OPMASK),
421 [IB_OPCODE_UC >> 5] =
422 BIT(UC_OP(SEND_ONLY) & OPMASK) |
423 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
424 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
425 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
431 __be64 ib_hfi1_sys_image_guid;
434 * hfi1_copy_sge - copy data to SGE memory
436 * @data: the data to copy
437 * @length: the length of the data
438 * @copy_last: do a separate copy of the last 8 bytes
441 struct rvt_sge_state *ss,
442 void *data, u32 length,
446 struct rvt_sge *sge = &ss->sge;
449 int cacheless_copy = 0;
451 if (sge_copy_mode == COPY_CACHELESS) {
452 cacheless_copy = length >= PAGE_SIZE;
453 } else if (sge_copy_mode == COPY_ADAPTIVE) {
454 if (length >= PAGE_SIZE) {
456 * NOTE: this *assumes*:
457 * o The first vaddr is the dest.
458 * o If multiple pages, then vaddr is sequential.
460 wss_insert(sge->vaddr);
461 if (length >= (2 * PAGE_SIZE))
462 wss_insert(sge->vaddr + PAGE_SIZE);
464 cacheless_copy = wss_exceeds_threshold();
466 wss_advance_clean_counter();
480 u32 len = sge->length;
484 if (len > sge->sge_length)
485 len = sge->sge_length;
486 WARN_ON_ONCE(len == 0);
487 if (unlikely(in_last)) {
488 /* enforce byte transfer ordering */
489 for (i = 0; i < len; i++)
490 ((u8 *)sge->vaddr)[i] = ((u8 *)data)[i];
491 } else if (cacheless_copy) {
492 cacheless_memcpy(sge->vaddr, data, len);
494 memcpy(sge->vaddr, data, len);
498 sge->sge_length -= len;
499 if (sge->sge_length == 0) {
503 *sge = *ss->sg_list++;
504 } else if (sge->length == 0 && sge->mr->lkey) {
505 if (++sge->n >= RVT_SEGSZ) {
506 if (++sge->m >= sge->mr->mapsz)
511 sge->mr->map[sge->m]->segs[sge->n].vaddr;
513 sge->mr->map[sge->m]->segs[sge->n].length;
528 * hfi1_skip_sge - skip over SGE memory
530 * @length: the number of bytes to skip
532 void hfi1_skip_sge(struct rvt_sge_state *ss, u32 length, int release)
534 struct rvt_sge *sge = &ss->sge;
537 u32 len = sge->length;
541 if (len > sge->sge_length)
542 len = sge->sge_length;
543 WARN_ON_ONCE(len == 0);
546 sge->sge_length -= len;
547 if (sge->sge_length == 0) {
551 *sge = *ss->sg_list++;
552 } else if (sge->length == 0 && sge->mr->lkey) {
553 if (++sge->n >= RVT_SEGSZ) {
554 if (++sge->m >= sge->mr->mapsz)
559 sge->mr->map[sge->m]->segs[sge->n].vaddr;
561 sge->mr->map[sge->m]->segs[sge->n].length;
568 * Make sure the QP is ready and able to accept the given opcode.
570 static inline opcode_handler qp_ok(int opcode, struct hfi1_packet *packet)
572 if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
574 if (((opcode & RVT_OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
575 (opcode == IB_OPCODE_CNP))
576 return opcode_handler_tbl[opcode];
582 * hfi1_ib_rcv - process an incoming packet
583 * @packet: data packet information
585 * This is called to process an incoming packet at interrupt level.
587 * Tlen is the length of the header + data + CRC in bytes.
589 void hfi1_ib_rcv(struct hfi1_packet *packet)
591 struct hfi1_ctxtdata *rcd = packet->rcd;
592 struct ib_header *hdr = packet->hdr;
593 u32 tlen = packet->tlen;
594 struct hfi1_pportdata *ppd = rcd->ppd;
595 struct hfi1_ibport *ibp = &ppd->ibport_data;
596 struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
597 opcode_handler packet_handler;
605 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
606 if (lnh == HFI1_LRH_BTH) {
607 packet->ohdr = &hdr->u.oth;
608 } else if (lnh == HFI1_LRH_GRH) {
611 packet->ohdr = &hdr->u.l.oth;
612 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
614 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
615 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
617 packet->rcv_flags |= HFI1_HAS_GRH;
622 trace_input_ibhdr(rcd->dd, hdr);
624 opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
625 inc_opstats(tlen, &rcd->opstats->stats[opcode]);
627 /* Get the destination QP number. */
628 qp_num = be32_to_cpu(packet->ohdr->bth[1]) & RVT_QPN_MASK;
629 lid = be16_to_cpu(hdr->lrh[1]);
630 if (unlikely((lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
631 (lid != be16_to_cpu(IB_LID_PERMISSIVE)))) {
632 struct rvt_mcast *mcast;
633 struct rvt_mcast_qp *p;
635 if (lnh != HFI1_LRH_GRH)
637 mcast = rvt_mcast_find(&ibp->rvp, &hdr->u.l.grh.dgid);
640 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
642 spin_lock_irqsave(&packet->qp->r_lock, flags);
643 packet_handler = qp_ok(opcode, packet);
644 if (likely(packet_handler))
645 packet_handler(packet);
647 ibp->rvp.n_pkt_drops++;
648 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
651 * Notify rvt_multicast_detach() if it is waiting for us
654 if (atomic_dec_return(&mcast->refcount) <= 1)
655 wake_up(&mcast->wait);
658 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
663 spin_lock_irqsave(&packet->qp->r_lock, flags);
664 packet_handler = qp_ok(opcode, packet);
665 if (likely(packet_handler))
666 packet_handler(packet);
668 ibp->rvp.n_pkt_drops++;
669 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
675 ibp->rvp.n_pkt_drops++;
679 * This is called from a timer to check for QPs
680 * which need kernel memory in order to send a packet.
682 static void mem_timer(unsigned long data)
684 struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
685 struct list_head *list = &dev->memwait;
686 struct rvt_qp *qp = NULL;
689 struct hfi1_qp_priv *priv;
691 write_seqlock_irqsave(&dev->iowait_lock, flags);
692 if (!list_empty(list)) {
693 wait = list_first_entry(list, struct iowait, list);
694 qp = iowait_to_qp(wait);
696 list_del_init(&priv->s_iowait.list);
697 /* refcount held until actual wake up */
698 if (!list_empty(list))
699 mod_timer(&dev->mem_timer, jiffies + 1);
701 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
704 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
707 void update_sge(struct rvt_sge_state *ss, u32 length)
709 struct rvt_sge *sge = &ss->sge;
711 sge->vaddr += length;
712 sge->length -= length;
713 sge->sge_length -= length;
714 if (sge->sge_length == 0) {
716 *sge = *ss->sg_list++;
717 } else if (sge->length == 0 && sge->mr->lkey) {
718 if (++sge->n >= RVT_SEGSZ) {
719 if (++sge->m >= sge->mr->mapsz)
723 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
724 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
729 * This is called with progress side lock held.
732 static void verbs_sdma_complete(
733 struct sdma_txreq *cookie,
736 struct verbs_txreq *tx =
737 container_of(cookie, struct verbs_txreq, txreq);
738 struct rvt_qp *qp = tx->qp;
740 spin_lock(&qp->s_lock);
742 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
743 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
744 struct ib_header *hdr;
747 hfi1_rc_send_complete(qp, hdr);
749 spin_unlock(&qp->s_lock);
754 static int wait_kmem(struct hfi1_ibdev *dev,
756 struct hfi1_pkt_state *ps)
758 struct hfi1_qp_priv *priv = qp->priv;
762 spin_lock_irqsave(&qp->s_lock, flags);
763 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
764 write_seqlock(&dev->iowait_lock);
765 list_add_tail(&ps->s_txreq->txreq.list,
766 &priv->s_iowait.tx_head);
767 if (list_empty(&priv->s_iowait.list)) {
768 if (list_empty(&dev->memwait))
769 mod_timer(&dev->mem_timer, jiffies + 1);
770 qp->s_flags |= RVT_S_WAIT_KMEM;
771 list_add_tail(&priv->s_iowait.list, &dev->memwait);
772 trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
775 write_sequnlock(&dev->iowait_lock);
776 qp->s_flags &= ~RVT_S_BUSY;
779 spin_unlock_irqrestore(&qp->s_lock, flags);
785 * This routine calls txadds for each sg entry.
787 * Add failures will revert the sge cursor
789 static noinline int build_verbs_ulp_payload(
790 struct sdma_engine *sde,
791 struct rvt_sge_state *ss,
793 struct verbs_txreq *tx)
795 struct rvt_sge *sg_list = ss->sg_list;
796 struct rvt_sge sge = ss->sge;
797 u8 num_sge = ss->num_sge;
802 len = ss->sge.length;
805 if (len > ss->sge.sge_length)
806 len = ss->sge.sge_length;
807 WARN_ON_ONCE(len == 0);
808 ret = sdma_txadd_kvaddr(
822 ss->num_sge = num_sge;
823 ss->sg_list = sg_list;
828 * Build the number of DMA descriptors needed to send length bytes of data.
830 * NOTE: DMA mapping is held in the tx until completed in the ring or
831 * the tx desc is freed without having been submitted to the ring
833 * This routine ensures all the helper routine calls succeed.
836 static int build_verbs_tx_desc(
837 struct sdma_engine *sde,
838 struct rvt_sge_state *ss,
840 struct verbs_txreq *tx,
841 struct hfi1_ahg_info *ahg_info,
845 struct hfi1_sdma_header *phdr = &tx->phdr;
846 u16 hdrbytes = tx->hdr_dwords << 2;
848 if (!ahg_info->ahgcount) {
849 ret = sdma_txinit_ahg(
857 verbs_sdma_complete);
860 phdr->pbc = cpu_to_le64(pbc);
861 ret = sdma_txadd_kvaddr(
869 ret = sdma_txinit_ahg(
877 verbs_sdma_complete);
882 /* add the ulp payload - if any. ss can be NULL for acks */
884 ret = build_verbs_ulp_payload(sde, ss, length, tx);
889 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
892 struct hfi1_qp_priv *priv = qp->priv;
893 struct hfi1_ahg_info *ahg_info = priv->s_ahg;
894 u32 hdrwords = qp->s_hdrwords;
895 struct rvt_sge_state *ss = qp->s_cur_sge;
896 u32 len = qp->s_cur_size;
897 u32 plen = hdrwords + ((len + 3) >> 2) + 2; /* includes pbc */
898 struct hfi1_ibdev *dev = ps->dev;
899 struct hfi1_pportdata *ppd = ps->ppd;
900 struct verbs_txreq *tx;
907 if (!sdma_txreq_built(&tx->txreq)) {
908 if (likely(pbc == 0)) {
909 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
911 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
912 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
914 pbc = create_pbc(ppd,
921 ret = build_verbs_tx_desc(tx->sde, ss, len, tx, ahg_info, pbc);
925 ret = sdma_send_txreq(tx->sde, &priv->s_iowait, &tx->txreq);
926 if (unlikely(ret < 0)) {
931 trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
932 &ps->s_txreq->phdr.hdr);
936 /* The current one got "sent" */
939 ret = wait_kmem(dev, qp, ps);
941 /* free txreq - bad state */
942 hfi1_put_txreq(ps->s_txreq);
949 * If we are now in the error state, return zero to flush the
952 static int pio_wait(struct rvt_qp *qp,
953 struct send_context *sc,
954 struct hfi1_pkt_state *ps,
957 struct hfi1_qp_priv *priv = qp->priv;
958 struct hfi1_devdata *dd = sc->dd;
959 struct hfi1_ibdev *dev = &dd->verbs_dev;
964 * Note that as soon as want_buffer() is called and
965 * possibly before it returns, sc_piobufavail()
966 * could be called. Therefore, put QP on the I/O wait list before
967 * enabling the PIO avail interrupt.
969 spin_lock_irqsave(&qp->s_lock, flags);
970 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
971 write_seqlock(&dev->iowait_lock);
972 list_add_tail(&ps->s_txreq->txreq.list,
973 &priv->s_iowait.tx_head);
974 if (list_empty(&priv->s_iowait.list)) {
975 struct hfi1_ibdev *dev = &dd->verbs_dev;
978 dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
979 dev->n_piodrain += !!(flag & RVT_S_WAIT_PIO_DRAIN);
981 was_empty = list_empty(&sc->piowait);
982 list_add_tail(&priv->s_iowait.list, &sc->piowait);
983 trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
985 /* counting: only call wantpiobuf_intr if first user */
987 hfi1_sc_wantpiobuf_intr(sc, 1);
989 write_sequnlock(&dev->iowait_lock);
990 qp->s_flags &= ~RVT_S_BUSY;
993 spin_unlock_irqrestore(&qp->s_lock, flags);
997 static void verbs_pio_complete(void *arg, int code)
999 struct rvt_qp *qp = (struct rvt_qp *)arg;
1000 struct hfi1_qp_priv *priv = qp->priv;
1002 if (iowait_pio_dec(&priv->s_iowait))
1003 iowait_drain_wakeup(&priv->s_iowait);
1006 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1009 struct hfi1_qp_priv *priv = qp->priv;
1010 u32 hdrwords = qp->s_hdrwords;
1011 struct rvt_sge_state *ss = qp->s_cur_sge;
1012 u32 len = qp->s_cur_size;
1013 u32 dwords = (len + 3) >> 2;
1014 u32 plen = hdrwords + dwords + 2; /* includes pbc */
1015 struct hfi1_pportdata *ppd = ps->ppd;
1016 u32 *hdr = (u32 *)&ps->s_txreq->phdr.hdr;
1019 unsigned long flags = 0;
1020 struct send_context *sc;
1021 struct pio_buf *pbuf;
1022 int wc_status = IB_WC_SUCCESS;
1024 pio_release_cb cb = NULL;
1026 /* only RC/UC use complete */
1027 switch (qp->ibqp.qp_type) {
1030 cb = verbs_pio_complete;
1036 /* vl15 special case taken care of in ud.c */
1038 sc = ps->s_txreq->psc;
1040 if (likely(pbc == 0)) {
1041 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1042 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1043 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1044 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1047 iowait_pio_inc(&priv->s_iowait);
1048 pbuf = sc_buffer_alloc(sc, plen, cb, qp);
1049 if (unlikely(!pbuf)) {
1051 verbs_pio_complete(qp, 0);
1052 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1054 * If we have filled the PIO buffers to capacity and are
1055 * not in an active state this request is not going to
1056 * go out to so just complete it with an error or else a
1057 * ULP or the core may be stuck waiting.
1061 "alloc failed. state not active, completing");
1062 wc_status = IB_WC_GENERAL_ERR;
1066 * This is a normal occurrence. The PIO buffs are full
1067 * up but we are still happily sending, well we could be
1068 * so lets continue to queue the request.
1070 hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1071 ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
1073 /* txreq not queued - free */
1075 /* tx consumed in wait */
1081 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1084 seg_pio_copy_start(pbuf, pbc, hdr, hdrwords * 4);
1086 void *addr = ss->sge.vaddr;
1087 u32 slen = ss->sge.length;
1091 if (slen > ss->sge.sge_length)
1092 slen = ss->sge.sge_length;
1093 update_sge(ss, slen);
1094 seg_pio_copy_mid(pbuf, addr, slen);
1097 seg_pio_copy_end(pbuf);
1101 trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1102 &ps->s_txreq->phdr.hdr);
1106 spin_lock_irqsave(&qp->s_lock, flags);
1107 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1108 spin_unlock_irqrestore(&qp->s_lock, flags);
1109 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1110 spin_lock_irqsave(&qp->s_lock, flags);
1111 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1112 spin_unlock_irqrestore(&qp->s_lock, flags);
1118 hfi1_put_txreq(ps->s_txreq);
1123 * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1124 * being an entry from the partition key table), return 0
1125 * otherwise. Use the matching criteria for egress partition keys
1126 * specified in the OPAv1 spec., section 9.1l.7.
1128 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1130 u16 mkey = pkey & PKEY_LOW_15_MASK;
1131 u16 mentry = ent & PKEY_LOW_15_MASK;
1133 if (mkey == mentry) {
1135 * If pkey[15] is set (full partition member),
1136 * is bit 15 in the corresponding table element
1137 * clear (limited member)?
1139 if (pkey & PKEY_MEMBER_MASK)
1140 return !!(ent & PKEY_MEMBER_MASK);
1147 * egress_pkey_check - check P_KEY of a packet
1148 * @ppd: Physical IB port data
1149 * @lrh: Local route header
1150 * @bth: Base transport header
1151 * @sc5: SC for packet
1152 * @s_pkey_index: It will be used for look up optimization for kernel contexts
1153 * only. If it is negative value, then it means user contexts is calling this
1156 * It checks if hdr's pkey is valid.
1158 * Return: 0 on success, otherwise, 1
1160 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth,
1161 u8 sc5, int8_t s_pkey_index)
1163 struct hfi1_devdata *dd;
1166 int is_user_ctxt_mechanism = (s_pkey_index < 0);
1168 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1171 pkey = (u16)be32_to_cpu(bth[0]);
1173 /* If SC15, pkey[0:14] must be 0x7fff */
1174 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1177 /* Is the pkey = 0x0, or 0x8000? */
1178 if ((pkey & PKEY_LOW_15_MASK) == 0)
1182 * For the kernel contexts only, if a qp is passed into the function,
1183 * the most likely matching pkey has index qp->s_pkey_index
1185 if (!is_user_ctxt_mechanism &&
1186 egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1190 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1191 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1196 * For the user-context mechanism, the P_KEY check would only happen
1197 * once per SDMA request, not once per packet. Therefore, there's no
1198 * need to increment the counter for the user-context mechanism.
1200 if (!is_user_ctxt_mechanism) {
1201 incr_cntr64(&ppd->port_xmit_constraint_errors);
1203 if (!(dd->err_info_xmit_constraint.status &
1204 OPA_EI_STATUS_SMASK)) {
1205 u16 slid = be16_to_cpu(lrh[3]);
1207 dd->err_info_xmit_constraint.status |=
1208 OPA_EI_STATUS_SMASK;
1209 dd->err_info_xmit_constraint.slid = slid;
1210 dd->err_info_xmit_constraint.pkey = pkey;
1217 * get_send_routine - choose an egress routine
1219 * Choose an egress routine based on QP type
1222 static inline send_routine get_send_routine(struct rvt_qp *qp,
1223 struct verbs_txreq *tx)
1225 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1226 struct hfi1_qp_priv *priv = qp->priv;
1227 struct ib_header *h = &tx->phdr.hdr;
1229 if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1230 return dd->process_pio_send;
1231 switch (qp->ibqp.qp_type) {
1233 return dd->process_pio_send;
1239 u8 op = get_opcode(h);
1242 qp->s_cur_size <= min(piothreshold, qp->pmtu) &&
1243 (BIT(op & OPMASK) & pio_opmask[op >> 5]) &&
1244 iowait_sdma_pending(&priv->s_iowait) == 0 &&
1245 !sdma_txreq_built(&tx->txreq))
1246 return dd->process_pio_send;
1252 return dd->process_dma_send;
1256 * hfi1_verbs_send - send a packet
1257 * @qp: the QP to send on
1258 * @ps: the state of the packet to send
1260 * Return zero if packet is sent or queued OK.
1261 * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1263 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1265 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1266 struct hfi1_qp_priv *priv = qp->priv;
1267 struct ib_other_headers *ohdr;
1268 struct ib_header *hdr;
1273 hdr = &ps->s_txreq->phdr.hdr;
1274 /* locate the pkey within the headers */
1275 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1276 if (lnh == HFI1_LRH_GRH)
1277 ohdr = &hdr->u.l.oth;
1281 sr = get_send_routine(qp, ps->s_txreq);
1282 ret = egress_pkey_check(dd->pport,
1287 if (unlikely(ret)) {
1289 * The value we are returning here does not get propagated to
1290 * the verbs caller. Thus we need to complete the request with
1291 * error otherwise the caller could be sitting waiting on the
1292 * completion event. Only do this for PIO. SDMA has its own
1293 * mechanism for handling the errors. So for SDMA we can just
1296 if (sr == dd->process_pio_send) {
1297 unsigned long flags;
1299 hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1301 spin_lock_irqsave(&qp->s_lock, flags);
1302 hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1303 spin_unlock_irqrestore(&qp->s_lock, flags);
1307 if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1311 RVT_S_WAIT_PIO_DRAIN);
1312 return sr(qp, ps, 0);
1316 * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1317 * @dd: the device data structure
1319 static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1321 struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1322 u16 ver = dd->dc8051_ver;
1324 memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1326 rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 16) |
1327 (u64)dc8051_ver_min(ver);
1328 rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1329 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1330 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1331 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1332 IB_DEVICE_MEM_MGT_EXTENSIONS;
1333 rdi->dparms.props.page_size_cap = PAGE_SIZE;
1334 rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1335 rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1336 rdi->dparms.props.hw_ver = dd->minrev;
1337 rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1338 rdi->dparms.props.max_mr_size = U64_MAX;
1339 rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1340 rdi->dparms.props.max_qp = hfi1_max_qps;
1341 rdi->dparms.props.max_qp_wr = hfi1_max_qp_wrs;
1342 rdi->dparms.props.max_sge = hfi1_max_sges;
1343 rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1344 rdi->dparms.props.max_cq = hfi1_max_cqs;
1345 rdi->dparms.props.max_ah = hfi1_max_ahs;
1346 rdi->dparms.props.max_cqe = hfi1_max_cqes;
1347 rdi->dparms.props.max_map_per_fmr = 32767;
1348 rdi->dparms.props.max_pd = hfi1_max_pds;
1349 rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1350 rdi->dparms.props.max_qp_init_rd_atom = 255;
1351 rdi->dparms.props.max_srq = hfi1_max_srqs;
1352 rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1353 rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1354 rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1355 rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1356 rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1357 rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1358 rdi->dparms.props.max_total_mcast_qp_attach =
1359 rdi->dparms.props.max_mcast_qp_attach *
1360 rdi->dparms.props.max_mcast_grp;
1363 static inline u16 opa_speed_to_ib(u16 in)
1367 if (in & OPA_LINK_SPEED_25G)
1368 out |= IB_SPEED_EDR;
1369 if (in & OPA_LINK_SPEED_12_5G)
1370 out |= IB_SPEED_FDR;
1376 * Convert a single OPA link width (no multiple flags) to an IB value.
1377 * A zero OPA link width means link down, which means the IB width value
1380 static inline u16 opa_width_to_ib(u16 in)
1383 case OPA_LINK_WIDTH_1X:
1384 /* map 2x and 3x to 1x as they don't exist in IB */
1385 case OPA_LINK_WIDTH_2X:
1386 case OPA_LINK_WIDTH_3X:
1388 default: /* link down or unknown, return our largest width */
1389 case OPA_LINK_WIDTH_4X:
1394 static int query_port(struct rvt_dev_info *rdi, u8 port_num,
1395 struct ib_port_attr *props)
1397 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1398 struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1399 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1402 props->lid = lid ? lid : 0;
1403 props->lmc = ppd->lmc;
1404 /* OPA logical states match IB logical states */
1405 props->state = driver_lstate(ppd);
1406 props->phys_state = hfi1_ibphys_portstate(ppd);
1407 props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1408 props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1409 /* see rate_show() in ib core/sysfs.c */
1410 props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1411 props->max_vl_num = ppd->vls_supported;
1413 /* Once we are a "first class" citizen and have added the OPA MTUs to
1414 * the core we can advertise the larger MTU enum to the ULPs, for now
1415 * advertise only 4K.
1417 * Those applications which are either OPA aware or pass the MTU enum
1418 * from the Path Records to us will get the new 8k MTU. Those that
1419 * attempt to process the MTU enum may fail in various ways.
1421 props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1422 4096 : hfi1_max_mtu), IB_MTU_4096);
1423 props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1424 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1429 static int modify_device(struct ib_device *device,
1430 int device_modify_mask,
1431 struct ib_device_modify *device_modify)
1433 struct hfi1_devdata *dd = dd_from_ibdev(device);
1437 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1438 IB_DEVICE_MODIFY_NODE_DESC)) {
1443 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1444 memcpy(device->node_desc, device_modify->node_desc,
1445 IB_DEVICE_NODE_DESC_MAX);
1446 for (i = 0; i < dd->num_pports; i++) {
1447 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1449 hfi1_node_desc_chg(ibp);
1453 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1454 ib_hfi1_sys_image_guid =
1455 cpu_to_be64(device_modify->sys_image_guid);
1456 for (i = 0; i < dd->num_pports; i++) {
1457 struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1459 hfi1_sys_guid_chg(ibp);
1469 static int shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1471 struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1472 struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1473 struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1476 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1477 OPA_LINKDOWN_REASON_UNKNOWN);
1478 ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1482 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1483 int guid_index, __be64 *guid)
1485 struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1486 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1488 if (guid_index == 0)
1489 *guid = cpu_to_be64(ppd->guid);
1490 else if (guid_index < HFI1_GUIDS_PER_PORT)
1491 *guid = ibp->guids[guid_index - 1];
1499 * convert ah port,sl to sc
1501 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1503 struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1505 return ibp->sl_to_sc[ah->sl];
1508 static int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1510 struct hfi1_ibport *ibp;
1511 struct hfi1_pportdata *ppd;
1512 struct hfi1_devdata *dd;
1516 /* test the mapping for validity */
1517 ibp = to_iport(ibdev, ah_attr->port_num);
1518 ppd = ppd_from_ibp(ibp);
1519 dd = dd_from_ppd(ppd);
1522 if (sl >= ARRAY_SIZE(ibp->sl_to_sc))
1525 sc5 = ibp->sl_to_sc[sl];
1526 if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1531 static void hfi1_notify_new_ah(struct ib_device *ibdev,
1532 struct ib_ah_attr *ah_attr,
1535 struct hfi1_ibport *ibp;
1536 struct hfi1_pportdata *ppd;
1537 struct hfi1_devdata *dd;
1541 * Do not trust reading anything from rvt_ah at this point as it is not
1542 * done being setup. We can however modify things which we need to set.
1545 ibp = to_iport(ibdev, ah_attr->port_num);
1546 ppd = ppd_from_ibp(ibp);
1547 sc5 = ibp->sl_to_sc[ah->attr.sl];
1548 dd = dd_from_ppd(ppd);
1549 ah->vl = sc_to_vlt(dd, sc5);
1550 if (ah->vl < num_vls || ah->vl == 15)
1551 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1554 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1556 struct ib_ah_attr attr;
1557 struct ib_ah *ah = ERR_PTR(-EINVAL);
1560 memset(&attr, 0, sizeof(attr));
1562 attr.port_num = ppd_from_ibp(ibp)->port;
1564 qp0 = rcu_dereference(ibp->rvp.qp[0]);
1566 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1572 * hfi1_get_npkeys - return the size of the PKEY table for context 0
1573 * @dd: the hfi1_ib device
1575 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1577 return ARRAY_SIZE(dd->pport[0].pkeys);
1580 static void init_ibport(struct hfi1_pportdata *ppd)
1582 struct hfi1_ibport *ibp = &ppd->ibport_data;
1583 size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1586 for (i = 0; i < sz; i++) {
1587 ibp->sl_to_sc[i] = i;
1588 ibp->sc_to_sl[i] = i;
1591 spin_lock_init(&ibp->rvp.lock);
1592 /* Set the prefix to the default value (see ch. 4.1.1) */
1593 ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1594 ibp->rvp.sm_lid = 0;
1595 /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1596 ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1597 IB_PORT_CAP_MASK_NOTICE_SUP;
1598 ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1599 ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1600 ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1601 ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1602 ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1604 RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1605 RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1608 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str,
1611 struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1612 struct hfi1_ibdev *dev = dev_from_rdi(rdi);
1613 u16 ver = dd_from_dev(dev)->dc8051_ver;
1615 snprintf(str, str_len, "%u.%u", dc8051_ver_maj(ver),
1616 dc8051_ver_min(ver));
1620 * hfi1_register_ib_device - register our device with the infiniband core
1621 * @dd: the device data structure
1622 * Return 0 if successful, errno if unsuccessful.
1624 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1626 struct hfi1_ibdev *dev = &dd->verbs_dev;
1627 struct ib_device *ibdev = &dev->rdi.ibdev;
1628 struct hfi1_pportdata *ppd = dd->pport;
1631 size_t lcpysz = IB_DEVICE_NAME_MAX;
1633 for (i = 0; i < dd->num_pports; i++)
1634 init_ibport(ppd + i);
1636 /* Only need to initialize non-zero fields. */
1638 setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev);
1640 seqlock_init(&dev->iowait_lock);
1641 INIT_LIST_HEAD(&dev->txwait);
1642 INIT_LIST_HEAD(&dev->memwait);
1644 ret = verbs_txreq_init(dev);
1646 goto err_verbs_txreq;
1649 * The system image GUID is supposed to be the same for all
1650 * HFIs in a single system but since there can be other
1651 * device types in the system, we can't be sure this is unique.
1653 if (!ib_hfi1_sys_image_guid)
1654 ib_hfi1_sys_image_guid = cpu_to_be64(ppd->guid);
1655 lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1656 strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1657 ibdev->owner = THIS_MODULE;
1658 ibdev->node_guid = cpu_to_be64(ppd->guid);
1659 ibdev->phys_port_cnt = dd->num_pports;
1660 ibdev->dma_device = &dd->pcidev->dev;
1661 ibdev->modify_device = modify_device;
1663 /* keep process mad in the driver */
1664 ibdev->process_mad = hfi1_process_mad;
1665 ibdev->get_dev_fw_str = hfi1_get_dev_fw_str;
1667 strncpy(ibdev->node_desc, init_utsname()->nodename,
1668 sizeof(ibdev->node_desc));
1671 * Fill in rvt info object.
1673 dd->verbs_dev.rdi.driver_f.port_callback = hfi1_create_port_files;
1674 dd->verbs_dev.rdi.driver_f.get_card_name = get_card_name;
1675 dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1676 dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1677 dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1678 dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1679 dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1680 dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1681 dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1683 * Fill in rvt info device attributes.
1685 hfi1_fill_device_attr(dd);
1688 dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1689 dd->verbs_dev.rdi.dparms.qpn_start = 0;
1690 dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1691 dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
1692 dd->verbs_dev.rdi.dparms.qpn_res_start = kdeth_qp << 16;
1693 dd->verbs_dev.rdi.dparms.qpn_res_end =
1694 dd->verbs_dev.rdi.dparms.qpn_res_start + 65535;
1695 dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1696 dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1697 dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1698 dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
1699 dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1700 dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1702 dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
1703 dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1704 dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1705 dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1706 dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send_from_rvt;
1707 dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1708 dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1709 dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1710 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1711 dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1712 dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1713 dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1714 dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1715 dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1716 dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1717 dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1718 dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
1719 dd->verbs_dev.rdi.driver_f.check_send_wqe = hfi1_check_send_wqe;
1721 /* completeion queue */
1722 snprintf(dd->verbs_dev.rdi.dparms.cq_name,
1723 sizeof(dd->verbs_dev.rdi.dparms.cq_name),
1724 "hfi1_cq%d", dd->unit);
1725 dd->verbs_dev.rdi.dparms.node = dd->node;
1728 dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1729 dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1730 dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1731 dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1733 /* post send table */
1734 dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
1737 for (i = 0; i < dd->num_pports; i++, ppd++)
1738 rvt_init_port(&dd->verbs_dev.rdi,
1739 &ppd->ibport_data.rvp,
1743 ret = rvt_register_device(&dd->verbs_dev.rdi);
1745 goto err_verbs_txreq;
1747 ret = hfi1_verbs_register_sysfs(dd);
1754 rvt_unregister_device(&dd->verbs_dev.rdi);
1756 verbs_txreq_exit(dev);
1757 dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1761 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1763 struct hfi1_ibdev *dev = &dd->verbs_dev;
1765 hfi1_verbs_unregister_sysfs(dd);
1767 rvt_unregister_device(&dd->verbs_dev.rdi);
1769 if (!list_empty(&dev->txwait))
1770 dd_dev_err(dd, "txwait list not empty!\n");
1771 if (!list_empty(&dev->memwait))
1772 dd_dev_err(dd, "memwait list not empty!\n");
1774 del_timer_sync(&dev->mem_timer);
1775 verbs_txreq_exit(dev);
1778 void hfi1_cnp_rcv(struct hfi1_packet *packet)
1780 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
1781 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1782 struct ib_header *hdr = packet->hdr;
1783 struct rvt_qp *qp = packet->qp;
1786 u8 sl, sc5, svc_type;
1788 switch (packet->qp->ibqp.qp_type) {
1790 rlid = qp->remote_ah_attr.dlid;
1791 rqpn = qp->remote_qpn;
1792 svc_type = IB_CC_SVCTYPE_UC;
1795 rlid = qp->remote_ah_attr.dlid;
1796 rqpn = qp->remote_qpn;
1797 svc_type = IB_CC_SVCTYPE_RC;
1802 svc_type = IB_CC_SVCTYPE_UD;
1805 ibp->rvp.n_pkt_drops++;
1809 sc5 = hdr2sc(hdr, packet->rhf);
1810 sl = ibp->sc_to_sl[sc5];
1811 lqpn = qp->ibqp.qp_num;
1813 process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);