109071a20ed7d960ce9fe5dfccb25f604f68e912
[open-ath9k-htc-firmware.git] / usb_defs.h
1 /*
2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted (subject to the limitations in the
7  * disclaimer below) provided that the following conditions are met:
8  *
9  *  * Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  *
12  *  * Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the
15  *    distribution.
16  *
17  *  * Neither the name of Qualcomm Atheros nor the names of its
18  *    contributors may be used to endorse or promote products derived
19  *    from this software without specific prior written permission.
20  *
21  * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22  * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23  * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 #ifndef USB_DEFS_H
36 #define USB_DEFS_H
37
38 #include "usb_table.h"
39 #include "dt_defs.h"
40 #include "reg_defs.h"
41
42 #define CHECK_SWITCH_BY_BOOTCODE         1   //to be verified for ZD1215, OK for ZD1211
43 #define VERIFY_CHECKSUM_BY_BOOTCODE      1
44
45 /***********************************************************************/
46 /*  for SEEPROM  Boot                                                  */
47 /***********************************************************************/
48 #define WLAN_BOOT_SIGNATURE         (0x19710303)
49
50 #define WLAN_SIGNATURE_ADDR         (0x102000)
51
52 #define cMAX_ADDR                       0x10000
53
54 #define cEEPROM_SIZE                    0x800       // 2k word (4k byte)
55
56 #define cRESERVE_LOAD_SPACE             0
57
58 // start addr. of boot code
59 #define cBOOT_CODE_ADDR                 (cMAX_ADDR - cEEPROM_SIZE)  // 0xF800
60
61 /************************** Register Addr Process *********************/
62 #define mpADDR(addr)                                            ((volatile uint16_t*) (addr))
63 #define mADDR(addr)                                             (*mpADDR(addr))
64 #define muADDR(addr)                                            ((uint16_t) (&(addr)))
65
66 #define USB_BYTE_REG_WRITE(addr, val)           HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val))
67 #define USB_BYTE_REG_READ(addr)                 HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3))
68 //#define USB_BYTE_REG_READ(addr)               HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr))
69
70 #define USB_HALF_WORD_REG_WRITE(addr, val)      HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val))
71 #define USB_HALF_WORD_REG_READ(addr)            HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr))
72
73 #define USB_WORD_REG_WRITE(addr, val)           HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val))
74 #define USB_WORD_REG_READ(addr)                 HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr))
75
76
77 /************************** Register Deinition ***************************/
78 //#define USB_BASE_ADDR_SOC                0x8000
79
80 //#define SOC_Reg                          mpADDR(USB_BASE_ADDR_SOC)
81
82 #define cSOC_USB_OFST                    (0x100)
83
84 #define ZM_CBUS_FIFO_SIZE_OFFSET    (cSOC_USB_OFST)     //OFFSET 0
85
86 #define cSOC_CBUS_CTL_OFFSET             0xF0
87
88 #define ZM_FUSB_BASE                     USB_CTRL_BASE_ADDRESS
89
90 #define ZM_MAIN_CTRL_OFFSET              0x00
91 #define ZM_DEVICE_ADDRESS_OFFSET         0x01
92 #define ZM_TEST_OFFSET                   0x02
93 #define ZM_PHY_TEST_SELECT_OFFSET        0x08
94 #define ZM_VDR_SPECIFIC_MODE_OFFSET       0x0A
95 #define ZM_CX_CONFIG_STATUS_OFFSET       0x0B
96 #define ZM_EP0_DATA1_OFFSET              0x0C
97 #define ZM_EP0_DATA2_OFFSET              0x0D
98 #define ZM_EP0_DATA_OFFSET               0x0C
99
100 #define ZM_INTR_MASK_BYTE_0_OFFSET       0x11
101 #define ZM_INTR_MASK_BYTE_1_OFFSET       0x12
102 #define ZM_INTR_MASK_BYTE_2_OFFSET       0x13
103 #define ZM_INTR_MASK_BYTE_3_OFFSET       0x14
104 #define ZM_INTR_MASK_BYTE_4_OFFSET       0x15
105 #define ZM_INTR_MASK_BYTE_5_OFFSET       0x16
106 #define ZM_INTR_MASK_BYTE_6_OFFSET       0x17
107 #define ZM_INTR_MASK_BYTE_7_OFFSET       0x18
108
109 #define ZM_INTR_GROUP_OFFSET             0x20
110 #define ZM_INTR_SOURCE_0_OFFSET          0x21
111 #define ZM_INTR_SOURCE_1_OFFSET          0x22
112 #define ZM_INTR_SOURCE_2_OFFSET          0x23
113 #define ZM_INTR_SOURCE_3_OFFSET          0x24
114 #define ZM_INTR_SOURCE_4_OFFSET          0x25
115 #define ZM_INTR_SOURCE_5_OFFSET          0x26
116 #define ZM_INTR_SOURCE_6_OFFSET          0x27
117 #define ZM_INTR_SOURCE_7_OFFSET          0x28
118
119 #define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET    0x3F
120 #define ZM_EP_IN_MAX_SIZE_LOW_OFFSET     0x3E
121
122 #define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET   0x5F
123 #define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET    0x5E
124
125 #define ZM_EP3_BYTE_COUNT_HIGH_OFFSET    0xAE
126 #define ZM_EP3_BYTE_COUNT_LOW_OFFSET     0xBE
127 #define ZM_EP4_BYTE_COUNT_HIGH_OFFSET    0xAF
128 #define ZM_EP4_BYTE_COUNT_LOW_OFFSET     0xBF
129
130 #define ZM_EP3_DATA_OFFSET               0xF8
131 #define ZM_EP4_DATA_OFFSET               0xFC
132
133 #define ZM_SOC_USB_MODE_CTRL_OFFSET      0x108
134 #define ZM_SOC_USB_MAX_AGGREGATE_OFFSET  0x110
135 #define ZM_SOC_USB_TIME_CTRL_OFFSET      0x114
136 #define ZM_SOC_USB_DMA_RESET_OFFSET      0x118
137
138 #define ZM_ADDR_CONV                     0x0
139
140 #define ZM_CBUS_FIFO_SIZE_REG                   (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV)
141                                                 
142 #define ZM_CBUS_CTRL_REG                                (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV)
143
144 #define ZM_MAIN_CTRL_REG                                (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV)
145
146 #define ZM_DEVICE_ADDRESS_REG                   (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV)
147
148 #define ZM_TEST_REG                                             (ZM_TEST_OFFSET^ZM_ADDR_CONV)
149
150 #define ZM_PHY_TEST_SELECT_REG                  (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV)))
151
152 #define ZM_CX_CONFIG_STATUS_REG                 (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV)
153
154 #define ZM_EP0_DATA1_REG                                (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV)))
155
156 #define ZM_EP0_DATA2_REG                                (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV)
157
158 #define ZM_EP0_DATA_REG                                 (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV)
159
160 #define ZM_INTR_MASK_BYTE_0_REG                 (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV)
161
162 #define ZM_INTR_MASK_BYTE_1_REG                 (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV)
163
164 #define ZM_INTR_MASK_BYTE_2_REG                 (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV)
165
166 #define ZM_INTR_MASK_BYTE_3_REG                 (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV)
167
168 #define ZM_INTR_MASK_BYTE_4_REG                 (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV)
169
170 #define ZM_INTR_MASK_BYTE_5_REG                 (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV)
171
172 #define ZM_INTR_MASK_BYTE_6_REG                 (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV)
173
174 #define ZM_INTR_MASK_BYTE_7_REG                 (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV)
175
176 #define ZM_INTR_SOURCE_0_REG                    (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV)
177
178 #define ZM_INTR_SOURCE_1_REG                    (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV)
179
180 #define ZM_INTR_SOURCE_2_REG                    (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV)
181
182 #define ZM_INTR_SOURCE_3_REG                    (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV)
183     
184 #define ZM_INTR_SOURCE_4_REG                    (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV)
185
186 #define ZM_INTR_SOURCE_5_REG                    (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV)
187
188 #define ZM_INTR_SOURCE_6_REG                    (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV)
189
190 #define ZM_INTR_SOURCE_7_REG                    (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV)
191
192 #define ZM_INTR_GROUP_REG                               (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV)))
193
194 #define ZM_EP3_BYTE_COUNT_HIGH_REG              (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
195
196 #define ZM_EP3_BYTE_COUNT_LOW_REG               (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
197
198 #define ZM_EP4_BYTE_COUNT_HIGH_REG              (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV)
199
200 #define ZM_EP4_BYTE_COUNT_LOW_REG               (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV)
201
202 #define ZM_EP3_DATA_REG                                 (ZM_EP3_DATA_OFFSET)
203
204 #define ZM_EP4_DATA_REG                                 (ZM_EP4_DATA_OFFSET)
205
206 #define ZM_SOC_USB_MODE_CTRL_REG                (ZM_SOC_USB_MODE_CTRL_OFFSET)
207
208 #define ZM_SOC_USB_MAX_AGGREGATE_REG    (ZM_SOC_USB_MAX_AGGREGATE_OFFSET)
209
210 #define ZM_SOC_USB_TIME_CTRL_REG                (ZM_SOC_USB_TIME_CTRL_OFFSET)
211
212 #define bmHIGH_SPEED                    BIT6
213 #define bmCWR_BUF_END                   BIT1
214
215 #define mUsbEP0DataRd1()                (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET))
216 //#define mUsbEP0DataRd2()              ZM_EP0_DATA2_REG
217 //#define mUsbEP0DataRd3()              ZM_EP0_DATA3_REG
218 //#define mUsbEP0DataRd4()              ZM_EP0_DATA4_REG
219 #define mUsbEP0DataWr1(data)            (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data))
220 #define mUsbEP0DataWr2(data)            (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data))
221
222 #define mGetByte0(data)                 ( data & 0xff )
223 #define mGetByte1(data)                 ( (data >> 8) & 0xff )
224 #define mGetByte2(data)                 ( (data >> 16) & 0xff )
225 #define mGetByte3(data)                 ( (data >> 24) & 0xff )
226
227 //#define mUsbHighSpeedST()             (ZM_MAIN_CTRL_REG & BIT6)
228 //#define mUsbCfgST()                   (ZM_DEVICE_ADDRESS_REG & BIT7)
229 //#define mUsbApWrEnd()                 (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
230 //#define mUsbApRdEnd()                 (ZM_CBUS_CTRL_REG = bmCWR_BUF_END)
231
232 #define mUsbHighSpeedST()               (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6)
233 #define mUsbCfgST()                     (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7)
234 #define mUsbApWrEnd()                   (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
235 #define mUsbApRdEnd()                   (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END)
236
237 #define mUsbRmWkupST()                  USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
238                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0)
239 #define mUsbRmWkupClr()                 USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
240                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0)
241 #define mUsbRmWkupSet()                 USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
242                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0)
243                                                                                  
244 #define mUsbGlobIntEnable()             USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \
245                                                                                         USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2)
246
247 #define mUSB_REG_OUT_INT_ENABLE()       USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
248                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
249 #define mUSB_REG_OUT_INT_DISABLE()      USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
250                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0)
251 #define mUSB_STATUS_IN_INT_ENABLE()     USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
252                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
253 #define mUSB_STATUS_IN_INT_DISABLE()    USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
254                                                                                         USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
255 //                                                                                      USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40)
256
257 #define mUSB_EP3_XFER_DONE()            USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \
258                                                                                         USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08)
259
260
261
262 #define HS_C1_I0_A0_EP1_MAX_PACKET              MX_PA_SZ_512
263 #define HS_C1_I0_A0_EP1_bInterval       00
264
265 #define HS_C1_I0_A0_EP_NUMBER           0x06
266 #define HS_C1_I0_A0_EP_LENGTH           (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
267 #define HS_C1_I0_ALT_LENGTH             (HS_C1_I0_A0_EP_LENGTH)
268 #define HS_C1_INTERFACE_LENGTH          (HS_C1_I0_ALT_LENGTH)
269
270 #define HS_C1_CONFIG_TOTAL_LENGTH       (CONFIG_LENGTH + INTERFACE_LENGTH +  HS_C1_INTERFACE_LENGTH)
271 #define FS_C1_CONFIG_TOTAL_LENGTH       (CONFIG_LENGTH + INTERFACE_LENGTH +  FS_C1_INTERFACE_LENGTH)
272
273 #define FS_C1_I0_A0_EP1_MAX_PACKET      MX_PA_SZ_64
274 //#define FS_C1_I0_A0_EP1_bInterval       HS_C1_I0_A0_EP1_bInterval
275
276 #define HS_CONFIGURATION_NUMBER         1
277 #define FS_CONFIGURATION_NUMBER         1
278
279 #define fDOUBLE_BUF                     1
280 #define fDOUBLE_BUF_IN                  1
281
282 #define fFLASH_DISK                     0
283 #define fENABLE_ISO                     0
284
285 #if (HS_CONFIGURATION_NUMBER >= 1)
286     // Configuration 0X01
287     #define HS_C1_INTERFACE_NUMBER      0x01
288     #define HS_C1                       0x01
289     #define HS_C1_iConfiguration        0x00
290     #define HS_C1_bmAttribute           0x80
291     #if !(fFLASH_DISK && !fFLASH_BOOT)
292     #define HS_C1_iMaxPower             0xFA
293     #else
294     #define HS_C1_iMaxPower             0x32
295     #endif
296
297     #if (HS_C1_INTERFACE_NUMBER >= 1)
298         // Interface 0
299         #define HS_C1_I0_ALT_NUMBER     0X01
300         #if (HS_C1_I0_ALT_NUMBER >= 1) 
301             // AlternateSetting 0X00
302             #define HS_C1_I0_A0_bInterfaceNumber   0X00
303             #define HS_C1_I0_A0_bAlternateSetting  0X00
304         //JWEI 2003/07/14
305             //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
306             #define HS_C1_I0_A0_EP_NUMBER          0x06
307             //#else
308             //#define HS_C1_I0_A0_EP_NUMBER          0X03
309             //#endif
310             #if !(fFLASH_DISK && !fFLASH_BOOT)
311             #define HS_C1_I0_A0_bInterfaceClass    0XFF
312             #define HS_C1_I0_A0_bInterfaceSubClass 0X00
313             #define HS_C1_I0_A0_bInterfaceProtocol 0X00
314             #else
315             #define HS_C1_I0_A0_bInterfaceClass    0X08
316             #define HS_C1_I0_A0_bInterfaceSubClass 0X06
317             #define HS_C1_I0_A0_bInterfaceProtocol 0X50
318             #endif
319             #define HS_C1_I0_A0_iInterface         0X00
320
321             #if (HS_C1_I0_A0_EP_NUMBER >= 1)
322                 //EP0X01
323                 #define HS_C1_I0_A0_EP1_BLKSIZE    BLK512BYTE
324             //JWEI 2003/05/19
325                 #if fDOUBLE_BUF
326                 #define HS_C1_I0_A0_EP1_BLKNO      DOUBLE_BLK
327                 #else
328                 #define HS_C1_I0_A0_EP1_BLKNO      SINGLE_BLK
329                 #endif
330                 #define HS_C1_I0_A0_EP1_DIRECTION  DIRECTION_OUT
331                 #define HS_C1_I0_A0_EP1_TYPE       TF_TYPE_BULK
332             //JWEI 2003/05/07
333                 #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512
334                 #define HS_C1_I0_A0_EP1_bInterval  00
335             #endif
336             #if (HS_C1_I0_A0_EP_NUMBER >= 2)
337                 //EP0X02
338                 #define HS_C1_I0_A0_EP2_BLKSIZE    BLK512BYTE
339             //JWEI 2003/08/20
340                 #if fDOUBLE_BUF_IN
341                 #define HS_C1_I0_A0_EP2_BLKNO      DOUBLE_BLK
342                 #else
343                 #define HS_C1_I0_A0_EP2_BLKNO      SINGLE_BLK
344                 #endif
345                 #define HS_C1_I0_A0_EP2_DIRECTION  DIRECTION_IN
346                 #define HS_C1_I0_A0_EP2_TYPE       TF_TYPE_BULK
347                 #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512
348                 #define HS_C1_I0_A0_EP2_bInterval  00
349             #endif
350             #if (HS_C1_I0_A0_EP_NUMBER >= 3)
351                 //EP0X03
352                 #define HS_C1_I0_A0_EP3_BLKSIZE    BLK64BYTE
353                 #define HS_C1_I0_A0_EP3_BLKNO      SINGLE_BLK
354                 #define HS_C1_I0_A0_EP3_DIRECTION  DIRECTION_IN
355                 #define HS_C1_I0_A0_EP3_TYPE       TF_TYPE_INTERRUPT
356                 #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040
357                 #define HS_C1_I0_A0_EP3_bInterval  01
358             #endif
359         // Note: HS Bulk type require max pkt size = 512
360         //       ==> must use Interrupt type for max pkt size = 64
361             #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
362                 //EP0X04
363                 #define HS_C1_I0_A0_EP4_BLKSIZE    BLK64BYTE
364                 #define HS_C1_I0_A0_EP4_BLKNO      SINGLE_BLK
365                 #define HS_C1_I0_A0_EP4_DIRECTION  DIRECTION_OUT
366                 #define HS_C1_I0_A0_EP4_TYPE       TF_TYPE_INTERRUPT
367                 #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040
368                 #define HS_C1_I0_A0_EP4_bInterval  01
369             #endif
370             #if (HS_C1_I0_A0_EP_NUMBER >= 5)
371                 //EP0X04
372                 #define HS_C1_I0_A0_EP5_BLKSIZE    BLK512BYTE
373                 #if fDOUBLE_BUF
374                 #define HS_C1_I0_A0_EP5_BLKNO      DOUBLE_BLK
375                 #else
376                 #define HS_C1_I0_A0_EP5_BLKNO      SINGLE_BLK
377                 #endif
378                 #define HS_C1_I0_A0_EP5_DIRECTION  DIRECTION_OUT
379                 #define HS_C1_I0_A0_EP5_TYPE       TF_TYPE_BULK
380                 #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512
381                 #define HS_C1_I0_A0_EP5_bInterval  00
382             #endif
383             #if (HS_C1_I0_A0_EP_NUMBER >= 6)
384                 //EP0X04
385                 #define HS_C1_I0_A0_EP6_BLKSIZE    BLK512BYTE
386                 #if fDOUBLE_BUF
387                 #define HS_C1_I0_A0_EP6_BLKNO      DOUBLE_BLK
388                 #else
389                 #define HS_C1_I0_A0_EP6_BLKNO      SINGLE_BLK
390                 #endif
391                 #define HS_C1_I0_A0_EP6_DIRECTION  DIRECTION_OUT
392                 #define HS_C1_I0_A0_EP6_TYPE       TF_TYPE_BULK
393                 #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512
394                 #define HS_C1_I0_A0_EP6_bInterval  00
395             #endif
396         #endif
397     #endif
398 #endif
399
400 #if (HS_CONFIGURATION_NUMBER >= 1)
401     // Configuration 1
402     #if (HS_C1_INTERFACE_NUMBER >= 1)
403         // Interface 0
404         #if (HS_C1_I0_ALT_NUMBER >= 1)
405             // AlternateSetting 0
406             #define HS_C1_I0_A0_EP_LENGTH           (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER)
407             #if (HS_C1_I0_A0_EP_NUMBER >= 1)
408                 // EP1
409                 #define HS_C1_I0_A0_EP1_FIFO_START  FIFO0
410                 #define HS_C1_I0_A0_EP1_FIFO_NO     (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE)
411                 #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE)
412                 #define HS_C1_I0_A0_EP1_FIFO_MAP    (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
413                 #define HS_C1_I0_A0_EP1_MAP         (HS_C1_I0_A0_EP1_FIFO_START |   (HS_C1_I0_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION)))
414             #endif
415             #if (HS_C1_I0_A0_EP_NUMBER >= 2)
416                 // EP2
417                 #if fDOUBLE_BUF
418                 #define HS_C1_I0_A0_EP2_FIFO_START  (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO)
419                 #else
420                 #define HS_C1_I0_A0_EP2_FIFO_START  FIFO2
421                 #endif
422                 #define HS_C1_I0_A0_EP2_FIFO_NO     (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE)
423                 #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE)
424                 #define HS_C1_I0_A0_EP2_FIFO_MAP    (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
425                 #define HS_C1_I0_A0_EP2_MAP         (HS_C1_I0_A0_EP2_FIFO_START |   (HS_C1_I0_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION)))
426             #endif
427             #if (HS_C1_I0_A0_EP_NUMBER >= 3)
428                 // EP3
429             //JWEI 2003/07/15
430             //    #define HS_C1_I0_A0_EP3_FIFO_START  (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
431                 #define HS_C1_I0_A0_EP3_FIFO_START  FIFO14
432                 #define HS_C1_I0_A0_EP3_FIFO_NO     (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE)
433                 #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE)
434                 #define HS_C1_I0_A0_EP3_FIFO_MAP    (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
435                 #define HS_C1_I0_A0_EP3_MAP         (HS_C1_I0_A0_EP3_FIFO_START |   (HS_C1_I0_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION)))
436             #endif
437             #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
438                 // EP4
439                 #define HS_C1_I0_A0_EP4_FIFO_START  (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO)
440                 #define HS_C1_I0_A0_EP4_FIFO_NO     (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE)
441                 #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE)
442                 #define HS_C1_I0_A0_EP4_FIFO_MAP    (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
443                 #define HS_C1_I0_A0_EP4_MAP         (HS_C1_I0_A0_EP4_FIFO_START |   (HS_C1_I0_A0_EP4_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION)))
444             #endif
445             #if (HS_C1_I0_A0_EP_NUMBER >= 5)
446                 // EP5
447                 #define HS_C1_I0_A0_EP5_FIFO_START  (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO)
448                 #define HS_C1_I0_A0_EP5_FIFO_NO     (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE)
449                 #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE)
450                 #define HS_C1_I0_A0_EP5_FIFO_MAP    (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
451                 #define HS_C1_I0_A0_EP5_MAP         (HS_C1_I0_A0_EP5_FIFO_START |   (HS_C1_I0_A0_EP5_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION)))
452             #endif
453             #if (HS_C1_I0_A0_EP_NUMBER >= 6)
454                 // EP5
455                 #define HS_C1_I0_A0_EP6_FIFO_START  (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO)
456                 #define HS_C1_I0_A0_EP6_FIFO_NO     (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE)
457                 #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE)
458                 #define HS_C1_I0_A0_EP6_FIFO_MAP    (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
459                 #define HS_C1_I0_A0_EP6_MAP         (HS_C1_I0_A0_EP6_FIFO_START |   (HS_C1_I0_A0_EP6_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION)))
460             #endif
461         #endif
462
463         #if (HS_C1_I0_ALT_NUMBER >= 2)
464             // AlternateSetting 1
465             #define HS_C1_I0_A1_EP_LENGTH           (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER)
466             #if (HS_C1_I0_A1_EP_NUMBER >= 1)
467                 // EP1
468                 #define HS_C1_I0_A1_EP1_FIFO_START  FIFO0
469                 #define HS_C1_I0_A1_EP1_FIFO_NO     (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE)
470                 #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE)
471                 #define HS_C1_I0_A1_EP1_FIFO_MAP    (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
472                 #define HS_C1_I0_A1_EP1_MAP         (HS_C1_I0_A1_EP1_FIFO_START |   (HS_C1_I0_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION)))
473             #endif
474             #if (HS_C1_I0_A1_EP_NUMBER >= 2)
475                 // EP2
476                 #define HS_C1_I0_A1_EP2_FIFO_START  (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO)
477                 #define HS_C1_I0_A1_EP2_FIFO_NO     (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE)
478                 #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE)
479                 #define HS_C1_I0_A1_EP2_FIFO_MAP    (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
480                 #define HS_C1_I0_A1_EP2_MAP         (HS_C1_I0_A1_EP2_FIFO_START |   (HS_C1_I0_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION)))
481             #endif
482             #if (HS_C1_I0_A1_EP_NUMBER >= 3)
483                 // EP3
484                 #define HS_C1_I0_A1_EP3_FIFO_START  (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO)
485                 #define HS_C1_I0_A1_EP3_FIFO_NO     (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE)
486                 #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE)
487                 #define HS_C1_I0_A1_EP3_FIFO_MAP    (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
488                 #define HS_C1_I0_A1_EP3_MAP         (HS_C1_I0_A1_EP3_FIFO_START |   (HS_C1_I0_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION)))
489             #endif
490         #endif
491
492         #if (HS_C1_I0_ALT_NUMBER == 1)
493             #define HS_C1_I0_ALT_LENGTH             (HS_C1_I0_A0_EP_LENGTH)
494         #elif (HS_C1_I0_ALT_NUMBER == 2)
495             #define HS_C1_I0_ALT_LENGTH             (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH)
496         #endif
497     #endif
498
499     #if (HS_C1_INTERFACE_NUMBER >= 2)
500         // Interface 1
501         #if (HS_C1_I1_ALT_NUMBER >= 1)
502             // AlternateSetting 0
503             #define HS_C1_I1_A0_EP_LENGTH           (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER)
504             #if (HS_C1_I1_A0_EP_NUMBER >= 1)
505                 // EP1
506                 #define HS_C1_I1_A0_EP1_FIFO_START  FIFO0
507                 #define HS_C1_I1_A0_EP1_FIFO_NO     (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE)
508                 #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE)
509                 #define HS_C1_I1_A0_EP1_FIFO_MAP    (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
510                 #define HS_C1_I1_A0_EP1_MAP         (HS_C1_I1_A0_EP1_FIFO_START |   (HS_C1_I1_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION)))
511             #endif
512             #if (HS_C1_I1_A0_EP_NUMBER >= 2)
513                 // EP2
514                 #define HS_C1_I1_A0_EP2_FIFO_START  (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO)
515                 #define HS_C1_I1_A0_EP2_FIFO_NO     (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE)
516                 #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE)
517                 #define HS_C1_I1_A0_EP2_FIFO_MAP    (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
518                 #define HS_C1_I1_A0_EP2_MAP         (HS_C1_I1_A0_EP2_FIFO_START |   (HS_C1_I1_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION)))
519             #endif
520             #if (HS_C1_I1_A0_EP_NUMBER >= 3)
521                 // EP3
522                 #define HS_C1_I1_A0_EP3_FIFO_START  (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO)
523                 #define HS_C1_I1_A0_EP3_FIFO_NO     (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE)
524                 #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE)
525                 #define HS_C1_I1_A0_EP3_FIFO_MAP    (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
526                 #define HS_C1_I1_A0_EP3_MAP         (HS_C1_I1_A0_EP3_FIFO_START |   (HS_C1_I1_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION)))
527             #endif
528         #endif
529
530         #if (HS_C1_I1_ALT_NUMBER >= 2)
531             // AlternateSetting 1
532             #define HS_C1_I1_A1_EP_LENGTH           (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER)
533             #if (HS_C1_I1_A1_EP_NUMBER >= 1)
534                 // EP1
535                 #define HS_C1_I1_A1_EP1_FIFO_START  FIFO0
536                 #define HS_C1_I1_A1_EP1_FIFO_NO     (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE)
537                 #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE)
538                 #define HS_C1_I1_A1_EP1_FIFO_MAP    (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
539                 #define HS_C1_I1_A1_EP1_MAP         (HS_C1_I1_A1_EP1_FIFO_START |   (HS_C1_I1_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION)))
540             #endif
541             #if (HS_C1_I1_A1_EP_NUMBER >= 2)
542                 // EP2
543                 #define HS_C1_I1_A1_EP2_FIFO_START  (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO)
544                 #define HS_C1_I1_A1_EP2_FIFO_NO     (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE)
545                 #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE)
546                 #define HS_C1_I1_A1_EP2_FIFO_MAP    (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
547                 #define HS_C1_I1_A1_EP2_MAP         (HS_C1_I1_A1_EP2_FIFO_START |   (HS_C1_I1_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION)))
548             #endif
549             #if (HS_C1_I1_A1_EP_NUMBER >= 3)
550                 // EP3
551                 #define HS_C1_I1_A1_EP3_FIFO_START  (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO)
552                 #define HS_C1_I1_A1_EP3_FIFO_NO     (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE)
553                 #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE)
554                 #define HS_C1_I1_A1_EP3_FIFO_MAP    (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
555                 #define HS_C1_I1_A1_EP3_MAP         (HS_C1_I1_A1_EP3_FIFO_START |   (HS_C1_I1_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION)))
556             #endif
557         #endif
558
559         #if (HS_C1_I1_ALT_NUMBER == 1)
560             #define HS_C1_I1_ALT_LENGTH             (HS_C1_I1_A0_EP_LENGTH)
561         #elif (HS_C1_I1_ALT_NUMBER == 2)
562             #define HS_C1_I1_ALT_LENGTH             (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH)
563         #endif
564     #endif
565
566     #if (HS_C1_INTERFACE_NUMBER == 1)
567         #define HS_C1_INTERFACE_LENGTH              (HS_C1_I0_ALT_LENGTH)
568     #elif (HS_C1_INTERFACE_NUMBER == 2)
569         #define HS_C1_INTERFACE_LENGTH              (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH)
570     #endif
571 #endif
572
573 #if (FS_CONFIGURATION_NUMBER >= 1)
574     // Configuration 0X01
575     #define FS_C1_INTERFACE_NUMBER  0X01
576     #define FS_C1                   0X01
577     #define FS_C1_iConfiguration    0X00
578     #define FS_C1_bmAttribute       0X80
579     #define FS_C1_iMaxPower         0XFA
580
581     #if (FS_C1_INTERFACE_NUMBER >= 1)
582         // Interface 0
583         #define FS_C1_I0_ALT_NUMBER    0X01
584         #if (FS_C1_I0_ALT_NUMBER >= 1)
585             // AlternateSetting 0X00
586             #define FS_C1_I0_A0_bInterfaceNumber   0X00
587             #define FS_C1_I0_A0_bAlternateSetting  0X00
588         //JWEI 2003/07/14
589             //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT)
590             #define FS_C1_I0_A0_EP_NUMBER          0x05
591             //#else
592             //#define FS_C1_I0_A0_EP_NUMBER          0X03
593             //#endif
594             #if !(fFLASH_DISK && !fFLASH_BOOT)
595             #define FS_C1_I0_A0_bInterfaceClass    0XFF
596             #define FS_C1_I0_A0_bInterfaceSubClass 0X00
597             #define FS_C1_I0_A0_bInterfaceProtocol 0X00
598             #else
599             #define FS_C1_I0_A0_bInterfaceClass    0X08
600             #define FS_C1_I0_A0_bInterfaceSubClass 0X06
601             #define FS_C1_I0_A0_bInterfaceProtocol 0X50
602             #endif
603             #define FS_C1_I0_A0_iInterface         0X00
604
605             #if (FS_C1_I0_A0_EP_NUMBER >= 1)
606                 //EP0X01
607                 #define FS_C1_I0_A0_EP1_BLKSIZE    BLK512BYTE
608             //JWEI 2003/05/19
609                 #if fDOUBLE_BUF
610                 #define FS_C1_I0_A0_EP1_BLKNO      DOUBLE_BLK
611                 #else
612                 #define FS_C1_I0_A0_EP1_BLKNO      SINGLE_BLK
613                 #endif
614                 #define FS_C1_I0_A0_EP1_DIRECTION  DIRECTION_OUT
615                 #define FS_C1_I0_A0_EP1_TYPE       TF_TYPE_BULK
616             //JWEI 2003/05/07
617                 #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64
618                 #define FS_C1_I0_A0_EP1_bInterval  00
619             #endif
620             #if (FS_C1_I0_A0_EP_NUMBER >= 2)
621                 //EP0X02
622                 #define FS_C1_I0_A0_EP2_BLKSIZE    BLK512BYTE
623             //JWEI 2003/08/20
624                 #if fDOUBLE_BUF_IN
625                 #define FS_C1_I0_A0_EP2_BLKNO      DOUBLE_BLK
626                 #else
627                 #define FS_C1_I0_A0_EP2_BLKNO      SINGLE_BLK
628                 #endif
629                 #define FS_C1_I0_A0_EP2_DIRECTION  DIRECTION_IN
630                 #define FS_C1_I0_A0_EP2_TYPE       TF_TYPE_BULK
631                 #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64
632                 #define FS_C1_I0_A0_EP2_bInterval  00
633             #endif
634             #if (FS_C1_I0_A0_EP_NUMBER >= 3)
635                 //EP0X03
636                 #define FS_C1_I0_A0_EP3_BLKSIZE    BLK64BYTE
637                 #define FS_C1_I0_A0_EP3_BLKNO      SINGLE_BLK
638                 #define FS_C1_I0_A0_EP3_DIRECTION  DIRECTION_IN
639                 #define FS_C1_I0_A0_EP3_TYPE       TF_TYPE_INTERRUPT
640                 #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040
641                 #define FS_C1_I0_A0_EP3_bInterval  01
642             #endif
643             #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
644                 //EP0X04
645                 #define FS_C1_I0_A0_EP4_BLKSIZE    BLK64BYTE
646                 #define FS_C1_I0_A0_EP4_BLKNO      SINGLE_BLK
647                 #define FS_C1_I0_A0_EP4_DIRECTION  DIRECTION_OUT
648                 #define FS_C1_I0_A0_EP4_TYPE       TF_TYPE_BULK
649                 #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040
650                 #define FS_C1_I0_A0_EP4_bInterval  00
651             #endif
652             #if (FS_C1_I0_A0_EP_NUMBER >= 5)
653                 //EP0X04
654                 #define FS_C1_I0_A0_EP5_BLKSIZE    BLK512BYTE
655                 #if fDOUBLE_BUF_IN
656                 #define FS_C1_I0_A0_EP5_BLKNO      DOUBLE_BLK
657                 #else
658                 #define FS_C1_I0_A0_EP5_BLKNO      SINGLE_BLK
659                 #endif
660                 #define FS_C1_I0_A0_EP5_DIRECTION  DIRECTION_OUT
661                 #define FS_C1_I0_A0_EP5_TYPE       TF_TYPE_BULK
662                 #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040
663                 #define FS_C1_I0_A0_EP5_bInterval  00
664             #endif
665             #if (FS_C1_I0_A0_EP_NUMBER >= 6)
666                 //EP0X04
667                 #define FS_C1_I0_A0_EP6_BLKSIZE    BLK512BYTE
668                 #if fDOUBLE_BUF_IN
669                 #define FS_C1_I0_A0_EP6_BLKNO      DOUBLE_BLK
670                 #else
671                 #define FS_C1_I0_A0_EP6_BLKNO      SINGLE_BLK
672                 #endif
673                 #define FS_C1_I0_A0_EP6_DIRECTION  DIRECTION_OUT
674                 #define FS_C1_I0_A0_EP6_TYPE       TF_TYPE_BULK
675                 #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040
676                 #define FS_C1_I0_A0_EP6_bInterval  00
677             #endif
678         #endif
679     #endif
680 #endif
681
682 #if (FS_CONFIGURATION_NUMBER >= 1)
683     // Configuration 1
684     #if (FS_C1_INTERFACE_NUMBER >= 1)
685         // Interface 0
686         #if (FS_C1_I0_ALT_NUMBER >= 1)
687             // AlternateSetting 0
688             #define FS_C1_I0_A0_EP_LENGTH           (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER)
689             #if (FS_C1_I0_A0_EP_NUMBER >= 1)
690                 // EP1
691                 #define FS_C1_I0_A0_EP1_FIFO_START  FIFO0
692                 #define FS_C1_I0_A0_EP1_FIFO_NO     (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE)
693                 #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE)
694                 #define FS_C1_I0_A0_EP1_FIFO_MAP    (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1)
695                 #define FS_C1_I0_A0_EP1_MAP         (FS_C1_I0_A0_EP1_FIFO_START |   (FS_C1_I0_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION)))
696             #endif
697             #if (FS_C1_I0_A0_EP_NUMBER >= 2)
698                 // EP2
699                 #define FS_C1_I0_A0_EP2_FIFO_START  (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO)
700                 #define FS_C1_I0_A0_EP2_FIFO_NO     (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE)
701                 #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE)
702                 #define FS_C1_I0_A0_EP2_FIFO_MAP    (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2)
703                 #define FS_C1_I0_A0_EP2_MAP         (FS_C1_I0_A0_EP2_FIFO_START |   (FS_C1_I0_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION)))
704             #endif
705             #if (FS_C1_I0_A0_EP_NUMBER >= 3)
706                 // EP3
707             //JWEI 2003/07/15
708             //    #define FS_C1_I0_A0_EP3_FIFO_START  (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
709                 #define FS_C1_I0_A0_EP3_FIFO_START  FIFO14
710                 #define FS_C1_I0_A0_EP3_FIFO_NO     (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE)
711                 #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE)
712                 #define FS_C1_I0_A0_EP3_FIFO_MAP    (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3)
713                 #define FS_C1_I0_A0_EP3_MAP         (FS_C1_I0_A0_EP3_FIFO_START |   (FS_C1_I0_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION)))
714             #endif
715             #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK
716                 // EP4
717                 #define FS_C1_I0_A0_EP4_FIFO_START  (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO)
718                 #define FS_C1_I0_A0_EP4_FIFO_NO     (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE)
719                 #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE)
720                 #define FS_C1_I0_A0_EP4_FIFO_MAP    (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4)
721                 #define FS_C1_I0_A0_EP4_MAP         (FS_C1_I0_A0_EP4_FIFO_START |   (FS_C1_I0_A0_EP4_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION)))
722             #endif
723             #if (FS_C1_I0_A0_EP_NUMBER >= 5)
724                 // EP5
725                 #define FS_C1_I0_A0_EP5_FIFO_START  (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO)
726                 #define FS_C1_I0_A0_EP5_FIFO_NO     (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE)
727                 #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE)
728                 #define FS_C1_I0_A0_EP5_FIFO_MAP    (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5)
729                 #define FS_C1_I0_A0_EP5_MAP         (FS_C1_I0_A0_EP5_FIFO_START |   (FS_C1_I0_A0_EP5_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION)))
730             #endif
731             #if (FS_C1_I0_A0_EP_NUMBER >= 6)
732                 // EP5
733                 #define FS_C1_I0_A0_EP6_FIFO_START  (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO)
734                 #define FS_C1_I0_A0_EP6_FIFO_NO     (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE)
735                 #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE)
736                 #define FS_C1_I0_A0_EP6_FIFO_MAP    (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6)
737                 #define FS_C1_I0_A0_EP6_MAP         (FS_C1_I0_A0_EP6_FIFO_START |   (FS_C1_I0_A0_EP6_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION)))
738             #endif
739         #endif
740
741         #if (FS_C1_I0_ALT_NUMBER >= 2)
742             // AlternateSetting 1
743             #define FS_C1_I0_A1_EP_LENGTH           (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER)
744             #if (FS_C1_I0_A1_EP_NUMBER >= 1)
745                 // EP1
746                 #define FS_C1_I0_A1_EP1_FIFO_START  FIFO0
747                 #define FS_C1_I0_A1_EP1_FIFO_NO     (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE)
748                 #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE)
749                 #define FS_C1_I0_A1_EP1_FIFO_MAP    (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1)
750                 #define FS_C1_I0_A1_EP1_MAP         (FS_C1_I0_A1_EP1_FIFO_START |   (FS_C1_I0_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION)))
751             #endif
752             #if (FS_C1_I0_A1_EP_NUMBER >= 2)
753                 // EP2
754                 #define FS_C1_I0_A1_EP2_FIFO_START  (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO)
755                 #define FS_C1_I0_A1_EP2_FIFO_NO     (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE)
756                 #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE)
757                 #define FS_C1_I0_A1_EP2_FIFO_MAP    (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2)
758                 #define FS_C1_I0_A1_EP2_MAP         (FS_C1_I0_A1_EP2_FIFO_START |   (FS_C1_I0_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION)))
759             #endif
760             #if (FS_C1_I0_A1_EP_NUMBER >= 3)
761                 // EP3
762                 #define FS_C1_I0_A1_EP3_FIFO_START  (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO)
763                 #define FS_C1_I0_A1_EP3_FIFO_NO     (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE)
764                 #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE)
765                 #define FS_C1_I0_A1_EP3_FIFO_MAP    (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3)
766                 #define FS_C1_I0_A1_EP3_MAP         (FS_C1_I0_A1_EP3_FIFO_START |   (FS_C1_I0_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION)))
767             #endif
768         #endif
769
770         #if (FS_C1_I0_ALT_NUMBER == 1)
771             #define FS_C1_I0_ALT_LENGTH             (FS_C1_I0_A0_EP_LENGTH)
772         #elif (FS_C1_I0_ALT_NUMBER == 2)
773             #define FS_C1_I0_ALT_LENGTH             (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH)
774         #endif
775     #endif
776
777     #if (FS_C1_INTERFACE_NUMBER >= 2)
778         // Interface 1
779         #if (FS_C1_I1_ALT_NUMBER >= 1)
780             // AlternateSetting 0
781             #define FS_C1_I1_A0_EP_LENGTH           (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER)
782             #if (FS_C1_I1_A0_EP_NUMBER >= 1)
783                 // EP1
784                 #define FS_C1_I1_A0_EP1_FIFO_START  FIFO0
785                 #define FS_C1_I1_A0_EP1_FIFO_NO     (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE)
786                 #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE)
787                 #define FS_C1_I1_A0_EP1_FIFO_MAP    (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1)
788                 #define FS_C1_I1_A0_EP1_MAP         (FS_C1_I1_A0_EP1_FIFO_START |   (FS_C1_I1_A0_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION)))
789             #endif
790             #if (FS_C1_I1_A0_EP_NUMBER >= 2)
791                 // EP2
792                 #define FS_C1_I1_A0_EP2_FIFO_START  (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO)
793                 #define FS_C1_I1_A0_EP2_FIFO_NO     (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE)
794                 #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE)
795                 #define FS_C1_I1_A0_EP2_FIFO_MAP    (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2)
796                 #define FS_C1_I1_A0_EP2_MAP         (FS_C1_I1_A0_EP2_FIFO_START |   (FS_C1_I1_A0_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION)))
797             #endif
798             #if (FS_C1_I1_A0_EP_NUMBER >= 3)
799                 // EP3
800                 #define FS_C1_I1_A0_EP3_FIFO_START  (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO)
801                 #define FS_C1_I1_A0_EP3_FIFO_NO     (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE)
802                 #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE)
803                 #define FS_C1_I1_A0_EP3_FIFO_MAP    (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3)
804                 #define FS_C1_I1_A0_EP3_MAP         (FS_C1_I1_A0_EP3_FIFO_START |   (FS_C1_I1_A0_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION)))
805             #endif
806         #endif
807
808         #if (FS_C1_I1_ALT_NUMBER >= 2)
809             // AlternateSetting 1
810             #define FS_C1_I1_A1_EP_LENGTH           (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER)
811             #if (FS_C1_I1_A1_EP_NUMBER >= 1)
812                 // EP1
813                 #define FS_C1_I1_A1_EP1_FIFO_START  FIFO0
814                 #define FS_C1_I1_A1_EP1_FIFO_NO     (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE)
815                 #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE)
816                 #define FS_C1_I1_A1_EP1_FIFO_MAP    (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1)
817                 #define FS_C1_I1_A1_EP1_MAP         (FS_C1_I1_A1_EP1_FIFO_START |   (FS_C1_I1_A1_EP1_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION)))
818             #endif
819             #if (FS_C1_I1_A1_EP_NUMBER >= 2)
820                 // EP2
821                 #define FS_C1_I1_A1_EP2_FIFO_START  (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO)
822                 #define FS_C1_I1_A1_EP2_FIFO_NO     (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE)
823                 #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE)
824                 #define FS_C1_I1_A1_EP2_FIFO_MAP    (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2)
825                 #define FS_C1_I1_A1_EP2_MAP         (FS_C1_I1_A1_EP2_FIFO_START |   (FS_C1_I1_A1_EP2_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION)))
826             #endif
827             #if (FS_C1_I1_A1_EP_NUMBER >= 3)
828                 // EP3
829                 #define FS_C1_I1_A1_EP3_FIFO_START  (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO)
830                 #define FS_C1_I1_A1_EP3_FIFO_NO     (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE)
831                 #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE)
832                 #define FS_C1_I1_A1_EP3_FIFO_MAP    (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3)
833                 #define FS_C1_I1_A1_EP3_MAP         (FS_C1_I1_A1_EP3_FIFO_START |   (FS_C1_I1_A1_EP3_FIFO_START << 4)   | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION)))
834             #endif
835         #endif
836
837         #if (FS_C1_I1_ALT_NUMBER == 1)
838             #define FS_C1_I1_ALT_LENGTH             (FS_C1_I1_A0_EP_LENGTH)
839         #elif (FS_C1_I1_ALT_NUMBER == 2)
840             #define FS_C1_I1_ALT_LENGTH             (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH)
841         #endif
842     #endif
843
844     #if (FS_C1_INTERFACE_NUMBER == 1)
845         #define FS_C1_INTERFACE_LENGTH              (FS_C1_I0_ALT_LENGTH)
846     #elif (FS_C1_INTERFACE_NUMBER == 2)
847         #define FS_C1_INTERFACE_LENGTH              (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH)
848     #endif
849 #endif
850
851 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
852 #define USB_ENABLE_UP_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
853                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable
854                                                     
855 #define USB_DISABLE_UP_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
856                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable
857
858 #define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
859                                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3)))   // upQ stream mode
860
861 #define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
862                                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3))          // upQ packet mode
863
864 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
865 #define USB_ENABLE_LP_DN_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
866                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1))    // lp downstream DMA enable
867
868 #define USB_DISABLE_LP_DN_DMA()  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,    \
869                                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1)))   // lp downstream DMA disable
870
871 #define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
872                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6)))   // lpQ packet mode
873
874 #define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
875                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6))          // lpQ stream mode
876
877 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
878 #define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,  \
879                                 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8))    // hp downstream DMA enable 
880
881 #define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,  \
882                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8)))  // hp downstream DMA disable 
883
884 #define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
885                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7)))   // hpQ packet mode
886
887 #define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
888                                     (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7))          // hpQ stream mode
889
890 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
891 #define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9))    // mp downstream DMA enable 
892
893 #define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9)))    // mp downstream DMA disable 
894
895 #define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10)))   // hpQ packet mode
896
897 #define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10))          // hpQ stream mode
898
899 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
900
901 #define USB_ENABLE_UP_PACKET_MODE()     USB_DISABLE_UP_DMA();    \
902                                             USB_UP_PACKET_MODE();   \
903                                             USB_ENABLE_UP_DMA();
904
905 #define USB_ENABLE_LP_DN_PACKET_MODE()  USB_DISABLE_LP_DN_DMA();    \
906                                             USB_LP_DN_PACKET_MODE();   \
907                                             USB_ENABLE_LP_DN_DMA()
908
909 #define USB_ENABLE_MP_DN_PACKET_MODE()   USB_DISABLE_MP_DN_DMA();    \
910                                             USB_MP_DN_PACKET_MODE();   \
911                                             USB_ENABLE_MP_DN_DMA();
912
913 #define USB_ENABLE_HP_DN_PACKET_MODE()    USB_DISABLE_HP_DN_DMA();    \
914                                             USB_HP_DN_PACKET_MODE();   \
915                                             USB_ENABLE_HP_DN_DMA();
916
917 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
918 #define USB_ENABLE_UP_STREAM_MODE()    USB_DISABLE_UP_DMA();    \
919                                         USB_UP_STREAM_MODE();   \
920                                         USB_ENABLE_UP_DMA();
921
922 #define USB_ENABLE_LP_DN_STREAM_MODE()    USB_DISABLE_LP_DN_DMA();    \
923                                             USB_LP_DN_STREAM_MODE();   \
924                                             USB_ENABLE_LP_DN_DMA()
925
926 #define USB_ENABLE_MP_DN_STREAM_MODE()    USB_DISABLE_MP_DN_DMA();    \
927                                             USB_MP_DN_STREAM_MODE();   \
928                                             USB_ENABLE_MP_DN_DMA();
929
930 #define USB_ENABLE_HP_DN_STREAM_MODE()    USB_DISABLE_HP_DN_DMA();    \
931                                             USB_HP_DN_STREAM_MODE();   \
932                                             USB_ENABLE_HP_DN_DMA();
933
934 #define USB_STREAM_HOST_BUF_SIZE(size)  USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
935                                                                             (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size)));   
936 #define USB_STREAM_TIMEOUT(time_cnt)    USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt);  // set stream mode timeout critirea
937 #define USB_STREAM_AGG_PKT_CNT(cnt)     USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea
938
939 #endif